CN114401250A - Address allocation method and device - Google Patents
Address allocation method and device Download PDFInfo
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- CN114401250A CN114401250A CN202111607242.3A CN202111607242A CN114401250A CN 114401250 A CN114401250 A CN 114401250A CN 202111607242 A CN202111607242 A CN 202111607242A CN 114401250 A CN114401250 A CN 114401250A
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Abstract
The invention discloses an address allocation method and device, and relates to the technical field of communication. The method is applied to a communication bus which is connected with a master station device and at least one slave station node device to be accessed, and comprises the following steps: when the master station device detects that any slave station node device is accessed to a communication bus, an allocation address query instruction is sent to the any slave station node device; any slave node equipment belongs to at least one slave node equipment to be accessed; and the master station device receives device reply data fed back by any slave station node device according to the allocation address query instruction through a communication bus, and allocates an address to any slave station node device, so that at least one slave station device to be accessed is allocated to the allocation address.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to an address allocation method and device.
Background
At present, because a serial communication bus has the advantages of small number of connecting pins, high system reliability, simple connection and low cost, the serial bus type communication technology has very wide application in the scenes of industrial control, signal acquisition, data communication and the like.
Specifically, the serial bus is generally designed as a communication mode of one master device and a plurality of slave node devices, and the conventional bus design needs to be configured with the node addresses of the slave stations in advance to facilitate the control and polling of the master station. The configuration of the node address of the slave node device generally needs to be completed by designing a dial switch on a circuit.
However, when the number of slave node devices on the serial bus is large, the node addresses of the slave node devices need to be set one by one, so that the node addresses of the slave node devices cannot be configured quickly; in addition, when the serial bus is newly accessed to the slave node device, the slave node device cannot allocate addresses quickly and accurately, so that the efficiency of allocating addresses to the node devices by the serial bus is low.
Disclosure of Invention
The embodiment of the invention provides an address allocation method and device, which are used for improving the address allocation efficiency of node equipment.
In a first aspect, a method for address allocation is provided, which is applied to a communication bus connecting a master device and at least one slave node device to be accessed, and includes:
when the master station device detects that any slave station node device is accessed to a communication bus, an allocation address query instruction is sent to the any slave station node device; any slave node equipment belongs to at least one slave node equipment to be accessed;
and the master station device receives device reply data fed back by any slave station node device according to the allocation address query instruction through a communication bus, and allocates an address to any slave station node device, so that at least one slave station device to be accessed is allocated to the allocation address.
In a possible implementation manner, after the master device performs a data round-robin transmission operation through the communication bus, the first node device accesses the communication bus, and the method further includes:
the master station equipment stops executing the current data round-robin sending operation and sends an address allocation inquiry instruction based on the communication bus;
if the master station device receives device reply data sent by the first node device for the allocation address query instruction, allocating an address for the first node device; the first node device is a node device other than the at least one slave node device.
In a possible implementation, after the second node device accesses the communication bus and before the second node device does not obtain an address allocated to it by the master device, the method further includes:
the master station device detects address allocation demand data sent by the second node device; the address allocation demand data is: the second node device is determined based on non-address allocation related data sent by the master device on the communication bus;
the master station device sends an address allocation inquiry instruction to the second node device on the communication bus based on the address allocation demand data;
and the master station equipment receives equipment reply data sent by the second node equipment aiming at the allocation address inquiry instruction, and allocates an address for the second node equipment.
In one possible embodiment, the method further comprises:
when the master station equipment receives the abnormal information, the master station equipment sends an address allocation inquiry instruction through the communication bus; the abnormal information indicates that the master station device does not receive reply information of the transmitted data, or the received data is data of a non-preset protocol;
and if the master station device receives device reply data sent by the third node device for the allocation address inquiry instruction, allocating an address for the third node device.
In one possible embodiment, before sending an assignment address query instruction to any slave node device when the master device detects that the any slave node device accesses a communication bus, the method further comprises:
the master station device determines whether an address allocation mode condition is satisfied; the address mode allocation condition is that an upper instruction or a mechanical switch selection instruction is received;
when the master station device determines that the address allocation mode is met, the master station device executes an operation of sequentially sending an allocation address query instruction to any slave station node device through the communication bus;
and when the master station device determines that the address allocation mode condition is not met, not executing the operation of sequentially sending an allocation address query instruction to any slave station node device.
In one possible embodiment, the method further comprises:
and when the master station equipment allocates addresses to the slave station node equipment, recording the addresses of the slave station node equipment on the corresponding round-robin address list.
In one possible embodiment, the method further comprises:
and when the master station device does not receive the device reply data within a preset time interval, executing the operation of data round-robin transmission.
In a second aspect, an address assignment apparatus is provided, which is applied to a communication bus connecting a master device and at least one slave node device to be accessed, and includes:
a sending unit, configured to send an allocation address query instruction to any slave node device when the master device detects that any slave node device accesses a communication bus; any slave node equipment belongs to at least one slave node equipment to be accessed;
and the allocating unit is used for receiving the device reply data fed back by any slave node device according to the allocation address query instruction by the master device through a communication bus, and allocating an address to any slave node device, so that at least one slave device to be accessed is allocated to the allocation address.
In a possible implementation manner, after the master device performs the data round-robin transmission operation through the communication bus, the first node device accesses the communication bus, and the apparatus further includes a first processing unit, configured to:
the master station equipment stops executing the current data round-robin sending operation and sends an address allocation inquiry instruction based on the communication bus;
if the master station device receives device reply data sent by the first node device for the allocation address query instruction, allocating an address for the first node device; the first node device is a node device other than the at least one slave node device.
In a possible implementation manner, after the second node device accesses the communication bus and before the second node device does not obtain the address allocated to it by the master device, the apparatus further includes a second processing unit configured to: the master station device detects address allocation demand data sent by the second node device; the address allocation demand data is: the second node device is determined based on non-address allocation related data sent by the master device on the communication bus;
the master station device sends an address allocation inquiry instruction to the second node device on the communication bus based on the address allocation demand data;
and the master station equipment receives equipment reply data sent by the second node equipment aiming at the allocation address inquiry instruction, and allocates an address for the second node equipment.
In a possible implementation, the apparatus further includes a third processing unit configured to:
when the master station equipment receives the abnormal information, the master station equipment sends an address allocation inquiry instruction through the communication bus; the abnormal information indicates that the master station device does not receive reply information of the transmitted data, or the received data is data of a non-preset protocol;
and if the master station device receives device reply data sent by the third node device for the allocation address inquiry instruction, allocating an address for the third node device.
In a possible implementation, the apparatus further includes a first execution unit configured to:
the master station device determines whether an address allocation mode condition is satisfied; the address mode allocation condition is that an upper instruction or a mechanical switch selection instruction is received;
when the master station device determines that the address allocation mode is met, the master station device executes an operation of sequentially sending an allocation address query instruction to any slave station node device through the communication bus;
and when the master station device determines that the address allocation mode condition is not met, not executing the operation of sequentially sending an allocation address query instruction to any slave station node device.
In a possible embodiment, the apparatus further comprises a recording unit configured to:
and when the master station equipment allocates addresses to the slave station node equipment, recording the addresses of the slave station node equipment on the corresponding round-robin address list.
In a possible implementation, the apparatus further includes a second execution unit configured to:
and when the master station device does not receive the device reply data within a preset time interval, executing the operation of data round-robin transmission.
In a third aspect, an electronic device is provided, which includes:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory and executing the steps included in any of the methods of the first aspect according to the obtained program instructions.
In a fourth aspect, there is provided a computer readable storage medium having stored thereon a computer program for execution by a processor to perform the steps included in implementing any of the methods of the first aspect.
The technical scheme provided by the embodiment of the invention at least has the following beneficial effects:
in the embodiment of the present invention, the master device may actively detect a slave node device to be accessed, which newly accesses the communication bus, and then send an allocation address query instruction to the slave node device. Further, the master station device receives device reply data fed back by the slave station node device according to the allocation address query instruction through the communication bus, and allocates addresses to the slave station node device until all slave station node devices needing to be allocated addresses and to be accessed to the communication bus realize address allocation.
Therefore, in the embodiment of the invention, the master station device can quickly and accurately detect the newly accessed slave station node device and allocate the address to the slave station node device needing to be allocated, thereby overcoming the defect that the address of the node device needs to be manually set and greatly improving the efficiency of allocating the address.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention and are not to be construed as limiting the invention.
FIG. 1 is a system architecture diagram according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of address assignment in an embodiment of the present invention;
FIG. 3 is a block diagram of an apparatus for address assignment according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device in an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The embodiments and features of the embodiments of the present invention may be arbitrarily combined with each other without conflict. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
The terms "first" and "second" in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the term "comprises" and any variations thereof, which are intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
As mentioned above, configuring the address for the slave node device by the master device generally requires designing a dial switch on a circuit or solidifying the dial switch into firmware (control code). Thus, when more slave node devices are present, the address configuration method is inefficient and prone to errors.
Although the related art also provides an address automatic allocation scheme, the scheme adds an address allocation line other than communication or adds an address allocation communication bus in addition to the serial communication bus, thus increasing the complexity of the serial bus line, resulting in that the address allocation to the slave node device is prone to errors.
In view of this, embodiments of the present invention provide an address allocation method, by which addresses can be accurately and quickly allocated to each slave node device to be accessed without adding any new line.
After the design idea of the embodiment of the present invention is introduced, some brief descriptions are made below on a system architecture applicable to the technical solution in the embodiment of the present invention, it should be noted that the system architecture described in the embodiment of the present invention is for more clearly describing the technical solution in the embodiment of the present invention, and does not form a limitation on the technical solution provided in the embodiment of the present invention, and it is obvious to a person skilled in the art that the technical solution provided in the embodiment of the present invention is also applicable to similar technical problems.
In the embodiment of the present invention, the scheme provided in the embodiment of the present invention may be applied to some scenarios where it is inconvenient to manually set the device address, for example, a serial bus system scenario of a system for picking up goods according to lights, or an application scenario of a portable self-service cabinet access device, or may be applied to a scenario of a file management device, or of course, may be any other scenario where address allocation is required, which is not limited in the embodiment of the present invention.
The hardware connection mode of the communication bus provided in the embodiment of the invention mainly comprises one communication master station device, a plurality of communication slave station node devices, a communication relay device (optional) and the like. Exemplary, communication bus connection topology is shown in FIG. 1.
Therefore, the hardware connection mode of the communication bus provided by the embodiment of the invention mainly comprises the communication master station equipment and the slave station node equipment. Optionally, the system may further include a communication relay device and a power supply relay device. It should be noted that, for convenience of description, the "communication master station device" is hereinafter referred to as a "master station device".
For example, in an actual deployment scenario, the number of master station devices is 1; the slave station node equipment is selected based on the actual conditions, for example, 1-80 slave station nodes in a long distance and 1-150 slave station nodes in a short distance are selected; the communication relay apparatus and the power supply relay apparatus may be determined based on the number of bus nodes and the connection distance at the time of actual implementation. In actual implementation, the power supply relay device and the communication relay may be provided integrally.
Specifically, the bus of the invention only needs one communication bus, and does not need an auxiliary communication bus or an address identification line. In addition, the bus includes a communication bus and a power bus, and the slave device obtains operating power from the power bus and is also connected to the communication bus. In addition, a hot plug protection circuit is arranged in a communication interface circuit of the communication equipment, so that when the slave node equipment is connected into the bus, the bus fault is not caused.
In the embodiment of the invention, because the serial communication bus responds to the interference data caused by the access of the new equipment, interference prevention measures are required to be carried out on the working environment of the communication bus, and therefore, in the actual implementation process, interference signals except bus data abnormity caused by the fact that the new equipment is accessed by hot plugging and hot plugging are required to be shielded, so that the stability of the bus is improved.
To further illustrate the solution of the address allocation method provided by the embodiment of the present invention, the following detailed description is made with reference to the accompanying drawings and the detailed description. Although embodiments of the present invention provide method steps as shown in the following embodiments or figures, more or fewer steps may be included in the method based on conventional or non-inventive efforts. In steps where no necessary causal relationship exists logically, the order of execution of the steps is not limited to that provided by embodiments of the present invention. The method can be executed in sequence or in parallel according to the method shown in the embodiment or the figures when the method is executed in an actual processing procedure or a device (for example, a parallel processor or an application environment of multi-thread processing).
The method for address assignment according to the embodiment of the present invention is described below with reference to a flowchart of the method shown in fig. 2, and the steps shown in fig. 2 may be executed by an electronic device. In an implementation, the electronic device may be a server, such as a personal computer, a midrange computer, a cluster of computers, and so on.
Step 201: when the master station device detects that any slave station node device is accessed into the communication bus, an allocation address query instruction is sent to any slave station node device; any slave node device belongs to at least one slave node device to be accessed.
In the embodiment of the present invention, the master device may transmit an address assignment query command preset in a trigger communication protocol based on the communication bus. Specifically, when any slave node device detected by the master device accesses the communication bus, an allocation address query instruction may be sent to any slave node device through the communication bus.
Step 202: and the master station equipment receives equipment reply data fed back by any slave station node equipment according to the allocation address query instruction through a communication bus, and allocates an address to any slave station node equipment, so that at least one slave station equipment to be accessed is allocated to the allocated address.
In the embodiment of the present invention, the master device receives, through the communication bus, device reply data fed back by any slave node device in response to the allocation address query instruction, and allocates an address to any slave node device.
It can be seen that, in the embodiment of the present invention, the master device may detect a to-be-accessed slave node device newly accessing the communication bus, and then send an allocation address query instruction to the slave node device. Further, the master station device receives device reply data fed back by the slave station node device according to the allocation address query instruction through the communication bus, and allocates addresses to the slave station node device until all slave station node devices needing to be allocated addresses and to be accessed to the communication bus realize address allocation.
It is obvious that, in the plurality of slave node devices that have been accessed on the communication bus in the embodiment of the present invention, at most only one slave node device to which an address is not assigned exists. In addition, in the embodiment of the present invention, after allocating an address to one slave node device, the master device may wait for a preset time period, and then allocate an address to the detected slave node device newly accessing the communication bus. The preset time length may be determined based on actual implementation, which is not limited in the embodiment of the present invention.
In the embodiment of the present invention, when the master device determines that an address is allocated to any slave node device, the address of the slave node device is recorded on its corresponding round-robin address list. And, the slave node device stores the corresponding address. In this way, the efficiency of the operation of subsequently performing the data round robin transmission can be improved. In addition, the slave node device may also store the corresponding address.
In the embodiment of the present invention, in consideration of the situation that there is a slave node device newly accessing a communication bus, in order to better describe a scheme in which a master device assigns an address to a new slave node device, the following description is made in conjunction with several different situations. It should be noted that, in this embodiment of the present invention, when two new slave node devices without addresses are connected to a communication bus, a certain time interval is required, where the time interval is, for example, 1 second to 2 seconds, and the time interval may be correspondingly determined based on an actual implementation situation, which is not limited in this embodiment of the present invention.
Case 1:
in the embodiment of the present invention, when a slave node device is newly accessed on a communication bus, since the master device is not aware of the new slave node device and the newly accessed slave node device actively transmits data after the master device performs a data round robin transmission operation through the communication bus, the master device finds that a device disturbs its own polling data and stops performing the current data round robin transmission operation. Specifically, the new slave node device is referred to as a first node device, for example.
Specifically, after the master station device stops executing the current data round-robin transmission operation, the master station device transmits an allocation address query instruction based on the communication bus; if the master station equipment receives equipment reply data sent by the first node equipment aiming at the allocation address inquiry instruction, allocating an address for the first node equipment; the first node device is at least one node device external to the slave node device.
Therefore, in the embodiment of the invention, the address can be rapidly allocated to the first node device newly accessed to the communication bus.
Case 2:
in the embodiment of the present invention, when a new unaddressed slave node device is connected to the communication bus and no assigned address of the master device is obtained, and when it is found that master data related to non-address assignment is transmitted on the bus, the slave node device sends a very short address assignment request data (or low-level interference data for a certain period of the control bus) to the master device after receiving the command.
Specifically, the slave node apparatus that receives the master data related to non-address allocation when the allocated address of the master apparatus is not obtained and when it is found that the master data related to non-address allocation is transmitted on the bus may be referred to as, for example, a second node apparatus.
In the embodiment of the present invention, after the second node device accesses the communication bus and before the master device does not obtain an address allocated to the second node device, after the master device detects address allocation demand data sent by the second node device, the master device may send an address allocation inquiry instruction to the second node device on the communication bus based on the address allocation demand data; the address allocation demand data is as follows: the second node device is determined based on non-address allocation related data transmitted by the master device on the communication bus.
Further, the master device may receive device reply data sent by the second node device for the address assignment query instruction, and then assign an address to the second node device. Therefore, the purpose of rapidly allocating the addresses to the newly added node equipment can be achieved.
Case 3:
in the embodiment of the present invention, when a new slave node device suddenly accesses to the communication bus, if there is data being transmitted on the communication bus at the same time, the access of the new slave node device may interfere with the data being transmitted on the communication bus, and therefore, the master device may detect the abnormal information of the communication bus at this time. That is, when the master device does not receive the reply message of the transmitted data, or the received data is data of a non-preset protocol, that is, the master device receives the abnormal information, it may consider whether there is a new access to the communication bus.
Specifically, when the master station device receives the abnormal information, the master station device sends an address allocation inquiry instruction through the communication bus; and if the master station equipment receives equipment reply data sent by the third node equipment aiming at the allocation address inquiry instruction, allocating an address for the third node equipment.
Therefore, in the embodiment of the present invention, the master device may allocate an address to the newly accessed slave node device. Specifically, after discovering that a new slave node device accesses the communication bus, the master device interrupts the inherent data round-robin transmission operation and immediately transmits an address allocation inquiry command to the communication bus; and the master station device determines the slave station node device to be assigned with the address based on the principle that only the device which is not assigned with the address feeds back data and the device which has the address does not feed back, and assigns the address for the slave station node device to be assigned with the address based on the address assignment instruction.
In one possible embodiment, if the slave node device is an addressed device, the master device does not receive a corresponding response after sending the address assignment query. Therefore, when the master device does not receive the device reply data within the preset time interval, the data round robin transmission operation is executed. The preset time interval may be 500ms or 400ms, and certainly, other time intervals correspondingly determined according to actual implementation may also be used, which is not limited in the embodiment of the present invention.
In a possible implementation manner, the master device may further send an address allocation inquiry instruction through the communication bus in a certain time period in normal communication, that is, the master device actively inquires whether there is a device that does not allocate an address, and when receiving device reply data that is not allocated an address, the master device may allocate an address to a slave node device corresponding to the device reply data.
In one possible embodiment, the master device may determine whether an address allocation pattern condition is satisfied; the address mode allocation condition is that an upper instruction or a mechanical switch selection instruction is received. Then, when the master station device determines that the address allocation mode is met, the master station device executes an operation of sequentially sending an allocation address query instruction to at least one slave station node device through a communication bus; and when the master station device determines that the address allocation mode condition is not met, the operation of sequentially sending the allocation address query instruction to at least one slave station node device is not executed.
Therefore, in the embodiment of the present invention, an optional mode whether the master station device allocates an address may also be provided, which enriches the embodiments of the method for allocating an address provided in the present solution and enhances the implementability of the present solution.
In the embodiment of the present invention, the communication bus may perform communication verification on the commands or data transmitted by the master device and the slave device. For example, the communication Check may be one or more of a CRC (Cyclic Redundancy Check) Check, an xor Check, an accumulation and a Check, which is not limited in this embodiment of the present invention. In this way, the reliability of data or command transmission can be ensured as much as possible.
Therefore, the method for allocating the address provided by the embodiment of the invention can realize the automatic allocation of the address of the slave station node equipment on the bus without adding the physical wiring of the serial bus, greatly reduce the maintenance cost of the serial bus and improve the working efficiency.
Based on the same inventive concept, the embodiment of the invention also provides an address allocation device, and the address allocation device can realize the corresponding function of the address allocation method. The means for address assignment may be a hardware structure, a software module, or a hardware structure plus a software module. The address assignment device may be implemented by a chip system, which may be formed by a chip, or may include a chip and other discrete devices. Referring to fig. 3, the apparatus for allocating addresses includes:
a sending unit 301, configured to send an allocation address query instruction to any slave node device when the master device detects that any slave node device accesses a communication bus; any slave node equipment belongs to at least one slave node equipment to be accessed;
an allocating unit 302, configured to receive, by the master device through a communication bus, device reply data fed back by any slave node device in response to the allocation address query instruction, and allocate an address to the any slave node device, so that at least one slave device to be accessed is allocated to the allocation address.
In a possible implementation manner, after the master device performs the data round-robin transmission operation through the communication bus, the first node device accesses the communication bus, and the apparatus further includes a first processing unit, configured to:
the master station equipment stops executing the current data round-robin sending operation and sends an address allocation inquiry instruction based on the communication bus;
if the master station device receives device reply data sent by the first node device for the allocation address query instruction, allocating an address for the first node device; the first node device is a node device other than the at least one slave node device.
In a possible implementation manner, after the second node device accesses the communication bus and before the second node device does not obtain the address allocated to it by the master device, the apparatus further includes a second processing unit configured to: the master station device detects address allocation demand data sent by the second node device; the address allocation demand data is: the second node device is determined based on non-address allocation related data sent by the master device on the communication bus;
the master station device sends an address allocation inquiry instruction to the second node device on the communication bus based on the address allocation demand data;
and the master station equipment receives equipment reply data sent by the second node equipment aiming at the allocation address inquiry instruction, and allocates an address for the second node equipment.
In a possible implementation, the apparatus further includes a third processing unit configured to:
when the master station equipment receives the abnormal information, the master station equipment sends an address allocation inquiry instruction through the communication bus; the abnormal information indicates that the master station device does not receive reply information of the transmitted data, or the received data is data of a non-preset protocol;
and if the master station device receives device reply data sent by the third node device for the allocation address inquiry instruction, allocating an address for the third node device.
In a possible implementation, the apparatus further includes a first execution unit configured to:
the master station device determines whether an address allocation mode condition is satisfied; the address mode allocation condition is that an upper instruction or a mechanical switch selection instruction is received;
when the master station device determines that the address allocation mode is met, the master station device executes an operation of sequentially sending an allocation address query instruction to any slave station node device through the communication bus;
and when the master station device determines that the address allocation mode condition is not met, not executing the operation of sequentially sending an allocation address query instruction to any slave station node device.
In a possible embodiment, the apparatus further comprises a recording unit configured to:
and when the master station equipment allocates addresses to the slave station node equipment, recording the addresses of the slave station node equipment on the corresponding round-robin address list.
In a possible implementation, the apparatus further includes a second execution unit configured to:
and when the master station device does not receive the device reply data within a preset time interval, executing the operation of data round-robin transmission.
Based on the same inventive concept, an embodiment of the present invention provides an electronic device, please refer to fig. 4, where the electronic device includes at least one processor 401 and a memory 402 connected to the at least one processor, a specific connection medium between the processor 401 and the memory 402 is not limited in the embodiment of the present invention, in fig. 4, the processor 401 and the memory 402 are connected through a bus 400 as an example, the bus 400 is represented by a thick line in fig. 4, and a connection manner between other components is only schematically illustrated and is not limited. The bus 400 may be divided into an address bus, a data bus, a control bus, etc., and is shown with only one thick line in fig. 4 for ease of illustration, but does not represent only one bus or type of bus. The device for address assignment also comprises a communication interface 403 for receiving or transmitting data.
In the embodiment of the present invention, the memory 402 stores instructions executable by the at least one processor 401, and the at least one processor 401 may execute the steps included in the foregoing address allocation method by executing the instructions stored in the memory 402.
The processor 401 is a control center of the electronic device, and may connect various portions of the whole electronic device by using various interfaces and lines, and perform various functions and process data of the electronic device by operating or executing instructions stored in the memory 402 and calling data stored in the memory 402, thereby performing overall monitoring on the electronic device.
Optionally, the processor 401 may include one or more processing units, and the processor 401 may integrate an application processor and a modem processor, wherein the application processor mainly handles an operating system, a user interface, an application program, and the like, and the modem processor mainly handles wireless communication. It will be appreciated that the modem processor described above may not be integrated into the processor 401. In some embodiments, processor 401 and memory 402 may be implemented on the same chip, or in some embodiments, they may be implemented separately on separate chips.
The processor 401 may be a general-purpose processor, such as a Central Processing Unit (CPU), digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like, that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.
By programming the processor 401, the code corresponding to the address allocation method described in the foregoing embodiment may be solidified into a chip, so that the chip can execute the steps of the address allocation method when running, and how to program the processor 401 is a technique known by those skilled in the art, and is not described herein again.
Based on the same inventive concept, embodiments of the present invention further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of implementing the method for address allocation as described above are implemented.
In some possible embodiments, the various aspects of the method for address assignment provided by the present invention may also be implemented in the form of a program product comprising program code means for causing a control electronic device to carry out the steps of the method for address assignment according to the various exemplary embodiments of the present invention described above in this description, when said program product is run on the control electronic device.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method of address allocation, applied to a communication bus connecting a master device and at least one slave node device to be accessed, the method comprising:
when the master station device detects that any slave station node device is accessed to a communication bus, an allocation address query instruction is sent to the any slave station node device; any slave node equipment belongs to at least one slave node equipment to be accessed;
and the master station device receives device reply data fed back by any slave station node device according to the allocation address query instruction through a communication bus, and allocates an address to any slave station node device, so that at least one slave station device to be accessed is allocated to the allocation address.
2. The method of claim 1, wherein a first node device accesses the communication bus after the master device performs a data round-robin transmission operation over the communication bus, the method further comprising:
the master station equipment stops executing the current data round-robin sending operation and sends an address allocation inquiry instruction based on the communication bus;
if the master station device receives device reply data sent by the first node device for the allocation address query instruction, allocating an address for the first node device; the first node device is a node device other than the at least one slave node device.
3. The method of claim 1, wherein after a second node device accesses the communication bus and before the master device is not obtaining an address assigned to it, the method further comprises:
the master station device detects address allocation demand data sent by the second node device; the address allocation demand data is: the second node device is determined based on non-address allocation related data sent by the master device on the communication bus;
the master station device sends an address allocation inquiry instruction to the second node device on the communication bus based on the address allocation demand data;
and the master station equipment receives equipment reply data sent by the second node equipment aiming at the allocation address inquiry instruction, and allocates an address for the second node equipment.
4. The method of claim 1, wherein the method further comprises:
when the master station equipment receives the abnormal information, the master station equipment sends an address allocation inquiry instruction through the communication bus; the abnormal information indicates that the master station device does not receive reply information of the transmitted data, or the received data is data of a non-preset protocol;
and if the master station device receives device reply data sent by the third node device for the allocation address inquiry instruction, allocating an address for the third node device.
5. The method of claim 1, wherein prior to transmitting an assignment address query instruction to any slave node device when the master device detects that the any slave node device is accessing a communication bus, the method further comprises:
the master station device determines whether an address allocation mode condition is satisfied; the address mode allocation condition is that an upper instruction or a mechanical switch selection instruction is received;
when the master station device determines that the address allocation mode is satisfied, the master station device executes an operation of sending an allocation address query instruction to any slave station node device through the communication bus;
and when the master station device determines that the address allocation mode condition is not met, not executing the operation of sequentially sending an allocation address query instruction to any slave station node device.
6. The method of any of claims 1-5, wherein the method further comprises:
and when the master station equipment allocates addresses to the slave station node equipment, recording the addresses of the slave station node equipment on the corresponding round-robin address list.
7. The method of any of claims 1-5, wherein the method further comprises:
and when the master station device does not receive the device reply data within a preset time interval, executing the operation of data round-robin transmission.
8. An address assignment apparatus, applied to a communication bus connecting a master device and at least one slave node device to be accessed, the apparatus comprising:
a sending unit, configured to send an allocation address query instruction to any slave node device when the master device detects that any slave node device accesses a communication bus; any slave node equipment belongs to at least one slave node equipment to be accessed;
and the allocating unit is used for receiving the device reply data fed back by any slave node device according to the allocation address query instruction by the master device through a communication bus, and allocating an address to any slave node device, so that at least one slave device to be accessed is allocated to the allocation address.
9. An electronic device, characterized in that the electronic device comprises: memory, processor and computer program stored on the memory and executable on the processor, which computer program, when being executed by the processor, carries out the steps of the method of address allocation according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the method of address assignment according to one of the claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111607242.3A CN114401250A (en) | 2021-12-27 | 2021-12-27 | Address allocation method and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111607242.3A CN114401250A (en) | 2021-12-27 | 2021-12-27 | Address allocation method and device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115174526A (en) * | 2022-06-29 | 2022-10-11 | 京东方科技集团股份有限公司 | Network adaptation method and device between devices, storage medium and electronic device |
| CN115277295A (en) * | 2022-07-29 | 2022-11-01 | 广东美的智能科技有限公司 | Communication method of controller and controller |
| CN117240651A (en) * | 2023-11-14 | 2023-12-15 | 广东宝莱特医用科技股份有限公司 | Method for inquiring equipment online, telemetry system, electronic equipment and storage medium |
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2021
- 2021-12-27 CN CN202111607242.3A patent/CN114401250A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115174526A (en) * | 2022-06-29 | 2022-10-11 | 京东方科技集团股份有限公司 | Network adaptation method and device between devices, storage medium and electronic device |
| CN115277295A (en) * | 2022-07-29 | 2022-11-01 | 广东美的智能科技有限公司 | Communication method of controller and controller |
| CN115277295B (en) * | 2022-07-29 | 2023-12-19 | 广东美的智能科技有限公司 | Communication method of controller and controller |
| CN117240651A (en) * | 2023-11-14 | 2023-12-15 | 广东宝莱特医用科技股份有限公司 | Method for inquiring equipment online, telemetry system, electronic equipment and storage medium |
| CN117240651B (en) * | 2023-11-14 | 2024-03-22 | 广东宝莱特医用科技股份有限公司 | Method for inquiring equipment online, telemetry system, electronic equipment and storage medium |
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