CN114400186A - Semiconductor structure, forming method and control method of semiconductor machine - Google Patents

Semiconductor structure, forming method and control method of semiconductor machine Download PDF

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CN114400186A
CN114400186A CN202111624015.1A CN202111624015A CN114400186A CN 114400186 A CN114400186 A CN 114400186A CN 202111624015 A CN202111624015 A CN 202111624015A CN 114400186 A CN114400186 A CN 114400186A
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functional layer
wafer
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肖文静
胡思平
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating

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Abstract

The embodiment of the application discloses a semiconductor structure, a forming method and a control method of a semiconductor machine, wherein the forming method comprises the following steps: providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device; and forming a stress adjusting structure covering the back surface, wherein the stress adjusting structure comprises a first functional layer and a second functional layer, the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.

Description

Semiconductor structure, forming method and control method of semiconductor machine
Technical Field
The present disclosure relates to the field of semiconductor technologies, and more particularly, to a semiconductor structure, a method for forming the same, and a method for controlling a semiconductor device.
Background
With the development of semiconductor chip manufacturing technology, the integration density of semiconductor devices is increasing, and the number of chips manufactured on a single wafer is increasing. In the production process of semiconductors, the wafer is warped due to different stresses of various thin film materials stacked and deposited on the wafer, which causes many problems. For example, wafer instability in the tool, wafer breakage, and reduced pattern registration accuracy. In addition, the difficulty of adsorption to the wafer is increased, and a part of the process is affected. The above problems all result in unstable product performance and reduce the yield and yield of the product. With the increasing number of layers of the 3D NAND memory device, the problem of wafer warpage is more and more serious.
Disclosure of Invention
Accordingly, the present disclosure is directed to a semiconductor structure, a method of forming the same, and a method of controlling a semiconductor machine.
In order to achieve the purpose, the technical scheme of the application is realized as follows:
the embodiment of the application provides a method for forming a semiconductor structure, which comprises the following steps:
providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device;
and forming a stress adjusting structure covering the back surface, wherein the stress adjusting structure comprises a first functional layer and a second functional layer, the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.
In the above scheme, the second functional layer includes a second functional layer first sub-layer, and the second functional layer first sub-layer is configured to block charges in the wafer from entering the first functional layer to adjust a charge amount in the first functional layer;
forming a stress accommodating structure overlying the backside, comprising:
forming a second functional layer first sublayer and a first functional layer covering the back surface in sequence;
the second functional layer first sublayer is located between the first functional layer and the wafer.
In the above solution, the second functional layer further includes a second functional layer second sub-layer, and the second functional layer second sub-layer is configured to derive charges in the first functional layer to adjust an amount of charges in the first functional layer;
forming a stress accommodating structure overlying the backside, comprising:
and forming a second functional layer and a second sub-layer on the first functional layer.
In the above scheme, the first functional layer includes at least one of silicon nitride and silicon oxynitride;
the second functional layer first sublayer is an insulating layer;
the second functional layer and the second sub-layer are doped silicon layers.
In the above solution, the second functional layer includes a second functional layer second sub-layer, and the second functional layer second sub-layer is configured to derive charges in the first functional layer to adjust an amount of charges in the first functional layer;
forming a stress accommodating structure overlying the backside, comprising:
sequentially forming a first functional layer and a second functional layer second sublayer covering the back surface;
the first functional layer is located between the second functional layer second sublayer and the wafer.
In the above scheme, the first functional layer includes at least one of silicon nitride and silicon oxynitride;
the second functional layer and the second sub-layer are doped silicon layers.
An embodiment of the present application further provides a semiconductor structure, including: a wafer comprising opposing front and back sides, the front side for forming a semiconductor device;
the stress adjusting structure is located on the back face of the wafer and comprises a first functional layer and a second functional layer, wherein the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.
In the above scheme, the second functional layer includes a second functional layer first sub-layer, and the second functional layer first sub-layer is configured to block charges in the wafer from entering the first functional layer to adjust a charge amount in the first functional layer;
the second functional layer first sublayer is located between the first functional layer and the wafer.
In the foregoing scheme, the second functional layer further includes a second functional layer second sub-layer, where the second functional layer second sub-layer is configured to derive charges in the first functional layer to adjust an amount of charges in the first functional layer, and the first functional layer is located between the second functional first sub-layer and the second functional layer second sub-layer.
In the above scheme, the first functional layer includes at least one of silicon nitride and silicon oxynitride;
the second functional layer first sublayer is an insulating layer;
the second functional layer and the second sub-layer are doped silicon layers.
In the above solution, the second functional layer includes a second functional layer second sub-layer, and the second functional layer second sub-layer is configured to derive charges in the first functional layer to adjust an amount of charges in the first functional layer;
the first functional layer is located between the second functional layer second sublayer and the wafer.
In the above scheme, the first functional layer includes at least one of silicon nitride and silicon oxynitride;
the second functional layer and the second sub-layer are doped silicon layers.
An embodiment of the present application further provides a method for controlling a semiconductor machine, where the method is applied to the semiconductor structure according to any one of the above schemes, the semiconductor machine includes an electrostatic chuck, and the method includes:
placing the semiconductor structure on the electrostatic chuck;
applying a voltage to the electrostatic chuck to cause the semiconductor structure to be attracted to the electrostatic chuck;
carrying out semiconductor process treatment on the semiconductor structure;
and the applied voltage of the electrostatic chuck is reset to zero so as to take the semiconductor structure subjected to the semiconductor process treatment from the electrostatic chuck.
In the above scheme, the semiconductor process includes a plasma etching process and a plasma deposition process.
In the semiconductor structure, the forming method and the control method of the semiconductor machine provided by the embodiment of the application, on one hand, the method comprises the following steps: providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device; forming a stress adjustment structure covering the back surface; the stress adjustment structure comprises a first functional layer and a second functional layer; the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer; in another aspect. The semiconductor structure is formed by the method provided by the embodiment of the application. So, on the basis that the realization was adjusted the wafer warpage, increased the second functional layer of adjusting first functional layer electric charge amount, through setting up first functional layer and second functional layer promptly, when the realization was adjusted the wafer warpage, can also adjust the electric charge amount that is arranged in the first functional layer that the wafer back is used for adjusting the warpage, reduced the electrostatic adsorption effect between first functional layer and the electrostatic Chuck (ESC), reduced the risk of board warning (Alarm) or wafer piece.
Drawings
FIG. 1 is a schematic view of the electrostatic chuck and wafer with electrostatic attraction;
fig. 2 is a schematic flow chart illustrating an implementation of a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 3 is a schematic view of a wafer backside stress adjustment structure according to an embodiment of the present disclosure;
fig. 4 is a schematic flow chart illustrating a method for forming a semiconductor structure according to another embodiment of the present disclosure;
FIG. 5 is a schematic view of a wafer backside stress adjustment structure according to another embodiment of the present application;
fig. 6 is a schematic flow chart illustrating an implementation of a method for forming a semiconductor structure according to yet another embodiment of the present application;
FIG. 7 is a schematic view of a wafer backside stress adjustment structure according to yet another embodiment of the present application
Fig. 8 is a schematic flow chart illustrating an implementation of a method for controlling a semiconductor apparatus according to an embodiment of the present disclosure.
Wherein the figures include the following reference numerals:
10-a wafer; 11-a silicon nitride film; 12-an electrostatic chuck; 13-an electrode; 30-a wafer; 31-second functional layer first sublayer; 32-a first functional layer; 50-a wafer; 51-a first functional layer; 52-second functional layer second sublayer; 70-a wafer; 71-the second functional layer first sublayer; 72-a first functional layer; 73-second functional layer second sublayer.
Detailed Description
The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any level at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces.
The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.
Fig. 1 is a schematic view showing the presence of electrostatic attraction between a wafer and an electrostatic chuck. With the development of semiconductor chip manufacturing technology, the integration density of semiconductor devices is increasing, and the number of chips manufactured on a single wafer is increasing. In the production process of semiconductors, the wafer is warped due to different stresses of various thin film materials stacked and deposited on the wafer, which causes many problems. For example, wafer instability in the tool, wafer breakage, reduced pattern registration accuracy, etc. In addition, the difficulty of adsorption to the wafer is increased, and a part of the process is affected. The above problems all result in unstable product performance and reduce the yield and yield of the product. With the increasing number of layers of the 3D NAND memory device, the problem of wafer warpage is more and more serious. Therefore, as shown in fig. 1, the wafer 10 includes opposite front and back surfaces, the front surface is used for forming a semiconductor device, and according to the warpage degree of the wafer, a silicon nitride film 11 is grown on the back surface of the wafer 10 to balance the stress of the wafer and adjust the warpage of the wafer, which is a common method for adjusting the warpage of the wafer. As shown in fig. 1, when the wafer is placed on the electrostatic Chuck 12, due to the high trap density between the interface of the silicon nitride film 11 and the wafer 10, under the action of the electric field of the electrostatic Chuck 12, the silicon nitride film easily captures (trap) charges, so that during the electrostatic adsorption (De-Chuck) removal process after the process is finished, a large electrostatic adsorption still exists between the silicon nitride film 11 and the electrostatic Chuck 12, and the situation that the machine alarm or the wafer fragment is caused due to failure in electrostatic adsorption removal is easily caused.
Based on this, an embodiment of the present application provides a method for forming a semiconductor structure, and fig. 2 is a schematic implementation flow diagram of the method for forming a semiconductor structure provided in the embodiment of the present application. As shown in fig. 2, the method comprises the steps of:
step 201: providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device;
step 202: and forming a stress adjusting structure covering the back surface, wherein the stress adjusting structure comprises a first functional layer and a second functional layer, the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.
According to the embodiment of the application, a stress adjusting structure is formed on the back surface of a wafer, and the stress adjusting structure comprises a first functional layer and a second functional layer; through first functional layer adjusts the angularity of wafer, through the second functional layer adjusts electric charge in the first functional layer, so, on the basis that the realization was adjusted the wafer angularity, the second functional layer of adjusting first functional layer electric charge has been increased, through setting up first functional layer and second functional layer promptly, when the realization is adjusted the wafer angularity, can also adjust the electric charge that is arranged in the first functional layer of wafer back and is used for adjusting the angularity, the electrostatic absorption between first functional layer and the ESC has been reduced, the risk of board warning or wafer piece has been reduced.
In this embodiment, the second functional layer includes a second functional layer first sub-layer, and step 202 includes sequentially forming the second functional layer first sub-layer and the first functional layer covering the back surface. Fig. 3 illustrates a schematic diagram of a wafer backside stress adjustment structure formed by the method illustrated in fig. 2. As shown in fig. 3, wafer 30 includes opposing front and back sides; a stress adjustment structure located on the back side of the wafer 30, wherein the stress adjustment structure includes a first functional layer 32 and a second functional layer first sublayer 31; the first functional layer 32 is used to adjust the warpage of the wafer, and the second functional layer first sublayer 31 is used to block charges in the wafer from entering the first functional layer to adjust the amount of charges in the first functional layer 32.
In the embodiment of the present application, the second functional layer first sub-layer 31 is located between the first functional layer 32 and the wafer 30. The charge in the wafer 30 is blocked from entering the first functional layer 32 by the charge isolating function of the second functional layer first sublayer 31.
In the embodiment of the present application, the wafer 30 may be a single crystal silicon wafer. In other embodiments, the wafer may also be other semiconductor material wafers, such as germanium (Ge), silicon germanium (SiGe), Silicon On Insulator (SOI), and the like. The front side of the wafer is used to form a semiconductor device.
In some embodiments, the wafer 30 may be a semiconductor substrate. The semiconductor substrate may be an elemental semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator (GeOI) substrate, etc. The front surface of the semiconductor substrate is used for forming a semiconductor device.
Here, the semiconductor device includes a memory array and a contact structure. The memory array may include transistors, word lines, and bit lines. The contact structure may include a conductive contact structure and a metal layer formed on the memory array, the contact structure for electrically leading out the memory array. For example, contact structures may be used to control signal transmission of one or more sources and/or drains of transistors and word lines, bit lines, and the like.
In the embodiment of the present application, the material of the first functional layer 32 includes at least one of silicon nitride, silicon oxynitride, polysilicon, and amorphous carbon; the second functional layer first sub-layer 31 includes an insulating layer, and in some embodiments, the second functional layer first sub-layer 31 may be any one of silicon oxide and aluminum oxide.
In practical applications, the first functional Layer 32 and the second functional Layer 31 may be formed by a Deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-Enhanced CVD (PECVD), or Atomic Layer Deposition (ALD).
In one embodiment, the wafer is first processedThe back surface is formed with a layer having a thickness in the range of
Figure BDA0003439172730000071
Then a silicon nitride layer (first functional layer) is formed on the silicon oxide layer. The silicon oxide layer between the wafer and the silicon nitride layer can play a role in isolating charges, so that the situation that the charges in the wafer are pulled into the silicon nitride layer under the action of the ESC electric field is avoided, and the charge quantity trapped in the silicon nitride layer is reduced. Therefore, the electrostatic adsorption effect between the silicon nitride layer and the ESC is reduced, and the risk of machine alarm or wafer fragment is reduced.
It should be noted that, in practical applications, the thickness of the silicon nitride layer (the first functional layer) may be determined according to the wafer warpage degree, so as to adjust the wafer warpage in a targeted manner.
In another embodiment of the present application, another method for forming a semiconductor structure is provided, and fig. 4 is a schematic implementation flow diagram of the method for forming a semiconductor structure provided in the embodiment of the present application. As shown in fig. 4, the method comprises the steps of:
step 401: providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device;
step 402: and forming a stress adjusting structure covering the back surface, wherein the stress adjusting structure comprises a first functional layer and a second functional layer, the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.
According to the embodiment of the application, a stress adjusting structure is formed on the back surface of a wafer, and the stress adjusting structure comprises a first functional layer and a second functional layer; through first functional layer adjusts the angularity of wafer, through the second functional layer derives the intraformational electric charge of first functional layer, so, on the basis that the realization was adjusted the wafer angularity, increased the second functional layer of adjusting first functional layer electric charge, through setting up first functional layer and second functional layer promptly, when realizing the adjustment to the wafer angularity, can also adjust through the second functional layer electric charge in the first functional layer, so, reduced the electrostatic absorption effect between first functional layer and the ESC, reduced the risk of board warning or wafer piece.
In this embodiment, the second functional layer includes a second functional layer second sub-layer, and step 402 includes sequentially forming a first functional layer and a second functional layer second sub-layer covering the back surface. Fig. 5 shows a schematic diagram of a wafer backside stress adjustment structure formed by the method shown in fig. 4. As shown in fig. 5, wafer 50 includes opposing front and back sides; a stress adjustment structure located on the back side of the wafer 50, the stress adjustment structure including a first functional layer 51 and a second functional layer second sublayer 52; the first functional layer 51 is configured to adjust the warpage of the wafer, and the second functional layer second sublayer 52 is configured to derive charges in the first functional layer to adjust the amount of charges in the first functional layer 51.
In the embodiment of the present application, the first functional layer 51 is located between the second functional layer second sublayer 52 and the wafer 50. The charge in the first functional layer 51 is derived from the high conductivity properties of the second functional layer second sublayer 52.
In the embodiment of the present application, the wafer 50 may be a single crystal silicon wafer. In other embodiments, the wafer may also be other semiconductor material wafers, such as germanium, silicon on insulator, and the like. The front side of the wafer is used to form a semiconductor device.
In some embodiments, the wafer may be a semiconductor substrate. The front surface of the semiconductor substrate is used for forming a semiconductor device.
In the embodiment of the present application, the material of the first functional layer 51 includes at least one of silicon nitride and silicon oxynitride; the second functional layer, the second sub-layer 52, is a doped silicon layer, and the polysilicon layer may be doped with one or more of boron, phosphorus, gallium, selenium, or arsenic to form the doped silicon layer.
In practical application, the first functional layer and the second sublayer can be formed through a deposition process, wherein the second functional layer and the second sublayer can also be formed through a deposition process to form a polycrystalline silicon layer and an ion implantation process to form a doped silicon layer.
In one embodiment, a silicon nitride layer (first functional layer) is first formed on the back side of the wafer, and then a layer having a thickness in the range of
Figure BDA0003439172730000091
In the above-described embodiment, the polysilicon layer (second functional layer second sublayer) may be doped with dopant ions such as boron ions, phosphorus ions, gallium ions, selenium ions, or arsenic ions in order to increase the conductivity of the polysilicon layer. After the ESC process is completed, the highly conductive second functional layer and the second sub-layer can rapidly conduct away the charges trapped in the first functional layer. Therefore, the electrostatic adsorption effect between the first functional layer and the ESC is reduced, and the risk of machine alarm or wafer fragment is reduced.
It should be noted that, in practical applications, the thickness of the silicon nitride layer (the first functional layer) may be determined according to the wafer warpage degree, so as to adjust the wafer warpage in a targeted manner.
In another embodiment of the present application, the stress adjustment structure on the back surface of the wafer includes a first functional layer, a second functional layer, and a third functional layer. Fig. 6 is a schematic implementation flow diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 6, the method comprises the steps of:
step 601: providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device;
step 602: forming a second functional layer first sublayer, a first functional layer and a second functional layer second sublayer covering the back surface in sequence; the first functional layer is used for adjusting the warping degree of the wafer, the second functional layer first sub-layer is used for blocking electric charges in the wafer from entering the first functional layer, and the second functional layer second sub-layer is used for leading out the electric charges in the first functional layer.
According to the embodiment of the application, a stress adjusting structure is formed on the back of a wafer, and the stress adjusting structure comprises a first functional layer, a second functional layer and a third functional layer; adjusting the warpage of the wafer through the first functional layer, adjusting the amount of charge in the first functional layer through the second functional layer first sublayer and the second functional layer second sublayer, and thus, on the basis of realizing the adjustment of the warping degree of the wafer, a first sublayer of a second functional layer for preventing the electric charges in the wafer from entering the first functional layer and a second sublayer of the second functional layer for leading out the electric charges in the first functional layer are added, namely by providing a first functional layer, a second functional layer first sub-layer and a second functional layer second sub-layer, the wafer warpage can be adjusted, and the electric charge quantity in the first functional layer for adjusting the warpage on the back surface of the wafer can be adjusted, so that, the electrostatic adsorption between the first functional layer and the ESC is reduced to the greatest extent, and the risk of machine alarm or wafer fragment is reduced.
Fig. 7 shows a schematic diagram of a wafer backside stress adjustment structure formed by the method shown in fig. 6. As shown in fig. 7, the wafer 70 includes opposing front and back sides; a stress adjustment structure located on the back side of the wafer 70, wherein the stress adjustment structure includes a second functional layer first sublayer 71, a first functional layer 72, and a second functional layer second sublayer 73; the first functional layer 72 is used to adjust the warpage of the wafer, and the second functional layer first sublayer 71 and the second functional layer second sublayer 73 are used to adjust the amount of charge in the first functional layer 72.
In the embodiment of the present application, the second functional layer first sub-layer 71 is located between the first functional layer 72 and the wafer 70 to block charges in the wafer from entering the first functional layer. The first functional layer 72 is located between the second functional first sublayer 71 and the second functional second sublayer 73, such that the second functional second sublayer 73 can be used to derive charge within the first functional layer.
In one embodiment, the wafer 70 may be a single crystal silicon wafer. In other embodiments, the wafer may also be other semiconductor material wafers, such as germanium, silicon on insulator, and the like. The front side of the wafer is used to form a semiconductor device.
In some embodiments, the wafer may be a semiconductor substrate. The front surface of the semiconductor substrate is used for forming a semiconductor device.
In the embodiment of the present application, the material of the first functional layer 72 includes at least one of silicon nitride and silicon oxynitride; the second functional layer first sub-layer 71 comprises an insulating layer, and in some embodiments, the second functional layer first sub-layer 71 may be any one of silicon oxide and aluminum oxide; the second functional layer, the second sub-layer 73, is a doped silicon layer, and the polysilicon layer may be doped with one or more of boron, phosphorus, gallium, selenium, or arsenic to form the doped silicon layer.
In practical application, the first functional layer, the second functional layer first sublayer and the second functional layer second sublayer may be formed by a deposition process, wherein the second functional layer second sublayer may also be formed by a deposition process to form a polysilicon layer, and then an ion implantation process to form a doped silicon layer.
In one embodiment, a layer of thickness in the range of
Figure BDA0003439172730000111
Then a silicon nitride layer (first functional layer) is formed on the silicon oxide layer, and finally a layer having a thickness in the range of
Figure BDA0003439172730000112
With or without dopant ions such as boron, phosphorus, gallium, selenium or arsenic ions (second functional layer, second sublayer). The method can prevent the charges in the wafer from entering the silicon nitride layer under the action of the ESC electric field, and meanwhile, the high-conductivity polycrystalline silicon layer on the outermost layer can quickly guide away the charges trapped in the silicon nitride layer after the ESC manufacturing process is finished.
In some embodiments, the thicknesses of the silicon oxide layer (second functional layer first sublayer) and the polysilicon layer (second functional layer second sublayer) may be the same. In practical application, the thicknesses of the first sublayer of the second functional layer and the second sublayer of the second functional layer can be set according to the thickness of the silicon nitride layer (the first functional layer) and the electric charge amount trapped therein, and as the first sublayer of the second functional layer can prevent electric charges in a wafer from entering the first functional layer and the second sublayer of the second functional layer can conduct away the electric charges in the silicon nitride layer, the second sublayer of the second functional layer can be set to be thinner when the first sublayer of the second functional layer is thicker; when the second functional layer second sublayer is thicker, the second functional layer first sublayer may be thinner to reduce the total thickness of the second functional layer first sublayer and the second functional layer second sublayer as much as possible.
The embodiment of the application also provides a control method of a semiconductor machine, which is applied to the semiconductor structure in any one of the embodiments, wherein the semiconductor machine comprises an electrostatic chuck. Fig. 8 is a schematic flow chart illustrating an implementation of a method for controlling a semiconductor apparatus according to an embodiment of the present disclosure. As shown in fig. 8, the control method includes the following steps
Step S801: placing the semiconductor structure on the electrostatic chuck;
step S802: applying a voltage to the electrostatic chuck to cause the semiconductor structure to be attracted to the electrostatic chuck;
in the above step S802, the above voltage is generally applied to the electrode of the electrostatic chuck, wherein the semiconductor structure is attracted to the electrostatic chuck by electrostatic force.
Step S803: and carrying out semiconductor process treatment on the semiconductor structure, wherein the semiconductor process treatment comprises plasma etching treatment and plasma deposition treatment.
Step S804: and the applied voltage of the electrostatic chuck is reset to zero so as to take the semiconductor structure subjected to the semiconductor process treatment from the electrostatic chuck.
In the step S804, since the control method is applied to the semiconductor structure according to any one of the embodiments of the present application, a situation that the semiconductor structure is "stuck" on the surface of the electrostatic chuck and is difficult to release after the voltage is cut off is avoided, and an electrostatic adsorption effect between the semiconductor structure and the electrostatic chuck is reduced in a process of releasing the electrostatic adsorption after the process is finished, so that a risk of machine alarm or wafer fragment is reduced.
The application provides a semiconductor structure, a forming method and a control method of a semiconductor machine. The semiconductor structure includes: a wafer comprising opposing front and back sides, the front side for forming a semiconductor device; the stress adjusting structure is positioned on the back surface of the wafer and comprises a first functional layer and a second functional layer; the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer. This application is realizing on the basis of adjusting wafer angularity, the second functional layer of adjusting first functional layer electric charge amount has been increased, promptly through setting up first functional layer and second functional layer, when the realization is to the adjustment of wafer angularity, can adjust the electric charge amount that is arranged in the first functional layer of wafer back and is used for adjusting the angularity, the electrostatic adsorption who removes between first functional layer and electrostatic chuck (ESC) after the process end has been reduced, the risk of board warning or wafer piece has been reduced.
It should be appreciated that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiments is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (14)

1. A method of forming a semiconductor structure, the method comprising:
providing a wafer, wherein the wafer comprises a front surface and a back surface which are opposite, and the front surface is used for forming a semiconductor device;
and forming a stress adjusting structure covering the back surface, wherein the stress adjusting structure comprises a first functional layer and a second functional layer, the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.
2. The method of claim 1, wherein the second functional layer comprises a second functional layer first sub-layer for blocking charges within the wafer from entering the first functional layer to adjust an amount of charges within the first functional layer;
forming a stress accommodating structure overlying the backside, comprising:
forming a second functional layer first sublayer and a first functional layer covering the back surface in sequence;
the second functional layer first sublayer is located between the first functional layer and the wafer.
3. The method of claim 2, wherein said second functional layer further comprises a second functional layer second sublayer for deriving charge within said first functional layer to adjust an amount of charge within said first functional layer;
forming a stress accommodating structure overlying the backside, comprising:
and forming a second functional layer and a second sub-layer on the first functional layer.
4. The method of claim 3,
the first functional layer is at least one of silicon nitride and silicon oxynitride;
the second functional layer first sublayer is an insulating layer;
the second functional layer and the second sub-layer are doped silicon layers.
5. The method of claim 1, wherein the second functional layer comprises a second functional layer second sublayer to derive charge within the first functional layer to adjust an amount of charge within the first functional layer;
forming a stress accommodating structure overlying the backside, comprising:
sequentially forming a first functional layer and a second functional layer second sublayer covering the back surface;
the first functional layer is located between the second functional layer second sublayer and the wafer.
6. The method of claim 5,
the first functional layer is at least one of silicon nitride and silicon oxynitride;
the second functional layer and the second sub-layer are doped silicon layers.
7. A semiconductor structure, comprising: a wafer comprising opposing front and back sides, the front side for forming a semiconductor device;
the stress adjusting structure is located on the back face of the wafer and comprises a first functional layer and a second functional layer, wherein the first functional layer is used for adjusting the warping degree of the wafer, and the second functional layer is used for adjusting the electric charge amount in the first functional layer.
8. The structure of claim 7, wherein the second functional layer comprises a second functional layer first sub-layer for blocking charges in the wafer from entering the first functional layer to adjust an amount of charges in the first functional layer;
the second functional layer first sublayer is located between the first functional layer and the wafer.
9. The structure of claim 8, wherein said second functional layer further comprises a second functional layer second sublayer for deriving charge within said first functional layer to adjust the amount of charge within said first functional layer, said first functional layer being located between said second functional first sublayer and said second functional layer second sublayer.
10. The structure of claim 9,
the first functional layer is at least one of silicon nitride and silicon oxynitride;
the second functional layer first sublayer is an insulating layer;
the second functional layer and the second sub-layer are doped silicon layers.
11. The structure of claim 7, wherein said second functional layer comprises a second functional layer second sublayer to derive charge within said first functional layer to adjust an amount of charge within said first functional layer;
the first functional layer is located between the second functional layer second sublayer and the wafer.
12. The structure of claim 11,
the first functional layer is at least one of silicon nitride and silicon oxynitride;
the second functional layer and the second sub-layer are doped silicon layers.
13. A method of controlling a semiconductor tool applied to the semiconductor structure of any one of claims 7 to 12, the semiconductor tool comprising an electrostatic chuck, the method comprising:
placing the semiconductor structure on the electrostatic chuck;
applying a voltage to the electrostatic chuck to cause the semiconductor structure to be attracted to the electrostatic chuck;
carrying out semiconductor process treatment on the semiconductor structure;
and the applied voltage of the electrostatic chuck is reset to zero so as to take the semiconductor structure subjected to the semiconductor process treatment from the electrostatic chuck.
14. The method of claim 13, wherein said semiconductor processing comprises a plasma etch process, a plasma deposition process.
CN202111624015.1A 2021-12-28 2021-12-28 Semiconductor structure, forming method and control method of semiconductor machine Pending CN114400186A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117080063A (en) * 2023-10-16 2023-11-17 粤芯半导体技术股份有限公司 Semiconductor process method adopting furnace tube, prefabricated wafer and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117080063A (en) * 2023-10-16 2023-11-17 粤芯半导体技术股份有限公司 Semiconductor process method adopting furnace tube, prefabricated wafer and preparation method thereof
CN117080063B (en) * 2023-10-16 2024-01-26 粤芯半导体技术股份有限公司 Semiconductor process method adopting furnace tube, prefabricated wafer and preparation method thereof

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