CN114400030A - Identification and remapping method for DDR4 interface data staggered routing - Google Patents

Abstract

The invention relates to the technical field of chips, in particular to a method for identifying and remapping data staggered routing of a DDR4 interface. The invention can automatically identify the cross connection condition between the DDR4 interface DQ of the DDRPHY and DRAM particles, and automatically configure the register remap DQ in the DDRPHY.

Description

Identification and remapping method for DDR4 interface data staggered routing

Technical Field

The invention relates to the technical field of chips, in particular to a method for identifying and remapping data staggered routing of a DDR4 interface.

Background

DDR is the most common memory interface at present, and most of the chips need to use a memory, especially an SOC chip. In the SOC chip, a ddrphy (double Data Rate Physical interface) is usually integrated, and the internal digital signal is analog-modulated into a high-speed signal on the PCB and then accesses Data with the DRAM particles. DDR is one of the most common technical protocol families in the world, and through decades of development, DDR1/DDR2/DDR3/DDR4/DDR5 and other derivative LPDDR/GDDR/HBM/and other protocols are developed in sequence from low speed to high speed.

The DDR4 interface is generally divided into two types of signals-CA (control) signaling command/address and DQ/DM/DQs (data) signaling data.

The total bit width of DQ determines the bit width of the data bus of the whole chip; DRAM particles with matching bit widths need to be spliced to the opposite surfaces of the PCB. DRAM granules have three bit width specifications of X4, X8 and X16, the DDR interface bus bit width is designed to be 16 bits, if the DRAM granules of X16 are used, only one DRAM granule is needed, as shown in FIG. 6; if X8DRAM pellets are used, then two are required, as in FIG. 7; if X4 particles are used, 4 particles are required. When the SOC chip and the DDR particles are connected on the PCB, the one-to-one correspondence between CA signals must be ensured, but the one-to-one correspondence between DQs is difficult to achieve (i.e., DDRPHY DQ0 is connected to DRAM DQ 0; DDRPHY DQn is connected to DRAM DQn, etc.), and the phenomenon that DDRPHY DQn is connected to DRAM DQm often occurs, as shown in fig. 8.

DQ signals between the DDRPHY and DRAM particles are parallelly transmitted by DQS high-speed double-edge sampling, and the rate reaches 1600Mbps to 3200Mbps as specified by a DDR4 protocol. Due to the trace difference between the chip and the PCB, mismatch occurs between DQ and DM and DQS when the signals are transmitted to the receiver. Each time the DDRPHY starts working after being powered on, the DDRPHY will carry out training and adjust the TX/RX delayline (delay line) of the signals of DQ/DM, DQS and the like in the DDRPHY; so that the electrical signals of DQ, DM and DQS are mutually matched when being transmitted to the receiving party, and DQ/DM is correctly sampled to the central point by DQS. There are two very important tracking-read tracking and write tracking, respectively.

The first common and very classic Read tracing method is that DDRPHY reads testpattern (test pattern) pre-stored in MPR register from DRAM grain, compares it with internally generated testpattern for collation, then adjusts internal DQ/DM/DQs rx delayline bit by bit, finds left and right boundaries that pass the comparison test, records them, and finally takes intermediate value. After reading tracing is finished, the DDRPHY can write tracing only after no problem is read, namely writing self-defined random pattern to DRAM particles, then reading back, checking whether data are matched, adjusting internal DQ/DM/DQS tx delay bit by bit to find left and right boundaries passing the comparison test, recording and finally taking a middle value. The read tracking read data must be placed in front of the write tracking write data; here, the reading tracing can be based on two preconditions; one is that the DRAM grain is consistent with testpattern in DDRPHY, and the second is one-to-one mapping between DDRPHY DQn and DRAM DQn. The first premise is based on the specification of the DDRn protocol and is certainly consistent, but the second premise is often not satisfied due to the aforementioned complexity of the wiring between the PCBs DQ; this problem also often results in delays in the DDR interface debug time.

The second kind of read tracing is to reduce the frequency first to ensure that the self-defined testpattern is completely and correctly written into DRAM particles, then to raise the frequency, and to read back the testpattern just written into the DRAM particles to make read tracing. Thus, although there may be an interleaved mapping between the DDRPHY and the DRAM DQ, the write-read-write-positive is negative, so that the write-read data is matched and can be compared with each other. However, the role of tracking is to ensure correct reading and writing, and the operation of ensuring correct writing of data before tracking is complicated and risky. So in fact the first read tracking above would be simpler and more reliable, but how to solve the inter-DQ remap problem that it encounters?

For the above-mentioned problem of inter-DQ remap on PCB board encountered by the first read tracing, the DDRPHY provides a solution-to remap DDRPHY DQ remap, e.g. internal DQn PAD remap to DQm, through register configuration. Thus, mismatches between DQs on the PCB can be corrected by remap inside the chip. This solution, however, still has a drawback: it is necessary to know the mapping between DQs on the PCB board in advance. As a chip developer, a whole set of packaged chip plus software solution is provided for equipment manufacturer customers, and the customers can design PCB circuits by themselves; unpredictable cross mapping conditions often occur in connection of DDR interface DQ signal lines and DRAM DQ signal lines of an SOC chip when a PCB is wired. Therefore, the DDR DQ remap parameters of the chip products need to be modified in a customized manner when the chip products are delivered to different customers and different products are delivered, and the labor cost and the use cost are increased.

Disclosure of Invention

The invention provides a method for identifying and remapping DDR4 interface data staggered routing, which can automatically identify the staggered connection condition between a DDRPHY interface and DDR4 interface DQ of DRAM particles, and automatically configure a register remap to remap DQ in the DDRPHY interface.

In order to realize the purpose of the invention, the adopted technical scheme is as follows: the DDR4 interface data staggered routing identification and remapping method comprises the following steps:

1) the data line of the DDRPHY is connected with the data line of the DRAM;

2) the control lines of the DDRPHY are correspondingly connected with the control lines of the DRAM one by one, and the DDRPHY configures one-hot codes for the MPR register of the DRAM through the control lines;

3) and the DDRPHY reads the one-hot code in the MPR register of the DRAM back through a data line so as to identify the data mapping relation between the DDRPHY and the DRAM.

As an optimized scheme of the invention, the one-hot code is one or a combination of more than one of 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40 and 0x 80.

As an optimization scheme of the invention, a parallel reading mode is adopted when the DDRPHY reads the one-hot code in the MPR register of the DRAM back through the data line.

As an optimization scheme of the invention, when the DDRPHY reads the one-hot code, DQ data acquired by taking a plurality of DQS in the middle as clock edges is taken as the standard.

The invention has the positive effects that: 1) the invention adds the solution of automatically identifying and correcting the staggered mapping between the DDRPHY and the DRAM, so that the solution is simple and reliable, and is convenient for DQ routing between the DDRPHY and DRAM particles on the PCB;

2) the invention uses a parallel reading mode to ensure that the read data cannot be overturned.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a flow chart of the inventive method;

FIGS. 2 and 3 are flow diagrams of embodiments of the method of the present invention;

FIG. 4 is a diagram illustrating the reading of the MPR register in parallel according to the present invention;

FIG. 5 is a schematic diagram of intercepting data when the MPR register is read in parallel mode according to the present invention;

FIG. 6 is a schematic diagram of a DDR interface 16bit wide docking X16DRAM connection;

FIG. 7 is a schematic diagram of a DDR interface 16bit wide docking X8DRAM connection;

FIG. 8 shows the cross-connection between DDRPHY and DRAM grain, with DRAM side on the left and DDRPHY side on the right.

Detailed Description

As shown in fig. 1, the present invention discloses a method for identifying and remapping data cross-trace of DDR4 interface, which comprises the following steps:

1) the data line of the DDRPHY is connected with the data line of the DRAM;

2) the control lines of the DDRPHY are correspondingly connected with the control lines of the DRAM one by one, and the DDRPHY configures one-hot codes for the MPR register of the DRAM through the control lines;

3) and the DDRPHY reads the one-hot code in the MPR register of the DRAM back through a data line so as to identify the data mapping relation between the DDRPHY and the DRAM.

The one-hot code is one or more of 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40 and 0x 80.

The DDRPHY adopts a parallel reading mode when reading back the one-hot code in the MPR register of the DRAM through a data line.

When the DDRPHY reads the one-hot code, DQ data acquired by taking the middle DQS as a clock edge is taken as the standard so as to ensure that the data is absolutely correct; there may be differences in the different chip design approaches. In the embodiment, the data bit width of a DFI interface (an internal data standard interface of a DDRPHY and a DMC module inside a chip) is 64 bits, and the data bit width of DDR4 is 16 bits; BL8 reads one time of one-hot codes, there are 8 continuous DQS edges to pick up DQ data, and there are 8 × 16 ═ 128bit data to be transmitted to the DFI data interface in a two-beat mode; the intercepted different bit field data of the DFI interface corresponds to the data acquired by different DQS. Because no read-write tracing is done, reading the MPR in DRAM directly may be in error, by which it is guaranteed that the correct one-hot code is read. Wherein, BL8, i.e. burst length, is 8; DDR4 defaults to BL8 as the most basic read-write operation mode; that is, DQ will appear 8 beats of data in succession, and is sampled by 4 rising edges and 4 falling edges of DQs in succession.

The invention can automatically identify the cross connection condition between the DDR4 interface DQ of the DDRPHY and the DRAM particle, and automatically configure the register remap DQ in the DDRPHY, different DDRPHY IPs of various manufacturers have the mapping relation of the register configurable remap DQ, and the mapping relation is identified first during specific execution, and then the register is configured to be remap for correction.

Example (b):

as shown in fig. 2 and fig. 3, after the WL and RXdqs _ gate tracing is completed, it can be ensured that the unique code in the DRAM can be read more easily and correctly later, MR3 is a mode register in the DRAM, then the unique code is written into the DRAM in sequence by a control signal, then the unique code is read in parallel by data signals in sequence, the data connection relationship between DDRPHY and the DRAM on the PCB board is sequentially identified, then the register is configured to remap and correct, and finally the classic and reliable read-write tracing is completed. Note that when the MPR register of the DRAM is read in parallel, the DQ value is fixed in one BL8, no inversion occurs, and the same value of DQ can be read eight times; and the DQ is taken by the middle DQS edge, so that the DQ value can be correctly read under the premise of not doing read tracing, as shown in FIGS. 4 and 5. DDRPHY2DRAM _ remap (m, n) is configured with DDRPHY register, DQm of DDRPHY is mapped into DQn, DQ mapping relation is confirmed, and MPR register default is restored.

The invention essentially writes a special code type one-hot code into a page0MPR register in DRAM particles through CA signal lines (the CA lines cannot be connected in a staggered way), and then reads the one-hot code back in the MPR register through DQ according to a parallel way, and the smart point is that the parallel way can ensure that DQ cannot be overturned in the read BL8, as shown in FIG. 4; theoretically, in BL8 reading, the same DQ pattern is adopted by the eight edges of DQS; we need to intercept the DQ one-hot codes taken along the middle DQS to analyze the DQ mapping relationship between DDRPHY and DRAM (see fig. 5), which is also the key point that the whole patent can implement to correctly read the DQ patterns of DRAM grains before reading training. The invention can be migrated to other DDR-like protocols.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (4)

1. The DDR4 interface data staggered routing identification and remapping method is characterized in that: the method comprises the following steps:

   1) the data line of the DDRPHY is connected with the data line of the DRAM;

   2) the control lines of the DDRPHY are correspondingly connected with the control lines of the DRAM one by one, and the DDRPHY configures one-hot codes for the MPR register of the DRAM through the control lines;

   3) and the DDRPHY reads the one-hot code in the MPR register of the DRAM back through a data line so as to identify the data mapping relation between the DDRPHY and the DRAM.
2. 2. The method for identifying and remapping DDR4 interface data cross-trace according to claim 1, wherein: the one-hot code is one or a combination of more than one of 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40 and 0x 80.
3. 3. The method for identifying and remapping DDR4 interface data cross-trace according to claim 1 or 2, wherein: the DDRPHY adopts a parallel reading mode when reading back the one-hot code in the MPR register of the DRAM through a data line.
4. 4. The method for identifying and remapping DDR4 interface data cross-trace according to claim 3, wherein: when the DDRPHY reads the one-hot code, DQ data acquired by taking a plurality of DQS in the middle as clock edges is taken as the standard.

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