CN114389719B - Spread spectrum demodulation simulation verification system - Google Patents
Spread spectrum demodulation simulation verification system Download PDFInfo
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Abstract
The invention relates to a spread spectrum demodulation simulation verification system, which comprises: the system comprises an imitation data signal source generation module, an imitation sine and cosine wave generation module, an imitation code bias self-adaptive adjustment spread spectrum code generation module, an imitation spread spectrum modulation module, an imitation demodulation data receiving module, an imitation working state detection module and a scoreboard module. The invention is suitable for ground simulation verification of the spread spectrum baseband processing FPGA in satellite products, and the configuration of the simulation environment can be carried out by changing parameters, so that the simulation spread spectrum modulation system verifies the working correctness of each module of the spread spectrum demodulation module FPGA under the condition that the Doppler frequency offset is any value, especially under the condition of dynamic frequency sweep. Meanwhile, the invention can also adjust intermediate frequency signals input by the FPGA according to feedback AGC values output by the FPGA, and provide a closed-loop simulation environment for the baseband processing FPGA.
Description
Technical Field
The invention relates to the field of spread spectrum transponders in satellite products, in particular to a spread spectrum demodulation simulation verification system.
Background
Spread spectrum demodulation processors are widely used in satellite engineering as communication devices. The FPGA is used for spread spectrum demodulation processing design, and has the advantages of high running speed, low power consumption and low cost, and the defects of using a chip for design and quite complex algorithm, so that internal signals and the complexity thereof are caused, and the hidden danger of design is easy to exist. The hardware joint measurement observation signals are limited, all the tedious signals cannot be observed, and design hidden trouble is found.
The existing simulation verification method uses Matlab simulation modulation signals of mathematical modeling software to generate input data files, reads one data at the rising edge of each system clock in a simulator, and sequentially imports and operates the data, so that the defects are obvious. Firstly, because the system clock frequency of the spread spectrum baseband processing FPGA of the spread spectrum transponder system is higher, the frequency is usually 60-100 Mhz, the actual unit signal is only 1khz, and 1 data is generated in each clock for the input of the FPGA, so that the data volume of each unit signal reaches 6-10 ten thousand, and the data volume of one frame reaches 3-5 k ten thousand. The cache of the computer is limited, so that the traditional Matlab analog modulation signal input method can only verify the input of 1 to several unit signals, often can only test the capturing function of the baseband processing FPGA, and cannot verify the subsequent tracking and bit synchronization functions. And secondly, even if the cache of a computer is large enough, a frame of data volume file is generated at one time by using Matlab, and the dynamic change sweep frequency tracking function test cannot be performed. And thirdly, the traditional Matlab data model generation method cannot be conveniently transmitted with an emulator, AGC feedback is realized, the baseband processing FPGA control energy stabilization function is verified, the traditional Matlab data model generation method cannot realize data consistency comparison between remote control data before modulation and remote control data after receiving and demodulation, closed loop test cannot be completed, and therefore error lock frame loss conditions of the baseband processing FPGA cannot be verified.
Disclosure of Invention
In order to simulate a carrier intermediate frequency signal which changes in real time and realize real-time closed loop test so as to ensure the functional test coverage rate of a baseband processing FPGA, the application provides a spread spectrum demodulation simulation verification system, which comprises: the system comprises an imitation data signal source generation module, an imitation sine and cosine wave generation module, an imitation code bias self-adaptive adjustment spread spectrum code generation module, an imitation spread spectrum modulation module, an imitation demodulation data receiving module, an imitation working state detection module and a scoreboard module;
the simulated data signal source generation module is used for generating a change data frame capable of judging whether to lose frames or not so as to give a meaningful data signal source according to the signal frequency;
the sine and cosine wave simulating generation module is used for modulating sine and cosine waves required by the carrier frequency simulation signal;
the spreading code generation module is used for generating a spreading code for spreading the data signal source according to the spreading frequency; generating 1023-bit spread spectrum codes according to a baseband processing FPGA spread spectrum code generation formula, and placing the 1023-bit spread spectrum codes in a read-only memory; generating 1 counter with initial value of 0 of 42 bits, the counter performs accumulated count according to code frequency and code bias generated code word, taking the counter value of high 10 bits as address of spread spectrum code memory, and reading out spread spectrum code;
the simulated spread spectrum modulation module is used for carrying out exclusive or on bit data generated by the simulated data signal source generation module and a spread spectrum code generated by the simulated code bias self-adaptive adjustment spread spectrum code generation module to obtain spread spectrum data, carrying out Binary Phase Shift Keying (BPSK) modulation on the spread spectrum data by using a sine value to obtain a modulated numerical value, and then adjusting the amplitude according to a voltage ratio set by initial parameters and an output AGC feedback value of an FPGA to obtain a final input intermediate frequency analog quantity;
the simulated demodulation data receiving module is used for receiving the remote control data which are output by the baseband processing FPGA in a spread spectrum demodulation way, carrying out serial-parallel conversion on the remote control data under the condition of remote control locking, starting to receive subsequent data after determining a frame head, and recording the data to an ACT array, namely, sending an actual measurement result to the scoreboard module for comparison after receiving a certain amount of data;
the simulated working state detection module is used for sending gating and clock baseband processing FPGA, receiving the internal working state of the FPGA, and comparing the Doppler frequency offset obtained by analyzing the working frame with the input Doppler frequency offset to obtain the test precision;
the scoreboard module is used for comparing the data of the EXP array of the simulated data signal source generation module with the data of the ACT array received by the simulated demodulation data receiving module, and if the data are consistent, the information of which frame is consistent is given; if the results are inconsistent, an error alarm is given, and the expected result and the actual measurement result are respectively given.
In one possible implementation manner, the data-like signal source generating module is configured to: constructing a 20bit frame header, a 16bit frame count and 464bit data bit mode to define a frame structure, generating a data frame according to the frame structure, packing and compressing the data frame into a stack, recording data in the stack into a record file, storing the data into an expected array EXP array, and sending the data to an integrator module as an expected value for subsequent data comparison;
generating a signal clock according to the signal frequency, counting at the rising edge of the signal clock, and outputting data of the data stack according to the count value, wherein the frame header is used for identifying the starting position of the data start, and the lengths of the data of each frame are consistent.
In one placeIn one possible implementation manner, the imitated sine and cosine wave generating module comprises a sine lookup table and a cosine lookup table, and a carrier frequency word f word Calculating and sine and cosine access address counters;
the sine lookup table and the cosine lookup table are respectively 1 complete sine wave value and cosine wave value, the number of the values is 13864, and binary data of which each value is 14 bits are respectively placed in 2 read-only memories; wherein the carrier frequency word f word The calculation formula is as follows:
f in the formula word For carrier frequency words, 16 bins; n represents binary bit width, fs is system sampling frequency, f Frequency of The carrier frequency can be adjusted in real time according to the receiving range of the FPGA;
the sine and cosine fetch address counter adopts a 32bit counter mode and is used for carrier frequency word f word Accumulating, namely taking high 14bit data as a lookup table address to obtain sine and cosine carriers with standard carrier frequencies capable of changing in real time; generating 1 32-bit address accumulator, obtaining frequency words through carrier frequency and working frequency, accumulating the frequency words by the address accumulator at each clock, taking the high 14-bit data of the accumulated result as the address of the read-only memory, and respectively obtaining corresponding sine and cosine carrier waves for modulating the data after spreading.
In one possible implementation manner, the carrier wave is a sine and cosine carrier wave which is swept from-Doppler frequency offset to +Doppler frequency offset;
the carrier frequency word = intermediate frequency-Doppler frequency offset is initialized, and the carrier frequency word is accumulated at each system clock, namely, the current carrier frequency word + sweep frequency change word; when the frequency is greater than or equal to the intermediate frequency plus Doppler frequency offset, each system clock decrements the carrier frequency word, namely the current carrier frequency word-sweep frequency change word; the frequency sweep frequency change word calculation mode is that the frequency sweep frequency change word of each clock calculated by the frequency sweep carrier change rate of 1us is added in the design.
In one possible implementation manner, the spreading code generating module with the code bias being adaptively adjusted includes a spreading code read-only memory, a code bias calculation, a code frequency word calculation and a spreading code fetch address counter.
In one possible implementation, the code bias calculation is used to: according to the code frequency offset obtained by the corresponding relation between Doppler frequency offset and code offset, the final code rate is obtained by the code frequency offset and spread spectrum frequency, and the code rate is 2 32 The codeword is calculated by the system operating frequency.
In one possible implementation manner, the spread spectrum simulating modulation module is used for: amplitude adjustment is carried out according to the AGC attenuation value fed back in the FPGA;
the adjusting method comprises the following steps: setting the highest bit of the AGC attenuation value as a sign bit, and taking the absolute value AGC_abs of the AGC attenuation value according to the sign of the sign bit; the sign bit is '1', which indicates that the input energy is too small, and the AGC_abs pieces DB are up-regulated; the symbol '0' indicates that the input energy is too large, down-regulating agc_abs number DB, 1.122 for current amplitude per 1DB increase, 1DB for current amplitude per 1.122 for attenuation.
In one possible implementation manner, the demodulation-like data receiving module is configured to: and receiving remote control data demodulated and output by the base band processing FPGA, defining a frame structure according to a 20bit frame header, a 16bit frame count and 464bit data bit mode, starting to receive 480bit data after receiving the 20bit frame header, storing the 480bit data in an ACT array, analyzing and printing according to a frame format, and generating a record file.
In one possible implementation manner, the working state simulating detection module is used for: the method comprises the steps of processing a workload telemetering state output by an FPGA (field programmable gate array) by a baseband, analyzing and printing according to a workload state frame format, generating a record file, and recording the current working state of the FPGA by the baseband, wherein the record file comprises at least one of a code loop locking state, a phase-locked loop locking state, a frequency-locked loop locking state, a bit locking state and Doppler frequency offset of the FPGA by the baseband.
In one possible implementation, the scoreboard module is to: comparing the data of the EXP array output by the analog data signal source generation module after the ACT array is received by the analog demodulation data receiving module, giving out the information of which frame is consistent, giving out an error alarm if the frame is inconsistent, and respectively giving out an expected result and an actual measurement result.
Due to the application of the technical scheme, compared with the prior art, the invention has the following beneficial effects:
(1) The method overcomes the defect that hardware joint measurement cannot detect all complex signals in complex algorithm logic in the baseband processing FPGA, and avoids hidden design trouble. In the prior art, the output data quantity is too large by utilizing Matlab modeling, and the problem of complete dynamic simulation test cannot be solved. According to the invention, by constructing the spread spectrum demodulation simulation verification system based on the baseband processing FPGA, the real-time changing data information can be simulated flexibly, static or dynamic sweep frequency input is generated according to the requirement, and energy adjustment is performed in time in response to the feedback AGC of the FPGA, so that the simulation verification coverage rate of the simulation system to the baseband processing FPGA is improved greatly.
(2) The automatic test is realized, the input expected data EXP array and the actual demodulation receiving data ACT array are collected in real time through the scoreboard module, and are compared, the demodulation error condition is given in real time, and the fault location is convenient.
(3) In order to realize the universality to the maximum extent, the invention provides a system with configurable clock frequency, voltage ratio, intermediate frequency, doppler frequency offset, carrier wave change rate, signal frequency and spread spectrum frequency parameters. The applicability is expanded to spread spectrum demodulation systems in different aerospace models, and the construction of the aerospace product type spectrum is promoted.
(4) The operation platform of the invention is a VCS platform of Synopsys company and has stronger development property. With the continuous development and progress of aerospace products, the VCS platform can synchronously perform technical development and upgrading, and sustainable technical support is provided for ground simulation work of the aerospace products.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a system provided in an exemplary embodiment of the present invention;
FIG. 2 is a flowchart of a set up working bad block table provided by an exemplary embodiment of the present invention;
fig. 3 is a flowchart of spreading code generation according to an exemplary embodiment of the present invention;
fig. 4 is a flowchart for generating a constructed modulated carrier signal according to an exemplary embodiment of the present invention;
fig. 5 is a flowchart for constructing an intermediate frequency analog output according to an exemplary embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
The embodiment provides a spread spectrum demodulation simulation verification system based on a baseband processing FPGA, which is used for providing a closed-loop working environment for the baseband processing FPGA, and particularly can overcome the problems that the output data volume is too large and complete dynamic simulation test cannot be performed in the prior simulation technology, flexibly simulate real-time changing data information, timely respond to the FPGA feedback AGC to perform energy adjustment, and realize the closed-loop simulation verification system for automatic comparison test
As shown in fig. 1, the system specifically includes:
the simulated data signal source generation module 1 is used for generating a change data frame capable of judging whether to lose the frame or not so as to give a meaningful data signal source according to the signal frequency;
the sine-cosine wave imitation generation module 2 is used for obtaining sine-cosine signals for carrier modulation according to the calculated carrier frequency;
the spreading code generation module 3 for adaptively adjusting the simulated code bias comprises a spreading code read-only memory, code bias calculation, code frequency word calculation and a spreading code fetch address counter, and generates a spreading code for spreading the data signal source;
the spread spectrum simulating modulation module 4 carries out BPSK modulation on the spread spectrum signal by using a sine and cosine signal and adjusts the amplitude according to AGC feedback;
the simulated demodulation data receiving module 5 is used for receiving demodulation data output after the baseband processing FPGA8 is spread and demodulated;
the working state imitation detection module 6 is used for receiving the workload telemetry state output by the baseband processing FPGA 8;
and the scoreboard module 7 is used for consistency comparison of the remote control data before modulation and the demodulation data after spread spectrum demodulation of the baseband processing FPGA 8.
Furthermore, the spread spectrum demodulation simulation verification system of the baseband processing FPGA can carry out environment configuration through configuration parameters including system clock frequency, intermediate frequency, signal frequency and spread spectrum frequency, and improves the adaptability of the baseband processing FPGA simulation system. The sensitivity test is realized by modifying the voltage ratio, the static Doppler frequency offset test is realized by setting the carrier change rate to 0, the dynamic sweep frequency input is generated by setting the carrier change rate to a specific value, and the Doppler frequency capture tracking frequency error test is realized by setting the Doppler frequency offset, so that the test coverage rate of the baseband processing FPGA simulation system is improved.
In a further preferred embodiment, the simulated data signal source generating module 1 is further configured to generate and simulate the demodulation data receiving module 5 to receive the aligned expected EXP array, and generate the record file send.
In a further preferred embodiment, the demodulation-like data receiving module 5 is specifically configured to receive the output data after three-wire system demodulation, and generate a record file tm_rev.
In a further preferred embodiment, the working state simulating detection module 6 is specifically configured to generate a telemetry clock and gate control, and receive the current working state of the FPGA fed back by the baseband processing FPGA 8.
The system is written by using Verilog codes, a used platform is a simulation verification tool VCS of Synopsys company, and a closed-loop working environment is provided for baseband processing FPGA.
The idea of the system for implementing the above embodiment is: spreading the serial data source signal generated by the analog data signal source generating module 1 by using the spreading code generated by the spreading code generating module 3 with the self-adaptive adjustment of the analog code bias, performing BPSK modulation on the spread signal by using the sine and cosine signal generated by the analog sine and cosine wave generating module 2, outputting the signal to the baseband processing FPGA8, and comparing the demodulated data of the baseband processing FPGA8 with the data source generated by the analog data signal source generating module 1 through the analog demodulation data receiving module 5 to realize a closed loop simulation system with automatic comparison.
To achieve the above object, the method of the present invention mainly comprises the steps of:
step 1: firstly, an imitation data signal source generating module 1, an imitation sine and cosine wave generating module 2, an imitation code bias self-adaptive adjustment spread spectrum code generating module 3, an imitation spread spectrum modulating module 4, an imitation demodulation data receiving module 5, an imitation working state detecting module 6 and a scoreboard module 7 are constructed as shown in fig. 1.
Step 2: referring to fig. 2, when the dummy data signal source generation module 1 is specifically constructed, a construction continuous data signal transmission flow is performed. When the power-on is started, a data frame is generated according to a 20bit frame header+16 bit frame count+464 bit frame structure, the frame header is unchanged and used for identifying the starting position of data, the length of each frame of data is consistent, the frame count is used for counting the number of frames, the initial frame count is 0 and used for judging whether the frame is lost, 464bit data bits are randomly generated, and a meaningful data frame capable of judging whether the frame is lost is obtained. The data frames are then packed and compressed into a stack in a stack mode in the SystemVerilog language, and the data in the stack is recorded into a recording file send. Generating a signal clock according to the signal frequency, starting counting at the rising edge of the signal clock, outputting data of a data stack according to a count value, immediately storing stack data into an expected 500bit array EXP array to be sent to an integrator module as an expected value for subsequent data comparison when one frame of data is transmitted and the count value is equal to 499. And then the current stack is emptied, next frame data is generated, and the stack is continuously pushed in, so that continuous data transmission is ensured.
Step 3: referring to fig. 3, when the spreading code generation module 3 for simulating the adaptive adjustment of the code offset is specifically constructed, a spreading code stream generation flow is constructed. The 1023bit spreading code is put into the read-only memory. Calculating code bias according to the corresponding relation between Doppler frequency bias and code bias, obtaining actual code frequency by spreading frequency plus code bias, and passing through code rate of 2 32 The system working frequency is calculated to obtain a code word, and the code word is calculated by calculating the change code bias = carrier change rate spread spectrum frequency/radio frequency, and then calculating the change code word = change code bias 2 32 The system operating frequency is changed to obtain a codeword. And accumulating codewords on the address accumulation counter of the spreading code at the rising edge of the system clock, and when the timer counts to 1 second, accumulating the changed codewords by the address counter of the spreading code, taking 10bit data higher than the address accumulator as the address of the read-only memory of the spreading code, and reading the spreading code. The spreading code must be completely consistent with the internal spreading code of the baseband processing FPGA, and the generated spreading code process is recorded in the file pncode.
Step 4: as shown in fig. 4, when the pseudo sine and cosine wave generation module 2 is specifically constructed, a modulated carrier signal generation flow is constructed. And leading into a sine lookup table and a cosine lookup table of 1 complete sine and cosine waveform values, wherein the number of the values is 13864, and binary data of 14 bits of each value are respectively placed in 2 read-only memories. Then, calculating initial carrier frequency=intermediate frequency+Doppler frequency offset, and calculating carrier frequency word=carrier frequency×2 32 And (3) the system working frequency, and accumulating the carrier frequency words when the timer counts to 1us, namely the current carrier frequency word and the sweep frequency change word. The current carrier frequency is greater than or equal to the intermediate frequency plus Doppler frequency offset, and the carrier frequency word is decremented when the timer counts to 1us, namely the current carrier frequency word-sweep frequency change word. The sweep frequency change word is calculated by calculating carrier frequency change frequency word=carrier frequency change rate 2 32 System operating frequency 2. Generating 1 32-bit address accumulator by carrier frequencyThe address accumulator accumulates the frequency words in each clock, takes the high 14-bit data of the accumulated result as the address of the read-only memory, and respectively obtains corresponding sine and cosine carriers for modulating the spread data subsequently;
step 5: as shown in fig. 5, when the spread spectrum simulating modulation module 4 is specifically constructed, an intermediate frequency analog quantity output flow is constructed. Amplitude adjustment can be performed according to an AGC attenuation voltage value fed back in the FPGA, an AGC lookup table is imported into the read-only memory at the initialization time, and the initial attenuation value is set to be 1. After the initialization is finished, the AGC voltage value fed back by the FPGA is used as an AGC lookup table address to obtain an AGC attenuation db value, the highest symbol bit of the AGC attenuation db value is judged to be 1, namely a negative number, and the negative number is added by 1, otherwise, the attenuation times are obtained unchanged. If the AGC decay db value is negative, it is indicated that the input energy is too small, up-turned, so 1db times 1.122; if the AGC decay db value is positive, it is stated that the input energy is too large, down-turned, and thus 1db divided by 1 times 1.122. The voltage ratio parameter set by the attenuation value after attenuation is the current voltage amplitude.
After the initialization is finished, the data signal generated by the simulated data signal source generation module 1 and the spread spectrum code signal generated by the spread spectrum code generation module 3 with the simulated code bias being adaptively adjusted are subjected to exclusive or, if the signal after the exclusive or is 1, the sine signal output by the simulated sine and cosine wave generation module 2 is added with 1 in a reverse mode, and otherwise, the signal is unchanged, and the primary modulation signal Sim1 is obtained. Taking an absolute value of Sim1, and multiplying the calculated voltage amplitude to obtain Sim2. If Sim2 is at most 1, it indicates that the voltage value overflows, and the highest bit of Sim2 is set to bit 0, and the other bits are all 1. If Sim1 is 1 at the highest position, sim2 is inverted by 1. And outputting the Sim2 obtained through final calculation to the FPGA as an intermediate frequency analog signal.
Step 6: as shown in fig. 1, the simulated demodulation data receiving module 5 is constructed, when the demodulated lock signal output by the baseband processing FPGA8 is low, the demodulated data is received at the falling edge of the demodulated clock, when the frame header is received, the counter counts from 20, the frame header is pushed to the stack, then the stack is pushed once every time 1bit of data is received, when the value of the counter reaches 499, the stack is stored in the ACT array to be sent to the scoreboard to be compared with the EXP array output by the simulated data signal source generating module 1, and meanwhile, the data is stored in the file tm_rev.
Step 7: as shown in fig. 1, an imitation working state detection module 6 is constructed, a telemetry clock and telemetry gating are sent to a baseband processing FPGA8, telemetry data output by the baseband processing FPGA8 is received, and working state information is obtained and stored in tm_rev.
Step 8: as shown in fig. 1, a scoreboard module 7 is constructed. Comparing the EXP array and the ACT array output by the simulated demodulation data receiving module 5, giving out the information of the same frame number, and giving out the error alarm of the frame number if the information of the frame number is inconsistent, and respectively giving out the expected result and the actual measurement result.
Specific examples are set forth herein to illustrate the invention in detail, and the description of the above examples is only for the purpose of aiding in understanding the core concept of the invention. It should be noted that any obvious modifications, equivalents, or other improvements to those skilled in the art without departing from the inventive concept are intended to be included in the scope of the present invention.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
It should be understood that references herein to "a plurality" are to two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description of the preferred embodiments of the present application is not intended to limit the invention to the particular embodiments of the present application, but to limit the scope of the invention to the particular embodiments of the present application.
Claims (9)
1. A spread spectrum demodulation simulation verification system, the system comprising: the system comprises an imitation data signal source generation module, an imitation sine and cosine wave generation module, an imitation code bias self-adaptive adjustment spread spectrum code generation module, an imitation spread spectrum modulation module, an imitation demodulation data receiving module, an imitation working state detection module and a scoreboard module;
the simulated data signal source generation module is used for generating a change data frame capable of judging whether to lose frames or not so as to give a meaningful data signal source according to the signal frequency; constructing a 20bit frame header, a 16bit frame count and 464bit data bit mode to define a frame structure, generating a data frame according to the frame structure, packing and compressing the data frame into a stack, recording data in the stack into a record file, storing the data into an expected array EXP array, and sending the data to an integrator module as an expected value for subsequent data comparison;
the sine and cosine wave simulating generation module is used for modulating sine and cosine waves required by the carrier frequency simulation signal;
the spreading code generation module is used for generating a spreading code for spreading the data signal source according to the spreading frequency; generating 1023-bit spread spectrum codes according to a baseband processing FPGA spread spectrum code generation formula, and placing the 1023-bit spread spectrum codes in a read-only memory; generating 1 counter with initial value of 0 of 42 bits, the counter performs accumulated count according to code frequency and code bias generated code word, taking the counter value of high 10 bits as address of spread spectrum code memory, and reading out spread spectrum code;
the simulated spread spectrum modulation module is used for carrying out exclusive or on bit data generated by the simulated data signal source generation module and a spread spectrum code generated by the simulated code bias self-adaptive adjustment spread spectrum code generation module to obtain spread spectrum data, carrying out Binary Phase Shift Keying (BPSK) modulation on the spread spectrum data by using a sine value generated by the simulated sine wave generation module to obtain a modulated numerical value, outputting the modulated numerical value to a baseband processing Field Programmable Gate Array (FPGA), and then adjusting the amplitude according to a voltage ratio set by an initial parameter and an output AGC feedback value of the FPGA to obtain a final input intermediate frequency analog quantity;
the simulated demodulation data receiving module is used for receiving the remote control data output by the baseband processing FPGA in a spread spectrum demodulation way, carrying out serial-parallel conversion on the remote control data under the condition of remote control locking, defining a frame structure according to a 20bit frame head+16 bit frame count+464 bit data bit mode, starting to receive 480bit data after receiving the 20bit frame head, storing the 480bit data in an ACT array, and carrying out analysis and printing according to a frame format to generate a record file;
the simulated working state detection module is used for sending gating and clocks to the baseband processing FPGA, receiving the internal working state of the FPGA, and comparing the Doppler frequency offset obtained by analyzing the working frame with the input Doppler frequency offset to obtain the test precision;
the scoreboard module is used for comparing the data of the EXP array of the simulated data signal source generation module with the data of the ACT array received by the simulated demodulation data receiving module, and if the data are consistent, the information of which frame is consistent is given; if the results are inconsistent, an error alarm is given, and the expected result and the actual measurement result are respectively given.
2. The system of claim 1, wherein the simulated data signal source generation module is configured to:
generating a signal clock according to the signal frequency, starting counting at the rising edge of the signal clock, and outputting data of the data stack according to the count value; each frame of data is consistent in length by identifying the starting position of the beginning of the data by the frame header.
3. The system of claim 1, wherein the pseudo sine and cosine wave generation module comprises a sine lookup table and a cosine lookup table, a carrier frequency word f word Calculating and sine and cosine access address counters;
wherein the sine lookup table and the cosine lookup table are respectively 1 complete sine wave waveform value and 1 complete cosine wave waveform value, wherein the carrier frequency word f word The calculation formula is as follows:
f in the formula word For carrier frequency words, 16 bins; n represents binary bit width, fs is system sampling frequency, f Frequency of The carrier frequency can be adjusted in real time according to the receiving range of the FPGA.
4. The system of claim 3, wherein the carrier implements sine and cosine carriers swept from-doppler frequency offset to +doppler frequency offset;
the method comprises the steps of firstly, carrying out carrier frequency word accumulation on a carrier frequency word in each system clock, wherein the initial carrier frequency word = intermediate frequency-Doppler frequency offset, and carrying out accumulation on the carrier frequency word, namely a current carrier frequency word + sweep frequency change word; when the frequency is greater than or equal to the intermediate frequency plus Doppler frequency offset, each system clock decrements the carrier frequency word, namely the current carrier frequency word-sweep frequency change word; the frequency sweep frequency change word calculation mode is that the frequency sweep frequency change word of each clock calculated by the frequency sweep carrier change rate of 1us is added in the design.
5. The system of claim 1, wherein the spreading code generation module for the adaptive adjustment of the pseudo code bias comprises a spreading code read only memory, a code bias calculation, a code frequency word calculation, and a spreading code fetch address counter.
6. The system of claim 5, wherein the code bias calculation is configured to: according to the code frequency offset obtained by the corresponding relation between Doppler frequency offset and code offset, the final code rate is obtained by the code frequency offset and spread spectrum frequency, and the code rate is 2 32 The codeword is calculated by the system operating frequency.
7. The system of claim 1, wherein the analog spread spectrum modulation module is configured to: amplitude adjustment is carried out according to the AGC attenuation value fed back in the FPGA;
the adjusting method comprises the following steps: setting the highest bit of the AGC attenuation value as a sign bit, and taking the absolute value AGC_abs of the AGC attenuation value according to the sign of the sign bit; the sign bit is '1', which indicates that the input energy is too small, and the AGC_abs pieces DB are up-regulated; the symbol '0' indicates that the input energy is too large, down-regulating agc_abs number DB, 1.122 for current amplitude per 1DB increase, 1DB for current amplitude per 1.122 for attenuation.
8. The system of claim 1, wherein the simulated operating condition detection module is configured to: the method comprises the steps of processing a workload telemetering state output by an FPGA (field programmable gate array) by a baseband, analyzing and printing according to a workload state frame format, generating a record file, and recording the current working state of the FPGA by the baseband, wherein the record file comprises at least one of a code loop locking state, a phase-locked loop locking state, a frequency-locked loop locking state, a bit locking state and Doppler frequency offset of the FPGA by the baseband.
9. The system of claim 1, wherein the scoreboard module is to: comparing the data of the EXP array output by the analog data signal source generation module after the ACT array is received by the analog demodulation data receiving module, giving out the information of which frame is consistent, giving out an error alarm if the frame is inconsistent, and respectively giving out an expected result and an actual measurement result.
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