CN114388474A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN114388474A CN114388474A CN202011118950.6A CN202011118950A CN114388474A CN 114388474 A CN114388474 A CN 114388474A CN 202011118950 A CN202011118950 A CN 202011118950A CN 114388474 A CN114388474 A CN 114388474A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims abstract description 134
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 2
- 229940094989 trimethylsilane Drugs 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor structure. The semiconductor structure includes: a semiconductor substrate; the semiconductor device comprises an interlayer dielectric layer positioned on a semiconductor substrate and a metal interconnection structure positioned in the interlayer dielectric layer; and a dielectric covering layer positioned above the metal interconnection structure, wherein the dielectric covering layer comprises a first dielectric layer and a second dielectric layer which are sequentially stacked from bottom to top, and the first dielectric layer has a rugged upper surface structure. The invention can reduce RC delay caused by metal wires and insulating media.
Description
Technical Field
The present invention relates to the field of semiconductor structures, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
As integrated circuits are developed, feature sizes are continuously reduced, and current densities introduced by metal wires are increased sharply. Meanwhile, the increase in the degree of integration of the chip leads to an increase in RC delay caused by the resistance of the metal wire and the capacitance of the interlayer insulating dielectric, which has a negative effect on the speed of the device. Therefore, a contrivance is required to reduce the RC delay.
Disclosure of Invention
To solve the above problems, the present invention provides a semiconductor structure and a method for manufacturing the same, which can reduce RC delay.
In a first aspect, the present invention provides a semiconductor structure comprising:
a semiconductor substrate;
the semiconductor substrate comprises an interlayer dielectric layer positioned on the semiconductor substrate and a metal interconnection structure positioned in the interlayer dielectric layer;
a dielectric capping layer over the metal interconnect structure, the dielectric capping layer comprising a first dielectric layer and a second dielectric layer sequentially stacked from bottom to top, wherein the first dielectric layer has an uneven upper surface structure.
Optionally, the first dielectric layer comprises one of SiON and SiN.
Optionally, the second dielectric layer comprises one of SiCN and SiC.
Optionally, the metal interconnection structure is a metal wire or a metal plug and a metal wire located thereon.
Optionally, the interlayer dielectric layer is a low-k dielectric, and the metal interconnection structure is made of copper.
In a second aspect, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate;
forming an interlayer dielectric layer and a metal interconnection structure positioned in the interlayer dielectric layer on the semiconductor substrate;
forming a first dielectric layer on the metal interconnection structure by adopting plasma enhanced chemical vapor deposition;
making the thickness of the first dielectric layer uneven through photoetching and etching processes;
a second dielectric layer is formed over the first dielectric layer.
Optionally, the first dielectric layer comprises one of SiON and SiN.
Optionally, wherein forming a second dielectric layer over the first dielectric layer comprises:
and forming a second dielectric layer on the first dielectric layer by adopting plasma enhanced chemical vapor deposition.
Optionally, the second dielectric layer comprises one of SiCN and SiC.
Optionally, the metal interconnection structure is formed by a single damascene or dual damascene process, and the material of the metal interconnection structure comprises copper.
According to the semiconductor structure and the manufacturing method thereof provided by the invention, the dielectric covering layer positioned above the metal interconnection structure comprises the first dielectric layer and the second dielectric layer which are sequentially stacked from bottom to top, wherein the first dielectric layer is provided with the rugged upper surface structure, the dielectric constant of the dielectric layer is reduced, and the RC delay caused by the resistance of the metal wire and the capacitance of the interlayer insulating medium is reduced.
Drawings
FIG. 1A is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention;
FIG. 1B is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention;
fig. 2 to 5 are schematic cross-sectional views of devices corresponding to steps of a method for manufacturing a semiconductor structure according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Fig. 1A illustrates a cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present invention. In which a semiconductor substrate 100 is first provided, and an interlayer dielectric layer 101 is disposed above the semiconductor substrate 100, wherein the interlayer dielectric layer 101 may be typically silicon dioxide or other low-k dielectric, such as silicon glass (FSG). In the interlayer dielectric layer 101, a copper interconnection structure, which is a dual damascene structure in this embodiment, is formed, and since copper is not easily adhered to the interlayer dielectric layer 101 and is easily diffused in the interlayer dielectric layer 101, a barrier layer 102 is deposited after a trench is etched in the interlayer dielectric layer 101 during a copper wiring process. Copper 103 is then filled in the trench after a copper deposition process. Finally, there is a dielectric cap layer 104 over the copper interconnect structure. Specifically, in this embodiment, the dielectric capping layer 104 includes a first dielectric layer 1041 and a second dielectric layer 1042 stacked in sequence from bottom to top, wherein the first dielectric layer 1041 has an uneven upper surface structure, which can increase a contact area between the first dielectric layer 1041 and the second dielectric layer 1042. Typically, the first dielectric layer 1041 includes one of SiON and SiN. The second dielectric layer 1042 includes one of SiCN and SiC.
Fig. 1B illustrates a cross-sectional view of a semiconductor structure provided in accordance with another embodiment of the present invention. Compared with fig. 1A, the copper interconnect structure in this embodiment is a single damascene structure, and other portions are similar to those in fig. 1A and will not be described again.
Next, detailed steps of forming a semiconductor structure according to a manufacturing method of one embodiment of the present invention are described with reference to fig. 2 to 5.
First, as shown in fig. 2, there is shown a schematic cross-sectional view of the device after forming an interlevel dielectric layer and a copper interconnect structure on a semiconductor substrate 200. In this embodiment, the copper interconnect structure is a dual damascene structure.
As shown in fig. 2, a semiconductor substrate 200 is provided, and the semiconductor substrate 200 may include Si, SiC, SiGe, SiGeC, Ge alloys, GeAs, InAs, InP, and other group III-V or II-VI compound semiconductors. The semiconductor substrate 200 includes various isolation structures, such as shallow trench isolation. A device layer may be formed on the semiconductor substrate. The invention is applied to the back-end process in the semiconductor manufacturing, and the contact part process of a device can be completed on the substrate, or several metal interconnection line processes can be completed on the substrate. An etch stop layer 210, which may be made of nitrogen-doped silicon carbide (NDC), may optionally be deposited on the semiconductor substrate 200 by Chemical Vapor Deposition (CVD). As an implementation mode, when the chemical vapor deposition is carried out, the power is 200-400W, the heating is carried out to ensure that the temperature in the cavity is 300-400 ℃, the pressure in the cavity is 2-5 Torr, the gas flow of trimethyl silane or tetramethyl silane is 100-200 cubic centimeters per minute, the gas flow of He is 350-400 cubic centimeters per minute, and NH is carried out3The gas flow is 300-500 cubic centimeters per minute, and the deposition time lasts for 3 s. Then, in the etching stop layer 2An interlayer dielectric layer 201 is deposited on the substrate 10, a Low-K dielectric is selected, the dielectric constant K is generally less than 3, the interlayer dielectric layer is usually prepared by a chemical vapor spin-on process (SOG), a spin-on coating technique or a chemical vapor deposition technique, and the material of the interlayer dielectric layer can be fluorine-doped silicate glass (FSG), silicon oxide or Low K material.
Next, the interlayer dielectric layer 201 is etched according to the shape of the metal wiring to be formed, forming a trench and a via hole. For the single Damascus process, a metal plug may be formed under the interlayer dielectric layer, and at the moment, only a groove needs to be formed for forming a copper wiring in the following process; for the dual damascene process, other metal wirings may have been formed on the semiconductor substrate, and at this time, the next layer of metal plug and copper wiring need to be formed at one time, and the trench and the via should be formed by etching at one time. Next, a diffusion barrier layer 202 and a copper metal layer 203 are sequentially formed in the trench and the via. The diffusion barrier layer 202 may be formed by Physical Vapor Deposition (PVD). The diffusion barrier layer material is a metal or metal compound, such as tantalum, tantalum nitride, titanium nitride, tungsten, an alloy of tungsten nitride, or a composition thereof. In addition, the diffusion barrier layer may include a plurality of film layers. Preferably, a cobalt (Co) enhancement layer (not shown) is formed on the diffusion barrier layer 202, followed by a copper seed layer (not shown). The cobalt enhancement layer can improve the electromigration capability of the copper interconnection, and simultaneously effectively enhance the copper filling capability in the groove with smaller size. A copper metal layer 203 is formed on the copper seed layer using an electrochemical plating method. Then, a Chemical Mechanical Polishing (CMP) process is used to process the copper metal layer to remove the excess copper metal layer until the interlayer dielectric layer 201 is exposed, and the chemical mechanical polishing is stopped when the surfaces of the copper metal layer 203 and the interlayer dielectric layer 201 are flush.
As shown in fig. 3, a first dielectric layer 2041 is formed over the copper interconnect structure using a Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), or e-beam evaporation process. As an implementation mode, the power is 100-2000W during plasma enhanced chemical vapor deposition, the temperature in the cavity is heated to 300-400 ℃, the pressure in the cavity is 1-900 mTorr, and the gas flow of trimethyl silane or tetramethyl silane is 100-200 cubic centimeters per minute. Typically, the first dielectric layer 2041 includes one of SiON and SiN.
As shown in fig. 4, after the first dielectric layer 2041 is formed, the thickness of the first dielectric layer 2041 becomes non-uniform through photolithography and etching processes. Of course, other processes may be used to realize the first dielectric layer 2041 having an uneven upper surface structure.
As shown in fig. 5, a second dielectric layer 2042 is formed over the first dielectric layer 2041 using Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), or e-beam evaporation, followed by chemical mechanical polishing of the second dielectric layer 2042. Typically, the second dielectric layer 2042 comprises one of SiCN and SiC. The second dielectric layer 2042 and the first dielectric layer 2041 having the uneven upper surface together form a covering layer of the semiconductor structure. When thicker cap layers are desired, depending on the particular process requirements, the operations may be repeated to form two or more cap layers, with reference to fig. 3-5.
By applying the semiconductor structure and the manufacturing method thereof provided by the embodiment of the invention, the dielectric covering layer positioned above the copper interconnection structure comprises the first dielectric layer and the second dielectric layer which are sequentially stacked from bottom to top, wherein the first dielectric layer has an uneven upper surface structure, the dielectric constant of the dielectric layer is reduced, and the RC delay caused by the resistance of the metal wire and the capacitance of the interlayer insulating medium is reduced. In addition, the contact area between the first dielectric layer and the second dielectric layer can be increased, the adhesion between the first dielectric layer and the second dielectric layer is increased, the leakage current between the interconnection metal wires is reduced, the electromigration caused by the outward diffusion of copper is reduced, and the reliability of the device is improved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A semiconductor structure, comprising:
a semiconductor substrate;
the semiconductor substrate comprises an interlayer dielectric layer positioned on the semiconductor substrate and a metal interconnection structure positioned in the interlayer dielectric layer;
a dielectric capping layer over the metal interconnect structure, the dielectric capping layer comprising a first dielectric layer and a second dielectric layer sequentially stacked from bottom to top, wherein the first dielectric layer has an uneven upper surface structure.
2. The semiconductor structure of claim 1, wherein the first dielectric layer comprises one of SiON and SiN.
3. The semiconductor structure of claim 1, wherein the second dielectric layer comprises one of SiCN and SiC.
4. The semiconductor structure of claim 1, wherein the metal interconnect structure is a metal wire or a metal plug and a metal wire thereon.
5. The semiconductor structure of claim 1, wherein the interlevel dielectric layer is a low-k dielectric; the metal interconnection structure is made of copper.
6. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate;
forming an interlayer dielectric layer and a metal interconnection structure positioned in the interlayer dielectric layer on the semiconductor substrate;
forming a first dielectric layer on the metal interconnection structure by adopting plasma enhanced chemical vapor deposition;
making the thickness of the first dielectric layer uneven through photoetching and etching processes;
a second dielectric layer is formed over the first dielectric layer.
7. The method of claim 6, wherein the first dielectric layer comprises one of SiON and SiN.
8. The method of claim 6, wherein forming a second dielectric layer over the first dielectric layer comprises:
and forming a second dielectric layer on the first dielectric layer by adopting plasma enhanced chemical vapor deposition.
9. The method of claim 8, wherein the second dielectric layer comprises one of SiCN and SiC.
10. The method of claim 6, wherein the metal interconnect structure is formed by a single damascene or dual damascene process, and wherein the material of the metal interconnect structure comprises copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011118950.6A CN114388474A (en) | 2020-10-19 | 2020-10-19 | Semiconductor structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011118950.6A CN114388474A (en) | 2020-10-19 | 2020-10-19 | Semiconductor structure and manufacturing method thereof |
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| CN114388474A true CN114388474A (en) | 2022-04-22 |
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