CN114388428A - Method and device for optimizing flatness of dielectric layer - Google Patents
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- 238000005498 polishing Methods 0.000 claims description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 49
- 239000010409 thin film Substances 0.000 claims description 30
- 229920005591 polysilicon Polymers 0.000 claims description 22
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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Abstract
The embodiment of the application discloses a method and a device for optimizing the flatness of a dielectric layer, the method is used for an integrated circuit device, the surface of the integrated circuit device is divided into a dense area and an open area, device bulges exist in the dense area, and no device bulges exist in the open area, the method comprises the following steps: forming a film on the integrated circuit device to generate a dielectric layer and a first grinding layer; carrying out planarization treatment on the first grinding layer to obtain a first grinding surface, wherein the treated first grinding surface is positioned between the dielectric layer and the first grinding layer; and etching the first grinding surface based on the etching proportion of the dielectric layer and the first grinding layer to obtain a second grinding surface, wherein the second grinding surface is positioned on the dielectric layer, and the flatness of the grinding surface is greater than the flatness threshold value. The technology provided by the scheme can reduce the overall drop of the dielectric layer to the minimum, not only meets the process requirements, but also greatly increases the subsequent process window.
Description
Technical Field
The embodiment of the application relates to the technical field of semiconductors, in particular to a method and a device for optimizing flatness of a dielectric layer.
Background
In a semiconductor manufacturing process, a semiconductor surface needs to be planarized and ground, and the thickness is controlled within a corresponding process line width, for example, in a current integrated circuit, the surface of a wafer is polished with high precision mainly by a Chemical Mechanical Polishing (CMP) technology, and the global flatness difference of 100A to 1000A (equivalent to an atomic level of 10 to 100nm) and ultrahigh flatness can be achieved. However, with the continuous refinement of the line width of the semiconductor process, the requirement for the CMP planarization is higher and higher, and the planarization limit exists in the conventional material planarization process, so that the global fall may not satisfy the requirement of the advanced process for the overall planarization.
In the prior art, the process flow of FDSOI generally uses an Inter Layer Dielectric (ILD) -CMP technique, i.e., a planarization process for a single material. The method still has defects in the global planarization height, the global fall can still reach 150-300A, and the ultra-high precision process requirement cannot be met.
Disclosure of Invention
The embodiment of the application provides a method and a device for optimizing the flatness of a dielectric layer. The technical scheme is as follows:
in one aspect, a method for optimizing flatness of a dielectric layer is provided, the method comprising:
the method is used for an integrated circuit device, the surface of the integrated circuit device is divided into a dense area and an open area, device bulges exist in the dense area, and the open area is free of the device bulges, and the method comprises the following steps:
forming a film on an integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is positioned on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the open area after the film forming treatment have different flatness;
carrying out planarization treatment on the first grinding layer to obtain a first grinding surface, wherein the planarization treatment process comprises carrying out Chemical Mechanical Polishing (CMP) treatment on the first grinding layer, and the treated first grinding surface is positioned between the dielectric layer and the first grinding layer;
and etching the first grinding surface based on the etching proportion of the dielectric layer and the first grinding layer to obtain a second grinding surface, wherein the second grinding surface is positioned on the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold value.
Specifically, the dielectric layer is filled with an oxide film layer and is formed by an oxide, and the thickness of the oxide film layer is 4000A; the first grinding layer is a polycrystalline silicon thin film layer, and the thickness of the polycrystalline silicon thin film layer is 2000-2500A;
specifically, the planarizing the first polishing layer to obtain a first polishing surface includes:
carrying out polysilicon film planarization treatment on the first grinding layer in the dense area and the open area after film formation;
stopping performing chemical mechanical polishing when the oxide film layer is in grinding contact to obtain the first grinding surface;
the flatness of the first grinding surface is smaller than the flatness threshold, and the hollow area has a recess depth of at least 100A relative to the polycrystalline silicon thin film layer of the dense area.
Specifically, the etching the first grinding surface based on the etching ratio of the dielectric layer to the first grinding layer to obtain a second grinding surface includes:
determining an etching ratio of the dielectric layer and the first polishing layer based on the recess depth of the first polishing surface;
and etching the oxide film layer and the polycrystalline silicon film layer in the first grinding surface based on the etching proportion to obtain the second grinding surface.
Specifically, the etching the oxide film layer and the polysilicon film layer in the first grinding surface based on the etching proportion to obtain the second grinding surface includes:
determining an etching depth based on the etching proportion and the thickness of a target dielectric layer, wherein the etching depth is greater than the maximum thickness of the polycrystalline silicon thin film after planarization treatment, and the thickness of the target dielectric layer is determined according to a semiconductor manufacturing process;
etching the oxide film layer and the polycrystalline silicon film layer in the first grinding surface based on the etching proportion and the etching depth to obtain a second grinding curved surface; the flatness of the second grinding curved surface is smaller than the flatness threshold, and the second grinding curved surface has a global fall of at least 100A;
and carrying out oxide film planarization treatment on the second grinding curved surface to obtain the second grinding surface.
Specifically, after the integrated circuit device is subjected to film forming treatment, at least a height difference of 600-800A exists between the polycrystalline silicon thin film layer and the oxide film layer.
Specifically, the thickness of the target dielectric layer is 600-800A, the etching ratio of the polycrystalline silicon thin film layer to the oxide film layer is 0.9:1, and the etching depth is 1000A.
In another aspect, an apparatus for optimizing flatness of a dielectric layer is provided, the apparatus is used for an integrated circuit device, the surface of the integrated circuit device is divided into a dense region and an open region, the dense region has device bumps, and the open region has no device bumps, the apparatus includes:
the film forming module is used for performing film forming treatment on an integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is positioned on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer, corresponding to the dense area and the open area, after the film forming treatment have different flatness;
the planarization processing module is used for carrying out planarization processing on the first grinding layer to obtain a first grinding surface, wherein the planarization processing process comprises the step of carrying out Chemical Mechanical Polishing (CMP) processing on the first grinding layer, and the processed first grinding surface is positioned between the dielectric layer and the first grinding layer;
and the etching module is used for etching the first grinding surface based on the etching proportion of the dielectric layer and the first grinding layer to obtain a second grinding surface, wherein the second grinding surface is positioned on the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold value.
In another aspect, a computer device is provided, the computer device comprising a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the method of dielectric layer planarity optimization as claimed above.
The beneficial effect that above-mentioned technical scheme brought includes at least: when the integrated circuit device is subjected to film forming treatment, a polysilicon thin film layer is additionally added on the outer side of the dielectric layer to serve as a first grinding layer, the first grinding layer is subjected to polysilicon thin film planarization treatment, and when an oxide film layer is ground, chemical mechanical polishing is stopped; because the two film layers formed by film forming are not horizontal planes, the integrated circuit device after grinding comprises an oxide film layer and a polycrystalline silicon film layer; and at the moment, continuously determining the etching proportion and the etching depth according to the depression depth on the first grinding surface and the thickness of the target dielectric layer, etching the first grinding surface to obtain a second grinding curved surface, and finally performing oxide film planarization treatment to obtain the second grinding surface. The overall fall is reduced to the minimum, so that the process requirements are met, and the subsequent process window is greatly increased.
Drawings
FIG. 1 is a schematic illustration of dielectric layer filling provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of the formation of a target dielectric layer based on ILD-CMP polishing provided in an embodiment of the present application;
FIG. 3 is a flow chart of a method for optimizing the planarity of a dielectric layer according to an embodiment of the present application;
FIG. 4 is a schematic filling view of a dielectric layer and a first polishing layer according to an embodiment of the present disclosure;
FIG. 5 is a schematic illustration of the generation of a first abrasive surface and the depth of the depression provided by an embodiment of the present application;
FIG. 6 is a schematic diagram of the generation of a second curved grinding surface and protrusions provided in the examples of the present application;
FIG. 7 is a schematic illustration of the generation of a second abrasive surface provided by an embodiment of the present application;
fig. 8 is a block diagram of a device for optimizing the flatness of a dielectric layer according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
In the related art, in the process flow of FDSOI, the ILD-CMP process employs a planarization polish of a single material. After the film formation, CMP processing, i.e., chemical mechanical polishing processing using an oxide film polishing liquid is directly performed to planarize the surface. As shown in fig. 1, the dense area of the integrated circuit device 10 has logic circuits and components embedded on its surface to form device bumps; the surface of the empty area has no logic circuit and element and no device bump. In a semiconductor manufacturing process, it is necessary to form a film on the surface of an integrated circuit device to form the dielectric layer 101. With the continuous refinement of the line width of the semiconductor process, the thickness of the dielectric layer 101 is gradually reduced, and the requirement on the flatness of the dielectric layer 101 is correspondingly increased, that is, the global drop of the surface of the dielectric layer 101 needs to meet a certain level. The dielectric layer 101 in fig. 1 is an oxide film layer (ILD OX), and the thickness of the oxide film layer 101 formed in the film forming process is uniform, but the overall drop is large and reaches 600 to 800A because of the device protrusions existing in the dense region of the integrated circuit device 10. When polishing is performed by the ILD-CMP technique, planarization polishing is performed only by the oxide film polishing solution, and the common single-material planarization treatment has a planarization limit. As shown in fig. 2, the thickness of the oxide film 201 after polishing meets the process requirement, but the second polished surface 210 formed after polishing has a recessed depth of h2 (located in the open region), the depth reaches about 150-300A, and the global flatness does not meet the process requirement.
In the embodiment of the application, the limited grinding precision of the ILD-CMP technology is considered, when the integrated circuit device is subjected to film forming treatment, a polysilicon film layer is additionally added on the outer side of a dielectric layer to be used as a first grinding layer, the first grinding layer is subjected to polysilicon film planarization treatment, and when an oxide film layer is ground, chemical mechanical polishing is stopped; because the two film layers formed by film forming are not horizontal planes, the integrated circuit device after grinding comprises an oxide film layer and a polycrystalline silicon film layer; and at the moment, continuously determining the etching proportion and the etching depth according to the depression depth on the first grinding surface and the thickness of the target dielectric layer, etching the first grinding surface to obtain a second grinding curved surface, and finally performing oxide film planarization treatment to obtain the second grinding surface. The flatness of the finally formed second grinding surface meets the process requirement.
Fig. 3 is a flowchart of a method for optimizing the flatness of a dielectric layer according to an embodiment of the present application, which specifically includes the following steps:
in step 301, a film forming process is performed on the integrated circuit device to form a dielectric layer and a first polishing layer.
In the film forming process, an oxide film layer is uniformly formed on the surface of the integrated circuit device and filled, and the oxide film layer is used for finally forming a target dielectric layer. The thickness of the oxide film layer is determined according to the process flow and the thickness of the target dielectric layer, the thickness of the target dielectric layer is usually 600-800A, and the thickness of the filled oxide film layer is about 4000A. After the oxide film layer is filled, the first grinding layer is continuously filled outside the oxide film layer, the first grinding layer is used for grinding in the subsequent process, the first grinding layer in the scheme is a polycrystalline silicon thin film layer Poly, and the thickness of the polycrystalline silicon thin film layer is controlled to be 2000-2500A.
As shown in fig. 4, since the device bump exists on the surface of the integrated circuit device, and the thicknesses of the filled polysilicon thin film layer 501 and the filled oxide film layer 502 are uniform, a large global difference exists on the surfaces of the filled polysilicon thin film layer 501 and the filled oxide film layer 502. In fig. 4, the thickness of the polysilicon thin film layer 501 is h2, the thickness of the oxide film layer 502 is h3, and the global difference of the surface is h1 (the global difference exists in a dense area). Wherein, the global fall is the height of the device bump.
Because the first polishing layer has a large global fall, the flatness cannot meet the process requirements, and h1 in fig. 4 reaches 600-800A, the polysilicon thin film layer needs to be subjected to polysilicon thin film planarization (Poly CMP). In the process, chemical mechanical polishing is carried out through the grinding liquid, and the polycrystalline silicon thin film layers in the dense area and the open area are ground and removed.
When the polycrystalline silicon thin film layer is ground and contacted with the oxide film layer (at the moment, the highest point of the oxide film layer is contacted), the chemical mechanical polishing is immediately stopped, and the obtained ground surface is the first ground surface.
As shown in fig. 5, the process has the same problem as the prior art, the first polishing surface located in the open area relative to the dense area has a concave depth h4, h4 measured by experiment is about 150A, and the flatness of the first polishing surface 510 is less than the flatness threshold. For example, the flatness threshold requires a global drop of no more than 100A, and thus the process requirements cannot be met by chemical mechanical polishing alone.
It should be noted that, due to the global difference, the first polishing layer is located between the oxide film layer and the polysilicon film layer, as shown in fig. 5, the first polishing surface 510 is simultaneously in contact with the polysilicon film layer 501 and the oxide film layer 502.
In step 304, the etching ratio of the dielectric layer and the first polishing layer is determined based on the recess depth of the first polishing surface.
In the scheme, after the polycrystalline silicon thin film is subjected to planarization treatment, the first grinding surface is continuously etched, and the overall drop can be further reduced by the etching technology. It should be noted that, in the present scheme, the etching technique is not directly adopted to etch the dielectric layer or the first polishing layer, because the global difference caused by the protrusion of the device is large, the etching technique is not suitable for use. Therefore, it is necessary to additionally fill the first polishing layer, and perform a cmp process and then perform an etching process. In addition, the etching technology usually adopts an atom bombardment mode to etch the first grinding layer, wherein the etching is to bombard the whole surface, but the device bulges in a dense area are more, and the etching process cannot be controlled.
Before the first grinding surface is etched, the etching ratio of the dielectric layer to the first grinding layer is determined according to the recess depth of the first grinding surface. Since the final target dielectric layer is only an oxide film and the recess depth needs to be eliminated, the etching ratio needs to be determined. In the scheme, the thickness of the target dielectric layer is 600-800A, and the etching ratio is 0.9:1, namely, the polycrystalline silicon, the oxide film layer and the oxide film layer are etched according to the thickness of 0.9: 1.
And 305, etching the oxide film layer and the polycrystalline silicon film layer in the first grinding surface based on the etching proportion to obtain a second grinding surface.
After the etching proportion is determined, the first grinding surface can be etched according to the etching proportion by adopting an etching technology, specifically, a physical etching technology or a chemical etching technology can be adopted, and the embodiment does not limit the etching proportion. It should be noted that, under the ultra-high process requirement, the etching process is not completed in one step, an etched curved surface is formed in the etching process, and after the etching is completed, the chemical mechanical polishing process needs to be continued on the etched curved surface, and the process specifically includes the following steps:
determining the etching depth based on the etching proportion and the thickness of the target dielectric layer, wherein the etching depth is larger than the maximum thickness of the planarized polysilicon film, and the thickness of the target dielectric layer is determined according to the semiconductor manufacturing process.
After the etching proportion of the polycrystalline silicon thin film layer and the oxide film layer is determined, the etching depth is further determined according to the thickness of the target dielectric layer, and the polycrystalline silicon thin film layer can be removed according to the etching depth. I.e., the etch depth is greater than the maximum thickness of the polysilicon film after the planarization process.
In this embodiment, the global drop corresponding to the oxide film is 800A, the thickness of the target dielectric layer is 800A, the etching depth should be at least greater than 800A, and the etching depth should be increased as much as possible to ensure the workload of the subsequent chemical mechanical polishing process and avoid re-forming the dishing depth as much as possible, and the etching depth is set to 1000A.
And etching the oxide film layer and the polycrystalline silicon film layer in the first grinding surface based on the etching proportion and the etching depth to obtain a second grinding curved surface.
Although the etching process is carried out according to the etching proportion, the etching process is continued to etch 1000A (the etching depth of the oxide film layer is 1000A) downwards on the basis of the original first grinding surface, the atom bombardment mode is adopted for carrying out, the grinding surface with higher flatness can not be obtained after the etching is finished, and in the actual etching process, a plurality of bulges, namely the second grinding curved surface can be formed in a dense area and a hollow area after the etching is finished.
As shown in fig. 6, the second curved polished surface 610 formed after the etching is completed is completely composed of the oxide film layer 601, a plurality of protrusions 602 exist in the second curved polished surface 610, and the height of the protrusion 602 is h2, which is generally a global step of 100A. The flatness of the second abrasive curved surface 610 is less than the flatness threshold.
And thirdly, carrying out oxide film planarization treatment on the second grinding curved surface to obtain a second grinding surface.
On the basis of the second grinding curved surface, oxide film planarization (ILD-CMP) treatment is continuously carried out on the oxide film layer, the same grinding liquid is used for carrying out chemical mechanical polishing in the treatment process, the step is different from the prior art in that the step is carried out to eliminate the global fall caused by the bulge on the second grinding curved surface, the oxide film layer is continuously ground to the thickness of the target dielectric layer, compared with the mode of directly grinding the first grinding surface in the prior art, the grinding thickness is greatly reduced, the global fall of the second grinding curved surface is relatively low, and the finally obtained second grinding surface cannot form large depression depth. As shown in FIG. 7, the second polishing surface 710 is completely covered by the oxide layer 701, i.e., the target dielectric layer is formed, and the global step of the second polishing surface 710 is usually about 50A, which is much smaller than the global steps of 150-300A in the prior art, so the flatness is greater than the flatness threshold (e.g., the global step corresponding to the flatness threshold is 80A).
In summary, in the implementation of the present application, when a film formation process is performed on an integrated circuit device, a polysilicon thin film layer is additionally added on the outer side of a dielectric layer to serve as a first polishing layer, a polysilicon thin film planarization process is performed on the first polishing layer, and when an oxide film layer is polished, chemical mechanical polishing is stopped; because the two film layers formed by film forming are not horizontal planes, the integrated circuit device after grinding comprises an oxide film layer and a polycrystalline silicon film layer; and at the moment, continuously determining the etching proportion and the etching depth according to the depression depth on the first grinding surface and the thickness of the target dielectric layer, etching the first grinding surface to obtain a second grinding curved surface, and finally performing oxide film planarization treatment to obtain the second grinding surface. The overall fall is reduced to the minimum, so that the process requirements are met, and the subsequent process window is greatly increased.
Fig. 8 is a block diagram of a device for optimizing the flatness of a dielectric layer according to an embodiment of the present disclosure. The device is used for the integrated circuit device, the surface of integrated circuit device is divided into dense district and open area, dense district has the device arch, open area does not have the device arch, the device includes:
the film forming module 801 is configured to perform film forming processing on an integrated circuit device to generate a dielectric layer and a first polishing layer, where the dielectric layer is located on the surface of the integrated circuit device, the first polishing layer covers the dielectric layer, and the dielectric layer and the first polishing layer corresponding to the dense region and the open region after the film forming processing have different flatness;
a planarization module 802, configured to perform planarization on the first polishing layer to obtain a first polishing surface, where the planarization includes performing Chemical Mechanical Polishing (CMP) on the first polishing layer, and the processed first polishing surface is located between the dielectric layer and the first polishing layer;
an etching module 803, configured to etch the first polished surface based on an etching ratio between the dielectric layer and the first polished layer to obtain a second polished surface, where the second polished surface is located on the dielectric layer, and the flatness of the polished surface is greater than a flatness threshold.
In an embodiment of the present application, there is also provided a computer device, including a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the method for dielectric layer flatness optimization provided by the various method embodiments described above.
The above description is of the preferred embodiment of the invention; it is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; any person skilled in the art can make many possible variations and modifications, or modify equivalent embodiments, without departing from the technical solution of the invention, without affecting the essence of the invention; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (9)
1. A method for optimizing flatness of a dielectric layer, the method being used for an integrated circuit device, a surface of the integrated circuit device being divided into a dense region and an open region, the dense region having device bumps and the open region having no device bumps, the method comprising:
forming a film on an integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is positioned on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer corresponding to the dense area and the open area after the film forming treatment have different flatness;
carrying out planarization treatment on the first grinding layer to obtain a first grinding surface, wherein the planarization treatment process comprises carrying out Chemical Mechanical Polishing (CMP) treatment on the first grinding layer, and the treated first grinding surface is positioned between the dielectric layer and the first grinding layer;
and etching the first grinding surface based on the etching proportion of the dielectric layer and the first grinding layer to obtain a second grinding surface, wherein the second grinding surface is positioned on the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold value.
2. The method of claim 1, wherein the dielectric layer is filled with an oxide film layer, and is formed of an oxide, wherein the oxide film layer has a thickness of 4000A; the first grinding layer is a polycrystalline silicon thin film layer, and the thickness of the polycrystalline silicon thin film layer is 2000-2500A.
3. The method of claim 2, wherein planarizing the first polishing layer to obtain a first polishing surface comprises:
carrying out polysilicon film planarization treatment on the first grinding layer in the dense area and the open area after film formation;
stopping performing chemical mechanical polishing when the oxide film layer is in grinding contact to obtain the first grinding surface;
the flatness of the first grinding surface is smaller than the flatness threshold, and the hollow area has a recess depth of at least 150A relative to the polycrystalline silicon thin film layer of the dense area.
4. The method of claim 3, wherein etching the first abrasive surface based on the etching ratio of the dielectric layer to the first abrasive layer to obtain a second abrasive surface comprises:
determining an etching ratio of the dielectric layer and the first polishing layer based on the recess depth of the first polishing surface;
and etching the oxide film layer and the polycrystalline silicon film layer in the first grinding surface based on the etching proportion to obtain the second grinding surface.
5. The method according to claim 4, wherein the etching the oxide film layer and the polysilicon thin film layer in the first grinding surface based on the etching ratio to obtain the second grinding surface comprises:
determining an etching depth based on the etching proportion and the thickness of a target dielectric layer, wherein the etching depth is greater than the maximum thickness of the polycrystalline silicon thin film after planarization treatment, and the thickness of the target dielectric layer is determined according to a semiconductor manufacturing process;
etching the oxide film layer and the polycrystalline silicon film layer in the first grinding surface based on the etching proportion and the etching depth to obtain a second grinding curved surface; the flatness of the second grinding curved surface is smaller than the flatness threshold, and the second grinding curved surface has a global fall of at least 100A;
and carrying out oxide film planarization treatment on the second grinding curved surface to obtain the second grinding surface.
6. The method according to any one of claims 1 to 5, wherein after the integrated circuit device is subjected to the film formation treatment, the polysilicon thin film layer and the oxide film layer have a height difference of at least 600 to 800A.
7. The method according to any one of claims 1 to 5, wherein the thickness of the target dielectric layer is 600-800A, the etching ratio of the polysilicon thin film layer to the oxide film layer is 0.9:1, and the etching depth is 1000A.
8. An apparatus for optimizing the flatness of a dielectric layer, the apparatus being used in an integrated circuit device, the surface of the integrated circuit device being divided into a dense region and an open region, the dense region having device bumps and the open region having no device bumps, the apparatus comprising:
the film forming module is used for performing film forming treatment on an integrated circuit device to generate a dielectric layer and a first grinding layer, wherein the dielectric layer is positioned on the surface of the integrated circuit device, the first grinding layer covers the dielectric layer, and the dielectric layer and the first grinding layer, corresponding to the dense area and the open area, after the film forming treatment have different flatness;
the planarization processing module is used for carrying out planarization processing on the first grinding layer to obtain a first grinding surface, wherein the planarization processing process comprises the step of carrying out Chemical Mechanical Polishing (CMP) processing on the first grinding layer, and the processed first grinding surface is positioned between the dielectric layer and the first grinding layer;
and the etching module is used for etching the first grinding surface based on the etching proportion of the dielectric layer and the first grinding layer to obtain a second grinding surface, wherein the second grinding surface is positioned on the dielectric layer, and the flatness of the grinding surface is greater than a flatness threshold value.
9. A computer device, wherein the computer device comprises a processor and a memory; the memory stores at least one instruction for execution by the processor to implement the method for dielectric layer planarity optimization as claimed in any of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210031918.7A CN114388428A (en) | 2022-01-12 | 2022-01-12 | Method and device for optimizing flatness of dielectric layer |
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