CN114388164B - Stacking machine interlocking system, stacking machine interlocking method, electronic equipment and storage medium - Google Patents
Stacking machine interlocking system, stacking machine interlocking method, electronic equipment and storage medium Download PDFInfo
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- CN114388164B CN114388164B CN202111619233.6A CN202111619233A CN114388164B CN 114388164 B CN114388164 B CN 114388164B CN 202111619233 A CN202111619233 A CN 202111619233A CN 114388164 B CN114388164 B CN 114388164B
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- G—PHYSICS
- G21—NUCLEAR PHYSICS; NUCLEAR ENGINEERING
- G21D—NUCLEAR POWER PLANT
- G21D3/00—Control of nuclear power plant
- G21D3/001—Computer implemented control
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- G—PHYSICS
- G21—NUCLEAR PHYSICS; NUCLEAR ENGINEERING
- G21D—NUCLEAR POWER PLANT
- G21D3/00—Control of nuclear power plant
- G21D3/04—Safety arrangements
- G21D3/06—Safety arrangements responsive to faults within the plant
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
Abstract
The invention discloses a stacker interlocking system, a stacker interlocking method, electronic equipment and a storage medium, wherein the stacker interlocking system comprises the following components: a first interlocking signal module for generating a first interlocking signal according to the first interlocking input signal and the first shutdown signal; a second interlock signal module for generating a second interlock signal according to the second interlock input signal and the second shutdown signal; generating an error jump prevention module for preventing an error jump signal according to the first interlocking input signal and the second interlocking input signal; generating a bounce prevention module for preventing a bounce signal according to the first shutdown signal and the second shutdown signal; a trip confirmation module for generating a trip confirmation signal according to the first interlock signal, the second interlock signal and the error trip prevention signal; and a trip signal generating module for generating a trip signal according to the trip confirm signal and the anti-trip signal. By arranging the modules, the invention can selectively connect the jump turbine unit when the reactor is shut down, and improves the safety, stability and economy of unit operation.
Description
Technical Field
The invention relates to the technical field of nuclear power operation, in particular to the technical field of interlocking control of a reactor and a steam turbine generator unit.
Background
The modular high-temperature gas-cooled reactor nuclear power station adopts the design that two reactors are provided with a steam turbine generator unit. The reactor emergency shutdown signal is sent to an emergency shutdown protection (Emergency trip system, ETS) cabinet to execute corresponding shutdown operation while being interlocked and jumped to a main water supply pump through an electric 6kV switch cabinet. The original reactor-to-machine interlock of the high temperature gas cooled reactor demonstration project only sets logic of the double-reactor emergency shutdown post-trip steam turbine in ETS, and the emergency shutdown condition in the single-reactor power operation process at the initial stage of unit starting is not considered. The emergency shutdown in the single-stack power operation process can cause the turbine to lose the acting steam source. Under this condition, the turbine will continue to operate in a pressure controlled manner without receiving a trip signal. Because the interlocking of the single-stack combined jump steam turbine generator unit is not provided, the steam turbine can only be jumped through the reverse power protection action and then through the generator protection signal. The reverse power protection needs to be delayed for 60 seconds, and in the process of delaying for 60 seconds, the generator is used as a motor to drag the steam turbine to continue rotating, at the moment, the steam turbine loses a through-flow steam source, and the temperature of the final stage blade is high due to the blasting effect, so that the service life of the steam turbine is influenced.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect that the tripping of the steam turbine cannot be timely and accurately performed in the prior art, so as to provide a stacker interlocking system, a stacker interlocking method, electronic equipment and a storage medium.
According to a first aspect, the present invention provides a stacker interlock system comprising: the trip signal generation device comprises a first interlocking signal module, a second interlocking signal module, an anti-false tripping module, a trip confirmation module and a trip signal generation module; the first interlocking signal module receives a first interlocking input signal input from the outside and a first shutdown signal input from the outside, and generates a first interlocking signal; the second interlocking signal module receives a second interlocking input signal input from the outside and a second shutdown signal input from the outside, and generates a second interlocking signal; the anti-false jump module receives a first interlocking input signal input from the outside and a second interlocking input signal input from the outside, and generates an anti-false jump signal; the anti-skip module receives a first shutdown signal input from the outside and a second shutdown signal input from the outside, and generates an anti-skip signal; the tripping confirmation module receives the first interlocking signal generated by the first interlocking signal module, the second interlocking signal generated by the second interlocking signal module and the error jump prevention signal generated by the error jump prevention module, and generates a tripping confirmation signal; the tripping signal generating module receives the tripping confirmation signal generated by the tripping confirmation module and the anti-tripping signal generated by the anti-tripping module to generate a tripping signal.
Optionally, the first interlock signal module includes: a first non-logic cell and a first or logic cell; the input end of the first non-logic unit receives a first interlocking input signal input from the outside, and the first non-logic unit outputs a first interlocking input signal which is inverted to the first or logic unit; the first input end of the first or logic unit receives the inverted first interlocking input signal generated by the first non-logic unit, the second input end of the first or logic unit receives the externally input first shutdown signal, and the first or logic unit outputs a first trip signal to the trip confirmation module.
Optionally, the second interlock signal module includes: a second non-logic cell and a second or logic cell; the input end of the second non-logic unit receives a second interlocking input signal input from the outside, and the second non-logic unit outputs a second interlocking input signal which is inverted to the second or logic unit; the first input end of the second or logic unit receives the inverted second interlock input signal generated by the second non-logic unit, the second input end of the second or logic unit receives a second shutdown signal input from the outside, and the second or logic unit outputs a second interlock signal to the tripping confirmation module.
Optionally, the anti-mis-jump module includes: a third or logic unit; the first input end of the third or logic unit receives a first interlocking input signal input from the outside, the second input end of the third or logic unit receives a second interlocking input signal input from the outside, and the third or logic unit outputs an error jump prevention signal to the tripping confirmation module.
Optionally, the anti-skip module includes: a first AND logic unit; the first input end of the first AND logic unit receives a first shutdown signal input from the outside, the second input end of the first AND logic unit receives a second shutdown signal input from the outside, and the first AND logic unit outputs a trip-preventing signal to the trip signal generating module.
Optionally, the trip confirmation module includes: a second AND logic unit; the first input end of the second AND logic unit receives the first interlocking signal generated by the first interlocking signal module, the second input end of the second AND logic unit receives the second interlocking signal generated by the second interlocking signal module, the third input end of the second AND logic unit receives the false jump preventing signal generated by the false jump preventing module, and the second AND logic unit outputs a trip confirmation signal to the trip signal generating module.
Optionally, the trip signal generation module includes: a fourth or logic unit; the first input end of the fourth or logic unit receives the tripping confirmation signal generated by the tripping confirmation module, the second input end of the fourth or logic unit receives the tripping prevention signal generated by the tripping prevention module, and the output end of the fourth or logic unit outputs the tripping signal.
According to a second aspect, the present invention provides a stacker interlock method, comprising: acquiring a first interlocking input signal, a second interlocking input signal, a first shutdown signal and a second shutdown signal; generating a first interlocking signal according to the first interlocking input signal and the first shutdown signal; generating a second interlock signal according to the second shutdown signal of the second interlock input signal; generating an error jump prevention signal according to the first interlocking input signal and the second interlocking input signal; generating a bounce prevention signal according to the first shutdown signal and the second shutdown signal; generating a trip confirmation signal according to the first interlocking signal, the second interlocking signal and the false trip prevention signal; and generating a tripping signal according to the tripping confirmation signal and the anti-tripping signal.
According to a third aspect, the present invention provides an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the heap machine interlock method as described in the second aspect.
According to a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the heap machine interlocking method as described in the second aspect.
The technical scheme of the invention has the following advantages:
according to the stacking machine interlocking system, the first interlocking signal module, the second interlocking signal module, the false tripping prevention module, the anti-tripping prevention module, the tripping confirmation module and the tripping signal generation module are arranged, so that when a reactor is stopped under various working conditions, the turbo generator set can be selectively and jointly tripped according to the requirements of the working conditions of the turbo generator set at the time, the false tripping and the false tripping of the turbo generator set are avoided, and the running safety, stability and economy of the high-temperature gas cooled stack nuclear power unit are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a specific example of a stacker interlock system in accordance with an embodiment of the present invention;
FIG. 2 is a circuit diagram of another embodiment of a stacker interlock system in accordance with an embodiment of the present invention;
FIG. 3 is a flowchart of an embodiment of a stacker interlock method according to an embodiment of the present invention;
fig. 4 is a diagram illustrating an embodiment of an electronic device according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The invention discloses a stacker interlocking system, as shown in figure 1, comprising: the trip signal generation device comprises a first interlocking signal module 1, a second interlocking signal module 2, an anti-misjump module 3, an anti-misjump module 4, a trip confirmation module 5 and a trip signal generation module 6.
The first interlock signal module 1 receives an externally input first interlock input signal and an externally input first shutdown signal, and generates a first interlock signal.
Specifically, as shown in fig. 1 and 2, the first interlock signal module 1 includes: a first non-logic cell 11 and a first or logic cell 12; the input end of the first non-logic unit 11 receives a first interlocking input signal input from the outside, and the first non-logic unit 11 outputs the inverted first interlocking input signal to the first or logic unit 12; the first input terminal of the first or logic unit 12 receives the inverted first interlock input signal generated by the first non-logic unit 11, the second input terminal of the first or logic unit 12 receives the externally input first shutdown signal, and the first or logic unit 12 outputs the first trip signal to the trip confirmation module 5.
When the stacking machine No. 1 is in interlocking, the first interlocking input signal is a high-level signal, and when the stacking machine No. 1 is not in interlocking, the first interlocking input signal is a low-level signal; when the No. 1 stacker is in normal operation, the first stacking stop signal is a low level signal, and when the No. 1 stacker is out of operation, the first stacking stop signal is a high level signal. For example, to ensure that the acquired first shutdown signal is accurate, the first shutdown signal may be acquired through a two-out-of-three redundancy structure.
Further, by setting the non-logic unit and the or logic unit in the first interlocking signal module, the high-level first jump signal is output under three conditions, namely: the first case is that the first interlock input signal is at a high level and the first shutdown signal is at a high level; the second condition is that the first interlocking input signal is low level, and the first shutdown signal is high level; the third case is that the first interlock input signal is low and the first shutdown signal is low.
Specifically, in the first case, the first interlock input signal is at a high level, that is, the No. 1 stacker and the turbine unit are interlocked, and the high level of the first shutdown signal indicates that the No. 1 stacker is stopped at this time, when the stacker is stopped, the turbine unit does not need to operate, and according to the first interlock input signal, a trip signal needs to be sent to the turbine unit at this time, so that a first jump signal at a high level is output.
Specifically, under the second and third conditions, the first interlock input signal is at a low level, i.e. the No. 1 stacker is not interlocked with the turbine unit, no matter how the No. 1 stacker works, the No. 1 stacker is irrelevant to the turbine unit, and the turbine unit does not need to work, so that the first jump signal at a high level is output.
Further, by setting the non-logic unit and the or logic unit in the first interlock signal module, only one case will output the first interlock signal with low level, namely: the first interlock input signal is high and the first shutdown signal is low.
Specifically, the first interlock input signal is at a high level, that is, the No. 1 stacker and the steam turbine unit are interlocked, the first shutdown signal is at a low level, which means that the No. 1 stacker is working at the moment, and because the No. 1 stacker and the steam turbine unit are interlocked, the steam turbine unit needs to continue working at the moment and is forbidden to trip, so that the first trip signal of the low level is output.
The second interlock signal module receives the second interlock input signal input from the outside and the second shutdown signal input from the outside, and generates a second interlock signal.
Specifically, the second interlock signal module includes: a second non-logic cell and a second or logic cell; the input end of the second non-logic unit receives a second interlocking input signal input from the outside, and the second non-logic unit outputs a second interlocking input signal which is inverted to the second or logic unit; the first input end of the second or logic unit receives the inverted second interlock input signal generated by the second non-logic unit, the second input end of the second or logic unit receives the second shutdown signal input from the outside, and the second or logic unit outputs the second interlock signal to the trip confirmation module.
When the No. 2 stacker is in interlocking, the second interlocking input signal is a high-level signal, and when the No. 2 stacker is not in interlocking, the second interlocking input signal is a low-level signal; when the No. 2 reactor is in normal operation, the second shutdown signal is a low level signal, and when the No. 2 reactor is out of operation, the second shutdown signal is a high level signal. For example, to ensure that the acquired second shutdown signal is accurate, the second shutdown signal may be acquired through a two-out-of-three redundancy structure.
Further, by setting the non-logic unit and the or logic unit in the second interlock signal module, the second interlock signal with high level is output in three cases, namely: the first case is that the second interlock input signal is high level, and the second shutdown signal is high level; the second condition is that the second interlock input signal is low level, and the second shutdown signal is high level; the third case is that the second interlock input signal is low and the second shutdown signal is low.
Specifically, in the first case, the second interlock input signal is at a high level, that is, the No. 2 stacker and the turbine unit are interlocked, and the second shutdown signal is at a high level, which indicates that the No. 2 stacker is stopped at this time, when the stacker is stopped, the turbine unit does not need to operate, and according to the second interlock input signal, a trip signal needs to be sent to the turbine unit at this time, so that the second interlock signal at a high level is output.
Specifically, under the second and third conditions, the second interlock input signal is at a low level, that is, the No. 2 stacker is not interlocked with the turbine unit, no matter how the No. 2 stacker works, the No. 2 stacker is irrelevant to the turbine unit, and the turbine unit does not need to work, so that the second interlock signal at a high level is output.
Further, by setting the non-logic unit and the or logic unit in the second interlock signal module, only one case will output the second interlock signal with low level, namely: the second interlock input signal is high and the second shutdown signal is low.
Specifically, the second interlock input signal is at a high level, that is, the No. 2 stacker and the steam turbine unit are interlocked, the second shutdown signal is at a low level, which means that the No. 2 stacker is working at the moment, and because the No. 2 stacker and the steam turbine unit are interlocked, the steam turbine unit needs to continue working at the moment and is forbidden to trip, so that the second interlock signal at the low level is output.
The anti-mistaking module receives a first interlocking input signal input from the outside and a second interlocking input signal input from the outside, and generates an anti-mistaking signal.
Specifically, the anti-mistaking module includes: a third or logic unit; the first input end of the third or logic unit receives the first interlocking input signal input from the outside, the second input end of the third or logic unit receives the second interlocking input signal input from the outside, and the third or logic unit outputs an error jump prevention signal to the tripping confirmation module.
Further, the anti-misjump module can ensure that a tripping signal can be output only when at least one stacker is in interlocking connection, so that the situation that the tripping signal is continuously output when any stacker is not in interlocking connection is avoided.
The anti-skip module receives the first shutdown signal input from the outside and the second shutdown signal input from the outside, and generates an anti-skip signal.
Specifically, the anti-skip module includes: a first AND logic unit; the first input end of the first AND logic unit receives a first shutdown signal input from the outside, the second input end of the first AND logic unit receives a second shutdown signal input from the outside, and the first AND logic unit outputs a trip-proof signal to the trip signal generating module.
Further, the anti-trip module can ensure that when the No. 1 stacker and the No. 2 stacker both send out shutdown signals, trip signals can be sent out, and the condition that the steam turbine continues to work when all the stackers are shut down is avoided.
The tripping confirmation module receives the first interlocking signal generated by the first interlocking signal module, the second interlocking signal generated by the second interlocking signal module and the error jump prevention signal generated by the error jump prevention module, and generates a tripping confirmation signal.
Specifically, the trip confirmation module includes: a second AND logic unit; the first input end of the second AND logic unit receives the first interlocking signal generated by the first interlocking signal module, the second input end of the second AND logic unit receives the second interlocking signal generated by the second interlocking signal module, the third input end of the second AND logic unit receives the error jump prevention signal generated by the error jump prevention module, and the second AND logic unit outputs a trip confirmation signal to the trip signal generation module.
Further, the trip confirmation module ensures that a high level trip confirmation signal is output if and only if the first interlock signal is high, the second interlock signal is high, and the anti-false-skip module is high. Namely, when the No. 1 stacker does not need the operation of the turbine unit and at least one stacker is in interlocking connection, a tripping confirmation signal of high level is output.
The tripping signal generating module receives the tripping confirmation signal generated by the tripping confirmation module and the anti-tripping signal generated by the anti-tripping module to generate a tripping signal.
Specifically, the trip signal generation module includes: a fourth or logic unit; the first input end of the fourth or logic unit receives the tripping confirmation signal generated by the tripping confirmation module, the second input end of the fourth or logic unit receives the anti-tripping signal generated by the anti-tripping module, and the output end of the fourth or logic unit outputs the tripping signal.
Further, the trip signal generation module ensures that the trip signal can be output to the steam turbine unit when the high-level trip confirmation signal or the high-level anti-trip signal is acquired.
According to the stacking machine interlocking system, the first interlocking signal module, the second interlocking signal module, the false tripping prevention module, the anti-tripping prevention module, the tripping confirmation module and the tripping signal generation module are arranged, so that when a reactor is stopped under various working conditions, the turbo generator set can be selectively and jointly tripped according to the requirements of the working conditions of the turbo generator set at the time, the false tripping and the false tripping of the turbo generator set are avoided, and the running safety, stability and economy of the high-temperature gas cooled stack nuclear power unit are improved.
In an embodiment, when the stacking machine 1 is in interlocking input and the stacking machine 2 is in shutdown, the first interlocking input signal is high, the second interlocking input signal is low, the first shutdown signal is low, and the second shutdown signal is high.
The first interlocking signal module inputs a high-level first interlocking input signal and a low-level first shutdown signal, the high-level first interlocking input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the low-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the low-level first interlocking signal. The second interlock signal module inputs a low-level second interlock input signal and a high-level second shutdown signal, the low-level second interlock input signal is inverted through the second non-logic unit to obtain a high-level signal, the high-level signal is input into the second OR logic unit, and OR logic operation is carried out on the high-level second shutdown signal and the high-level signal output by the second non-logic unit through the second OR logic unit to output a high-level second interlock signal. The anti-false jump module inputs a high-level first interlocking input signal and a low-level second interlocking input signal, performs OR logic operation on the high-level first interlocking input signal and the low-level second interlocking input signal through a third OR logic unit, and outputs a high-level anti-false jump signal. The anti-bounce module inputs a low-level first shutdown signal and a high-level second shutdown signal, performs AND logic operation on the low-level first shutdown signal and the high-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-bounce signal. The tripping confirmation module inputs the first interlocking signal with low level, the second interlocking signal with high level and the error jump prevention signal with high level, performs AND logic operation on the first interlocking signal with low level, the second interlocking signal with high level and the error jump prevention signal with high level through the second AND logic unit, and outputs the tripping confirmation signal with low level. The tripping signal generating module inputs the tripping confirmation signal with low level and the anti-tripping signal with low level, and performs OR logic operation on the tripping confirmation signal with low level and the anti-tripping signal with low level through the fourth OR logic unit to output the tripping signal with low level, and at the moment, the steam turbine unit operates normally.
When the reactor is shut down at any time 1, the first shutdown signal is changed from a low level to a high level, the first interlocking input signal is kept at a high level, the second interlocking input signal is kept at a low level, and the second shutdown signal is kept at a high level.
The first interlock signal module inputs a high-level first interlock input signal and a high-level first shutdown signal, the high-level first interlock input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the high-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the high-level first interlock signal. The second interlock signal module inputs a low-level second interlock input signal and a high-level second shutdown signal, and keeps outputting the high-level second interlock signal. The anti-false jump module inputs the first interlocking input signal with high level and the second interlocking input signal with low level, and keeps outputting the anti-false jump signal with high level. The anti-trip module inputs a high-level first shutdown signal and a high-level second shutdown signal, performs AND logic operation on the high-level first shutdown signal and the high-level second shutdown signal through the first AND logic unit, and outputs a high-level anti-trip signal. The tripping confirmation module inputs the high-level first interlocking signal, the high-level second interlocking signal and the high-level false tripping prevention signal, performs AND logic operation on the high-level first interlocking signal, the high-level second interlocking signal and the high-level false tripping prevention signal through the second AND logic unit, and outputs the high-level tripping confirmation signal. The trip signal generation module inputs a high-level trip confirmation signal and a high-level anti-trip signal, performs OR logic operation on the high-level trip confirmation signal and the high-level anti-trip signal through a fourth OR logic unit, and outputs the high-level trip signal, at the moment, the turbine unit trips, and stops running, namely, when a single stack works and the number 1 stack which is put in an interlocking way is shut down, the turbine unit is jumped.
In an embodiment, when the stacking machine 1 is in interlocking, the stacking machine 2 is not in interlocking but works normally, the first interlocking input signal is high, the second interlocking input signal is low, the first shutdown signal is low, and the second shutdown signal is low.
The first interlocking signal module inputs a high-level first interlocking input signal and a low-level first shutdown signal, the high-level first interlocking input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the low-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the low-level first interlocking signal. The second interlock signal module inputs a low-level second interlock input signal and a low-level second shutdown signal, the low-level second interlock input signal is inverted through the second non-logic unit to obtain a high-level signal, the high-level signal is input into the second OR logic unit, and OR logic operation is carried out on the low-level second shutdown signal and the high-level signal output by the second non-logic unit through the second OR logic unit to output a high-level second interlock signal. The anti-false jump module inputs a high-level first interlocking input signal and a low-level second interlocking input signal, performs OR logic operation on the low-level first interlocking input signal and the low-level second interlocking input signal through a third OR logic unit, and outputs a high-level anti-false jump signal. The anti-bounce module inputs a low-level first shutdown signal and a low-level second shutdown signal, performs AND logic operation on the low-level first shutdown signal and the low-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-bounce signal. The tripping confirmation module inputs the first interlocking signal with low level, the second interlocking signal with high level and the error jump prevention signal with high level, performs AND logic operation on the first interlocking signal with low level, the second interlocking signal with high level and the error jump prevention signal with high level through the second AND logic unit, and outputs the tripping confirmation signal with low level. The tripping signal generating module inputs the tripping confirmation signal with low level and the anti-tripping signal with low level, and performs OR logic operation on the tripping confirmation signal with low level and the anti-tripping signal with low level through the fourth OR logic unit to output the tripping signal with low level, and at the moment, the steam turbine unit operates normally.
When the reactor is shut down at any time No. 1, the first shutdown signal is changed from a low level to a high level, the second interlock input signal is kept at a low level, the first interlock input signal is kept at a high level, and the second shutdown signal is kept at a low level.
The first interlock signal module inputs a high-level first interlock input signal and a high-level first shutdown signal, the high-level first interlock input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the high-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the high-level first interlock signal. The second interlock signal module inputs the low-level second interlock input signal and the low-level second shutdown signal, and keeps outputting the high-level second interlock signal. The anti-false jump module inputs the first interlocking input signal with high level and the second interlocking input signal with low level, and keeps outputting the anti-false jump signal with high level. The anti-trip module inputs a high-level first shutdown signal and a low-level second shutdown signal, performs AND logic operation on the high-level first shutdown signal and the low-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-trip signal. The tripping confirmation module inputs the high-level first interlocking signal, the high-level second interlocking signal and the high-level false tripping prevention signal, performs AND logic operation on the high-level first interlocking signal, the high-level second interlocking signal and the high-level false tripping prevention signal through the second AND logic unit, and outputs the high-level tripping confirmation signal. The trip signal generation module inputs a high-level trip confirmation signal and a low-level anti-trip signal, performs OR logic operation on the high-level trip confirmation signal and the low-level anti-trip signal through a fourth OR logic unit, and outputs the high-level trip signal, at the moment, the turbine unit trips and stops running, namely, when the interlocking input No. 1 reactor is shut down, the turbine unit is jumped.
Similarly, when the No. 2 reactor trip occurs at any one time, the second trip signal transitions from a low level to a high level, the first interlock input signal remains high, the second interlock input signal remains low, and the first trip signal remains low.
The first interlock signal module inputs a high-level first interlock input signal and a low-level first shutdown signal, and keeps outputting the low-level first interlock signal. The second interlock signal module inputs a low-level second interlock input signal and a high-level second shutdown signal, the low-level second interlock input signal is inverted through the second non-logic unit to obtain a high-level signal, the high-level signal is input into the second OR logic unit, and OR logic operation is carried out on the high-level second shutdown signal and the high-level signal output by the second non-logic unit through the second OR logic unit to output a high-level second interlock signal. The anti-false jump module inputs the first interlocking input signal with high level and the second interlocking input signal with low level, and keeps outputting the anti-false jump signal with high level. The anti-bounce module inputs a low-level first shutdown signal and a high-level second shutdown signal, performs AND logic operation on the low-level first shutdown signal and the high-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-bounce signal. The tripping confirmation module inputs the first interlocking signal with low level, the second interlocking signal with high level and the error-jump-preventing signal with high level, and keeps outputting the tripping confirmation signal with low level. The tripping signal generating module inputs a tripping confirmation signal with a low level and an anti-tripping signal with a low level, keeps outputting the tripping signal with the low level, and the steam turbine set normally operates at the moment, namely the No. 2 reactor shutdown which is not put into interlocking does not influence the operation of the steam turbine set.
In an embodiment, when the stacking machine 1 is in interlocking input and the stacking machine 2 is in interlocking input, the first interlocking input signal is high, the second interlocking input signal is high, the first shutdown signal is low, and the second shutdown signal is low.
The first interlocking signal module inputs a high-level first interlocking input signal and a low-level first shutdown signal, the high-level first interlocking input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the low-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the low-level first interlocking signal. The second interlock signal module inputs a high-level second interlock input signal and a low-level second shutdown signal, the high-level second interlock input signal is inverted through the second non-logic unit to obtain a low-level signal, the low-level signal is input into the second OR logic unit, and OR logic operation is carried out on the low-level second shutdown signal and the low-level signal output by the second non-logic unit through the second OR logic unit to output the low-level second interlock signal. The anti-false jump module inputs a high-level first interlocking input signal and a high-level second interlocking input signal, performs OR logic operation on the high-level first interlocking input signal and the high-level second interlocking input signal through a third OR logic unit, and outputs a high-level anti-false jump signal. The anti-bounce module inputs a low-level first shutdown signal and a low-level second shutdown signal, performs AND logic operation on the low-level first shutdown signal and the low-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-bounce signal. The tripping confirmation module inputs the first interlocking signal with low level, the second interlocking signal with low level and the anti-false tripping signal with high level, and performs AND logic operation on the first interlocking signal with low level, the second interlocking signal with low level and the anti-false tripping signal with high level through the second AND logic unit, and outputs the tripping confirmation signal with low level. The tripping signal generating module inputs the tripping confirmation signal with low level and the anti-tripping signal with low level, and performs OR logic operation on the tripping confirmation signal with low level and the anti-tripping signal with low level through the fourth OR logic unit to output the tripping signal with low level, and at the moment, the steam turbine unit operates normally.
When the reactor is shut down at any time 1, the first shutdown signal is changed from a low level to a high level, the first interlocking input signal is kept at a high level, the second interlocking input signal is kept at a high level, and the second shutdown signal is kept at a low level.
The first interlock signal module inputs a high-level first interlock input signal and a high-level first shutdown signal, the high-level first interlock input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the high-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the high-level first interlock signal. The second interlock signal module inputs a high-level second interlock input signal and a low-level second shutdown signal, and keeps outputting the low-level second interlock signal. The anti-false jump module inputs the first interlocking input signal with high level and the second interlocking input signal with high level, and keeps outputting the anti-false jump signal with high level. The anti-trip module inputs a high-level first shutdown signal and a low-level second shutdown signal, performs AND logic operation on the high-level first shutdown signal and the low-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-trip signal. The tripping confirmation module inputs the high-level first interlocking signal, the low-level second interlocking signal and the high-level false tripping prevention signal, performs AND logic operation on the high-level first interlocking signal, the low-level second interlocking signal and the high-level false tripping prevention signal through the second AND logic unit, and outputs the low-level tripping confirmation signal. The tripping signal generating module inputs a tripping confirmation signal with a low level and an anti-tripping signal with a low level, keeps outputting the tripping signal with the low level, and normally operates the turbine unit at the moment, namely the independent shutdown of the No. 1 stack can not be combined with the tripping of the turbine unit.
When the reactor is shut down at any time No. 2, the second shutdown signal is changed from a low level to a high level, the first interlocking input signal is kept at a high level, the second interlocking input signal is kept at a high level, and the first shutdown signal is kept at a low level.
The first interlock signal module inputs a high-level first interlock input signal and a low-level first shutdown signal, and keeps outputting the low-level first interlock signal. The second interlock signal module inputs a high-level second interlock input signal and a high-level second shutdown signal, the high-level second interlock input signal is inverted through the second non-logic unit to obtain a low-level signal, the low-level signal is input into the second OR logic unit, and OR logic operation is carried out on the high-level second shutdown signal and the low-level signal output by the second non-logic unit through the second OR logic unit to output a high-level second interlock signal. The anti-false jump module inputs the first interlocking input signal with high level and the second interlocking input signal with high level, and keeps outputting the anti-false jump signal with high level. The anti-bounce module inputs a low-level first shutdown signal and a high-level second shutdown signal, performs AND logic operation on the low-level first shutdown signal and the high-level second shutdown signal through the first AND logic unit, and outputs a low-level anti-bounce signal. The tripping confirmation module inputs the first interlocking signal with low level, the second interlocking signal with high level and the error jump prevention signal with high level, performs AND logic operation on the first interlocking signal with low level, the second interlocking signal with high level and the error jump prevention signal with high level through the second AND logic unit, and outputs the tripping confirmation signal with low level. The tripping signal generating module inputs a tripping confirmation signal with a low level and an anti-tripping signal with a low level, keeps outputting the tripping signal with the low level, and normally operates the turbine unit at the moment, namely the No. 2 reactor is shut down singly and cannot be connected with the tripping turbine unit.
When the No. 1 reactor and the No. 2 reactor are shut down at any moment, the first shutdown signal is changed from a low level to a high level, the second shutdown signal is changed from the low level to the high level, the first interlocking input signal is kept at the high level, and the second interlocking input signal is kept at the high level.
The first interlock signal module inputs a high-level first interlock input signal and a high-level first shutdown signal, the high-level first interlock input signal is inverted through the first non-logic unit to obtain a low-level signal, the low-level signal is input into the first OR logic unit, and OR logic operation is carried out on the high-level first shutdown signal and the low-level signal output by the first non-logic unit through the first OR logic unit to output the high-level first interlock signal. The second interlock signal module inputs a high-level second interlock input signal and a high-level second shutdown signal, the high-level second interlock input signal is inverted through the second non-logic unit to obtain a low-level signal, the low-level signal is input into the second OR logic unit, and OR logic operation is carried out on the high-level second shutdown signal and the low-level signal output by the second non-logic unit through the second OR logic unit to output a high-level second interlock signal. The anti-false jump module inputs the first interlocking input signal with high level and the second interlocking input signal with high level, and keeps outputting the anti-false jump signal with high level. The anti-trip module inputs a high-level first shutdown signal and a high-level second shutdown signal, performs AND logic operation on the high-level first shutdown signal and the high-level second shutdown signal through the first AND logic unit, and outputs a high-level anti-trip signal. The tripping confirmation module inputs the high-level first interlocking signal, the high-level second interlocking signal and the high-level false tripping prevention signal, performs AND logic operation on the high-level first interlocking signal, the high-level second interlocking signal and the high-level false tripping prevention signal through the second AND logic unit, and outputs the high-level tripping confirmation signal. The trip signal generation module inputs a high-level trip confirmation signal and a high-level anti-trip signal, performs OR logic operation on the high-level trip confirmation signal and the high-level anti-trip signal through a fourth OR logic unit, and outputs the high-level trip signal, at the moment, the turbine unit trips and stops running, namely, when the No. 1 stack and the No. 2 stack are shut down simultaneously, the turbine unit is jumped.
The invention also provides a stacker interlocking method, as shown in fig. 3, comprising the following steps:
step S1, a first interlocking input signal, a second interlocking input signal, a first shutdown signal and a second shutdown signal are obtained.
And S2, generating a first interlocking signal according to the first interlocking input signal and the first shutdown signal. For details, reference is made to the description of the first interlocking signal module 1 in the above system embodiment, and details are not repeated here.
And S3, generating a second interlocking signal according to a second shutdown signal of the second interlocking input signal. For details, reference is made to the description of the second interlock signal module 2 in the above system embodiment, and details are not repeated here.
And S4, generating an error jump prevention signal according to the first interlocking input signal and the second interlocking input signal. For details, refer to the related description of the anti-mis-jump module 3 in the above system embodiment, and will not be repeated here.
And S5, generating a skip preventing signal according to the first pile stop signal and the second pile stop signal. For details, reference is made to the related description of the anti-skip module 4 in the above system embodiment, which is not repeated here.
And S6, generating a tripping confirmation signal according to the first interlocking signal, the second interlocking signal and the error-tripping prevention signal. For details, reference is made to the description of the trip confirmation module 5 in the above system embodiment, and details are not repeated here.
Step S7, generating a tripping signal according to the tripping confirmation signal and the anti-tripping signal. For details, reference is made to the description of the trip signal generation module 6 in the above system embodiment, and details are not repeated here.
According to the stacking machine interlocking method provided by the invention, the first interlocking signal, the second interlocking signal, the false trip prevention signal, the trip confirmation signal and the trip signal generation signal are generated, so that when a reactor is stopped under various working conditions, the turbo generator set can be selectively connected and tripped according to the requirements of the working conditions of the turbo generator set at the time, the false trip and the false trip prevention of the turbo generator set are avoided, and the running safety, stability and economy of the high-temperature gas cooled reactor nuclear power unit are improved.
The embodiment of the present invention further provides an electronic device, as shown in fig. 4, where the electronic device may include a processor 201 and a memory 202, where the processor 201 and the memory 202 may be connected by a bus or other means, and in fig. 4, the connection is exemplified by a bus.
The processor 201 may be a central processing unit (Central Processing Unit, CPU). The processor 201 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), field programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above.
The memory 202 is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the heap machine interlocking method in the embodiments of the present invention. The processor 201 executes various functional applications of the processor and data processing by running non-transitory software programs, instructions, and modules stored in the memory 202, i.e., implementing the heap machine interlocking method in the method embodiment described above.
One or more modules are stored in memory 202 that, when executed by processor 201, perform the heap machine interlock method of the embodiment shown in fig. 3.
The details of the electronic device may be understood in correspondence with the corresponding related descriptions and effects in the embodiment shown in fig. 3, which are not described herein.
Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and alterations to these embodiments without departing from the spirit of the invention and the scope of protection as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while remaining within the scope of the present invention.
Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. From the present disclosure, it will be readily understood by those of ordinary skill in the art that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (8)
1. A stacker interlock system, comprising: the trip signal generation device comprises a first interlocking signal module, a second interlocking signal module, an anti-false tripping module, a trip confirmation module and a trip signal generation module;
the first interlocking signal module receives a first interlocking input signal input from the outside and a first shutdown signal input from the outside, generates a first interlocking signal, and comprises: the trip confirmation module comprises a first non-logic unit and a first or logic unit, wherein the input end of the first non-logic unit receives a first interlocking input signal input from the outside, the first non-logic unit outputs a reversed first interlocking input signal to the first or logic unit, the first input end of the first or logic unit receives a reversed first interlocking input signal generated by the first non-logic unit, the second input end of the first or logic unit receives a first shutdown signal input from the outside, and the first or logic unit outputs a first joint jump signal to the trip confirmation module;
the second interlock signal module receives a second interlock input signal input from the outside and a second shutdown signal input from the outside, and generates a second interlock signal, and the second interlock signal module includes: the input end of the second non-logic unit receives a second interlock input signal input from the outside, the second non-logic unit outputs a second interlock input signal which is inverted to the second or logic unit, the first input end of the second or logic unit receives the second interlock input signal which is inverted and generated by the second non-logic unit, the second input end of the second or logic unit receives a second shutdown signal which is input from the outside, and the second or logic unit outputs a second interlock signal to the trip confirmation module;
The anti-false jump module receives a first interlocking input signal input from the outside and a second interlocking input signal input from the outside, and generates an anti-false jump signal;
the anti-skip module receives a first shutdown signal input from the outside and a second shutdown signal input from the outside, and generates an anti-skip signal;
the tripping confirmation module receives the first interlocking signal generated by the first interlocking signal module, the second interlocking signal generated by the second interlocking signal module and the error jump prevention signal generated by the error jump prevention module, and generates a tripping confirmation signal;
the tripping signal generating module receives the tripping confirmation signal generated by the tripping confirmation module and the anti-tripping signal generated by the anti-tripping module to generate a tripping signal.
2. The system of claim 1, wherein the anti-mis-jump module comprises: a third or logic unit;
the first input end of the third or logic unit receives a first interlocking input signal input from the outside, the second input end of the third or logic unit receives a second interlocking input signal input from the outside, and the third or logic unit outputs an error jump prevention signal to the tripping confirmation module.
3. The system of claim 1, wherein the anti-skip module comprises: a first AND logic unit;
The first input end of the first AND logic unit receives a first shutdown signal input from the outside, the second input end of the first AND logic unit receives a second shutdown signal input from the outside, and the first AND logic unit outputs a trip-preventing signal to the trip signal generating module.
4. The system of claim 1, wherein the trip confirmation module comprises: a second AND logic unit;
the first input end of the second AND logic unit receives the first interlocking signal generated by the first interlocking signal module, the second input end of the second AND logic unit receives the second interlocking signal generated by the second interlocking signal module, the third input end of the second AND logic unit receives the false jump preventing signal generated by the false jump preventing module, and the second AND logic unit outputs a trip confirmation signal to the trip signal generating module.
5. The system of claim 1, wherein the trip signal generation module comprises: a fourth or logic unit;
the first input end of the fourth or logic unit receives the tripping confirmation signal generated by the tripping confirmation module, the second input end of the fourth or logic unit receives the tripping prevention signal generated by the tripping prevention module, and the output end of the fourth or logic unit outputs the tripping signal.
6. A stacker interlock method employing the stacker interlock system of any one of claims 1 to 5, comprising:
acquiring a first interlocking input signal, a second interlocking input signal, a first shutdown signal and a second shutdown signal;
generating a first interlocking signal according to the first interlocking input signal and the first shutdown signal;
generating a second interlock signal according to the second shutdown signal of the second interlock input signal;
generating an error jump prevention signal according to the first interlocking input signal and the second interlocking input signal;
generating a bounce prevention signal according to the first shutdown signal and the second shutdown signal;
generating a trip confirmation signal according to the first interlocking signal, the second interlocking signal and the false trip prevention signal;
and generating a tripping signal according to the tripping confirmation signal and the anti-tripping signal.
7. An electronic device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the steps of the heap machine interlock method of claim 6.
8. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the heap machine interlocking method as claimed in claim 6.
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| US3999390A (en) * | 1974-04-25 | 1976-12-28 | Westinghouse Electric Corporation | HTGR power plant turbine-generator load control system |
| US7130703B2 (en) * | 2003-04-08 | 2006-10-31 | Fisher-Rosemount Systems, Inc. | Voter logic block including operational and maintenance overrides in a process control system |
| CN102280148B (en) * | 2011-04-29 | 2014-01-22 | 清华大学 | Integration testing method and system for digital protection system of high temperature gas cooled reactor |
| CN103400621B (en) * | 2013-07-29 | 2016-02-24 | 国核电力规划设计研究院 | A kind of control method of start and stop shut-down system of HTGR Nuclear Power Plant and device |
| CN106875993B (en) * | 2017-01-04 | 2019-03-19 | 中广核研究院有限公司 | Presurized water reactor power generator turbine, which has tripped, characterizes signal generating method |
| CN110783009A (en) * | 2019-12-06 | 2020-02-11 | 华能山东石岛湾核电有限公司 | Automatic debugging device and method for high-temperature gas cooled reactor safety control system |
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