CN114374389A - Control circuit of successive approximation register analog-digital converter - Google Patents

Abstract

The invention discloses a control circuit of an analog-digital converter. The successive approximation register analog-to-digital converter comprises a comparator and a switched capacitor digital-to-analog converter. The switched capacitor digital-to-analog converter includes a target capacitance. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and to a second reference voltage through a second switch. The control circuit comprises a third switch and a buffer circuit. A third switch is coupled between the first reference voltage and the second end of the target capacitance. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch by a control signal. When the first switch and the third switch are conducted, the second switch is not conducted, and when the second switch is conducted, the first switch and the third switch are not conducted.

Description

Control circuit of successive approximation register analog-digital converter

Technical Field

The present invention relates to an analog-to-digital converter (ADC) (hereinafter referred to as SAR ADC), and more particularly, to a control circuit of the SAR ADC.

Background

In the following description, one end of the capacitively coupled comparator is referred to as an "upper plate", and one end of the non-coupled comparator is referred to as a "lower plate". Such definitions are for convenience of description only and do not necessarily relate to "up" and "down" in actual circuits.

Fig. 1 is a functional block diagram of a prior art SAR ADC. The SAR ADC is used to convert the analog input signal Vi into a digital signal (i.e., digital code D). The SAR ADC mainly includes a switched-capacitor (switched-capacitor) digital-to-analog converter (DAC) 110, a comparator 120, a successive approximation register 130, and a control circuit 140. The SAR ADC operates according to the frequency CLK. In one operation of the SAR ADC, the successive approximation register 130 determines the value of one bit of the digital code D according to the comparison result of the comparator 120 (1/0), and the control circuit 140 generates the control signal G according to the digital code D. The control signal G controls the terminal voltage of the internal capacitor of the switched capacitor DAC 110 (i.e. controls the lower plate of the capacitor to be coupled to the reference voltage Vref1 or the reference voltage Vref2), so as to redistribute the charges on the capacitor, and further change the voltage of the inverting input terminal (negative terminal) or the non-inverting input terminal (positive terminal) of the comparator 120, so as to change the comparison object of the comparator 120 in the next comparison operation. Repeating the above steps, the digital code D is determined sequentially from the Most Significant Bit (MSB) to the Least Significant Bit (LSB), and the value represented by the digital code D gradually approaches the input signal Vi in the process.

Fig. 2 is an internal circuit diagram of the switched capacitor DAC 110. The switched capacitor DAC 110 includes two capacitor arrays, each capacitor array includes n capacitors (C1-Cn or C1 '-Cn') and n switches (SW 1-SWn or SW1 '-SWn') (n is a positive integer), meaning that the digital code D includes n +1 bits (D1-Dn +1, D1 is LSB, Dn +1 is MSB) and the control signal G includes n sub-control signals G1-Gn and n sub-control signals # G1- # Gn, the sub-control signals G1-Gn (or # G1- # Gn) correspond to the bits D2-Dn +1, respectively. The switches SWk and SWk' are controlled by sub-control signals Gk and # Gk, respectively (k is an integer and 1 ≦ k ≦ n). In more detail, when the switch SWk is switched to the reference voltage Vref1, the switch SWk' is switched to the reference voltage Vref 2; when the switch SWk is switched to the reference voltage Vref2, the switch SWk' is switched to the reference voltage Vref 1. Fig. 2 also shows that the input signal Vi is a differential signal (composed of signals Vip and Vin), and the switch SWip and the switch SWin are used for sampling the input signal Vi.

Each switch SWk (or SWk ') includes a first sub-switch coupled between the lower plate of the capacitance Ck (or Ck ') and a reference voltage Vref1, and a second sub-switch coupled between the lower plate of the capacitance Ck (or Ck ') and a reference voltage Vref 2. Controlled by the sub-control signal Gk (or # Gk), the first and second sub-switches are conductive or non-conductive to couple the lower plate of the capacitance Ck (or Ck') to the reference voltage Vref1 or the reference voltage Vref 2.

Fig. 3 is a circuit diagram of the comparator 120. The comparator 120 mainly includes a transistor 121 and a transistor 126. When the comparator 120 switches from the reset state (switch 125 conducting) to the compare state (switch 125 not conducting), the signals at the output Vo-and the output Vo + kick back (kick back) to the negative terminal Vi-and the positive terminal Vi + of the comparator 120 through the parasitic capacitor 122 of the transistor 121 and the parasitic capacitor 127 of the transistor 126, respectively.

As can be seen from fig. 2 and 3, the equivalent impedance coupled to the negative terminal (or the positive terminal) of the comparator 120 is closely related to the configuration of the switches SW 1-SWn (or SW1 '-SWn'), and the configuration of the switches SW 1-SWn (or SW1 '-SWn') is related to the input signal Vi. When the two input terminals of the comparator 120 are not matched in equivalent impedance, the kickback noise (kick noise) may cause an error in the comparison result of the comparator 120, thereby affecting the performance or accuracy of the SAR ADC. The impedance mismatch between the first sub-switch and the second sub-switch is a main reason for the impedance mismatch between the two input terminals of the comparator 120.

Disclosure of Invention

In view of the shortcomings of the prior art, it is an object of the present invention to provide a control circuit for a SAR ADC.

The invention provides a control circuit of a successive approximation register analog-digital converter. The successive approximation register analog-to-digital converter comprises a comparator and a switched capacitor digital-to-analog converter. The switched capacitor digital-to-analog converter includes a target capacitance. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and to a second reference voltage through a second switch. The control circuit comprises a third switch and a buffer circuit. A third switch is coupled between the first reference voltage and the second end of the target capacitance. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch by a control signal. When the first switch and the third switch are conducted, the second switch is not conducted, and when the second switch is conducted, the first switch and the third switch are not conducted.

The features, structure and effects of the present invention will be described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 is a functional block diagram of a prior art SAR ADC;

FIG. 2 is an internal circuit diagram of a switched capacitor DAC;

FIG. 3 is a circuit diagram of a comparator;

FIG. 4 is a circuit diagram of one embodiment of a sub-control circuit according to the present invention;

FIG. 5 is a circuit diagram of another embodiment of a sub-control circuit according to the present invention;

FIG. 6 is a circuit diagram of yet another embodiment of a sub-control circuit according to the present invention;

fig. 7 is a circuit diagram of still another embodiment of a sub-control circuit according to the present invention.

Detailed Description

The technical terms in the following description refer to the conventional terms in the technical field, and if some terms are described or defined in the specification, the explanation of the some terms is based on the description or the definition in the specification.

The invention relates to a control circuit of a SAR ADC. Since some of the components included in the control circuit of the SAR ADC of the present invention may be known components by themselves, the following description will not describe the details of the known components without affecting the full disclosure and feasibility of the device invention.

Please refer to fig. 2. The more matched the equivalent impedance between the lower plate of the capacitor Ck (hereinafter referred to as the target capacitor) and the reference voltage Vref1 and the equivalent impedance between the lower plate of the capacitor Ck and the reference voltage Vref2, the more independent the equivalent impedance between the two input terminals of the comparator 120 is from the configuration of the switches (SW 1-SWn and SW1 '-SWn') (i.e., the more matched the equivalent impedance coupled to the negative terminal of the comparator 120 is to the equivalent impedance coupled to the positive terminal of the comparator 120). Some embodiments are provided below to improve the impedance matching between the two inputs of the comparator 120.

Fig. 4 is a circuit diagram of an embodiment of a sub-control circuit of the present invention, which is a part of a control circuit of a SAR ADC. The sub-control circuit 400-k is used to generate the sub-control signal Gk by a control signal (i.e., the value of the bit Dk + 1). The sub-control circuit 400-k includes a buffer circuit 410 (or called a driving circuit for driving the switches 420 and 430 to be turned on) and a switch 440. The switch SWk includes a switch 420 and a switch 430. A first terminal (i.e., upper plate) of the target capacitance Ck is coupled to the comparator of the SAR ADC, a second terminal (i.e., lower plate) of the target capacitance Ck is coupled to a reference voltage Vref1 through switch 420, and to a reference voltage Vref2 through switch 430. The lower plate of the target capacitance Ck is further coupled to a reference voltage Vref1 through a switch 440. The buffer circuit 410 generates a sub-control signal Gk according to the control signal, and the sub-control signal Gk controls whether the switches 420 and 430 are turned on or off. Switch 420 and switch 430 are not substantially simultaneously conductive (i.e., switch 420 and switch 430 are not substantially simultaneously conductive except at the instant of switching when both may be simultaneously conductive). In addition to the sub-control signal Gk, the buffer circuit 410 further generates a switch control signal SC according to the control signal, and the switch control signal SC is used to control whether the switch 440 is turned on. When the switch 420 and the switch 440 are conductive, the switch 430 is non-conductive, and when the switch 430 is conductive, the switch 420 and the switch 440 are non-conductive.

The switches 420,430 and 440 may be formed of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs): the switches 420,430 and 440 may be transmission gates (transmission gates) formed by one or more MOSFETs. In some embodiments, the switch 420 has a smaller on-resistance (i.e., a larger aspect ratio) but requires a larger driving force to turn on (i.e., a larger buffer circuit is required to drive, i.e., the corresponding buffer circuit has a larger gate delay), and the switch 440 has a larger on-resistance (i.e., a smaller aspect ratio) and requires a smaller driving force (i.e., a smaller buffer circuit is required to drive, i.e., the corresponding buffer circuit has a smaller gate delay). In other words, with such a design, switch 440 conducts earlier than switch 420.

When the lower plate of the target capacitance Ck should receive the reference voltage Vref1, the sub-control circuit 400-k controls the switch 420 to be turned on and the switch 430 to be turned off by the sub-control signal Gk, and controls the switch 440 to be turned on by the switch control signal SC. In the case where the switch 440 is turned on earlier than the switch 420, the lower plate of the target capacitor Ck is coupled to the reference voltage Vref1 through the switch 440, and the switch 420 is turned on (after a certain gate delay). When both the switch 440 and the switch 420 are turned on, the lower plate of the target capacitor Ck is coupled to the reference voltage Vref1 through the switch 420 and the switch 440. The fast turn-on of the switch 440 causes the lower plate of the target capacitance Ck to receive the target voltage earlier (compared to the case without the switch 440), which helps the switched-capacitor DAC of the SAR ADC to settle faster (in other words, the SAR ADC can operate at a higher speed). On the other hand, after the switch 440 is added, the equivalent on-resistance between the lower plate of the target capacitance Ck and the reference voltage Vref1 is lower (compared to the case without the switch 440). That is, in the case where the on-resistance of the switch 420 is greater than the on-resistance of the switch 430 (e.g., due to a semiconductor process), the switch 440 may reduce the equivalent impedance between the lower plate of the target capacitance Ck and the reference voltage Vref1, in other words, may increase the impedance matching degree between the lower plate of the target capacitance Ck and the reference voltage Vref1 and between the lower plate of the target capacitance Ck and the reference voltage Vref 2.

Fig. 5 is a circuit diagram of another embodiment of a sub-control circuit of the present invention, which is a part of a control circuit of a SAR ADC. The sub-control circuit 500-k is used to generate the sub-control signal Gk by a control signal (i.e., the value of the bit Dk + 1). The sub control signal Gk includes a switch control signal Gk _1 and a switch control signal Gk _ 2. The switch control signal Gk _1 controls whether the switch 420 is turned on, and the switch control signal Gk _2 controls whether the switch 430 is turned on. In this embodiment, the sub-control circuit 500-k includes two buffer circuits: buffer circuit 510 and buffer circuit 515. The buffer circuit 510 generates the switch control signal Gk _1 and the switch control signal SC according to the control signal, and the buffer circuit 515 generates the switch control signal Gk _2 according to the control signal. In some embodiments, the switch 420 and the switch 430 are composed of different kinds of MOSFETs, and the voltage levels of the switch control signal Gk _1 and the switch control signal Gk _2 are the same. For example, the switch 420 is formed by a P-type MOSFET (PMOS), and the switch 430 is formed by an N-type MOSFET (NMOS). In some cases, buffer circuit 510 and buffer circuit 515 may be considered as a larger buffer circuit.

Fig. 6 is a circuit diagram of a sub-control circuit of a portion of a control circuit of a SAR ADC according to another embodiment of the present invention. In this embodiment, the switches 420 and 430 are respectively composed of PMOS and NMOS (both constitute one inverter, i.e., the switch SWk is composed of an inverter), and the switch 440 is composed of PMOS. The reference voltage Vref1 is the power voltage VDD of the SAR ADC, and the reference voltage Vref2 is ground level (the power voltage VDD is higher than the ground level). The buffer circuit 610 includes w buffers (buffers) 612(612-1, …, 612-x +1, …, 612-w, w > x ≧ 1) connected in series. The buffers may also be referred to as drivers, and each buffer 612 may be an inverter. The buffer circuit 610 generates the sub-control signal Gk and the switch control signal SC according to the control signal. More specifically, x buffers 612 are provided between the control signal and the switch control signal SC, and w buffers 612 are provided between the control signal and the sub-control signal Gk, where w and x are odd numbers (i.e., the switch control signal SC and the sub-control signal Gk are at the same level). Since w > x, the switch control signal SC switches level earlier than the sub-control signal Gk after the control signal switches level, i.e., there is a delay between the switch control signal SC and the sub-control signal Gk (about the delay of (w-x) buffers 612). For example, when the value of the bit Dk +1 is shifted from 0 to 1, the switch 440 will be turned on first (to switch the lower plate voltage of the target capacitor Ck rapidly), and then the switch 420 will be turned on (to make the lower plate voltage of the target capacitor Ck closer to the power supply voltage VDD, i.e., to make the equivalent impedance between the lower plate of the target capacitor Ck and the power supply voltage VDD lower).

Note that when the target capacitance of fig. 6 is capacitance Ck' instead of capacitance Ck (i.e., when the sub-control circuit is coupled to the positive terminal of the comparator 120), w and x are both even numbers.

Fig. 7 is a circuit diagram of a sub-control circuit of a SAR ADC according to a further embodiment of the present invention. The buffer circuit 710 includes w buffers 712(712-1, …, 712-y +1, …, 712-w, w > y ≧ 1) connected in series. The buffers may also be referred to as drivers, and each buffer 712 may be an inverter. This embodiment is similar to the embodiment of fig. 6, except that the switch 440 is formed by NMOS in this embodiment. Therefore, in the present embodiment, the switch control signal SC and the sub-control signal Gk have different levels, that is, w is an odd number and y is an even number.

Note that when the target capacitance of fig. 7 is capacitance Ck' instead of capacitance Ck (i.e., when the sub-control circuit is coupled to the positive terminal of the comparator 120), w is even and y is odd.

Please refer to fig. 4 and 5. It is noted that in some embodiments, the on-resistance of the switch 440 may be less than or equal to the on-resistance of the switch 420, if it is desired to achieve the goal of reducing the equivalent on-resistance between the lower plate of the target capacitance Ck and the reference voltage Vref 1.

In summary, the present invention provides a control circuit of SAR ADC, which can improve the impedance matching degree of the two input terminals of the comparator of the SAR ADC, so as to reduce the negative effect of the kickback noise of the comparator on the SAR ADC (in other words, the result of the SAR ADC is more correct). In addition, the control circuit also helps to make the switched capacitor DAC of the SAR ADC more quickly stable, thereby improving the performance of the SAR ADC (for example, the SAR ADC can be operated at a higher speed).

It should be noted that the shapes, sizes, proportions and the like of the components in the drawings are merely illustrative and are provided for persons skilled in the art to understand the application of the present invention, and are not intended to limit the scope of the present invention.

Although the embodiments of the present invention have been described above, the above embodiments are not intended to limit the scope of the present invention, and one skilled in the art may apply variations to the technical features of the present invention according to the explicit or implicit disclosure of the present invention, which may all fall into the scope of the present invention.

Description of the reference numerals

110: switched capacitor digital-to-analog converter

120: comparator with a comparator circuit

130: successive approximation register

140: control circuit

CLK: frequency of

G: control signal

D: digital code

C1-Cn, C1 '-Cn': capacitor with a capacitor element

G1-Gn, # G1- # Gn: sub control signal

Vref1, Vref 2: reference voltage

SWip, SWin, SW 1-SWn, SW1 'SWn', 125,420,430,440: switch with a switch body

121,126: transistor with a metal gate electrode

122,127: parasitic capacitance

400-k, 500-k: sub-control circuit

410,510,515,610,710: buffer circuit

Dk + 1: bit value (control signal)

SC, Gk _1, Gk _ 2: switch control signal

VDD: supply voltage

612,712: buffer device

Claims (10)

1. A control circuit for a successive approximation register adc, the successive approximation register adc comprising a comparator and a switched capacitor dac, the switched capacitor dac comprising a target capacitor, a first end of the target capacitor being coupled to an input of the comparator, a second end of the target capacitor being coupled to a first reference voltage via a first switch, the second end of the target capacitor being coupled to a second reference voltage via a second switch, the control circuit comprising:

a third switch coupled between the first reference voltage and the second terminal of the target capacitance; and

a first buffer circuit coupled to the first switch and the third switch for controlling the first switch and the third switch by a control signal;

wherein the second switch is non-conductive when the first switch and the third switch are conductive, and the first switch and the third switch are non-conductive when the second switch is conductive.

2. The control circuit of claim 1, wherein the control circuit further comprises:

and the second buffer circuit is coupled to the second switch and used for controlling the second switch through the control signal.

3. The control circuit of claim 1, wherein the first buffer circuit generates a first switch control signal for controlling the first switch via the control signal and a second switch control signal for controlling the third switch via the control signal, the first buffer circuit comprises a plurality of buffers, the control signal is separated from the first switch control signal by N buffers, the control signal is separated from the second switch control signal by M buffers, and N is greater than M.

4. The control circuit of claim 3, wherein the buffer is formed by an inverter, the first switch and the third switch are transistors of the same type, and N and M are both odd or even.

5. The control circuit of claim 3, wherein the buffers are formed by inverters, the first switch and the third switch are transistors of different types, and one of N and M is an odd number and the other is an even number.

6. The control circuit of claim 1, wherein an on-resistance of the first switch is less than an on-resistance of the third switch.

7. The control circuit of claim 1, wherein the first switch is a P-type metal oxide semiconductor field effect transistor and the first reference voltage is greater than the second reference voltage.

8. The control circuit of claim 7, wherein the third switch is a P-type metal oxide semiconductor field effect transistor.

9. The control circuit of claim 1, wherein the first buffer circuit generates a first switch control signal for controlling the first switch via the control signal and generates a second switch control signal for controlling the third switch via the control signal, and wherein a delay is provided between the first switch control signal and the second switch control signal.

10. The control circuit of claim 1, wherein the first switch and the second switch form an inverter.

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