CN114373499A

CN114373499A - Nonvolatile memory device, word line testing method thereof and memory system

Info

Publication number: CN114373499A
Application number: CN202111681162.2A
Authority: CN
Inventors: 沙观宇
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-04-19

Abstract

The application provides a nonvolatile storage device, a word line testing method thereof and a storage system. The word line testing method comprises the following steps: applying a charging voltage to at least one test word line to bring the voltage of the test word line to a target voltage; after the first time node, reducing the voltage of the test word line from the target voltage; and determining a resistance value or a leakage current value of the test word line according to a target voltage and an interval between the first time node and a second time node when the voltage of the test word line is reduced to a predetermined reference voltage.

Description

Nonvolatile memory device, word line testing method thereof and memory system

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a word line test method of a nonvolatile memory device, a nonvolatile memory system, a computer apparatus, and a computer readable medium.

Background

Non-volatile memory systems are capable of retaining data stored therein after a power failure and are widely used in computers, cellular phones, smart phones, personal digital assistants and other electronic device systems. A nonvolatile memory system generally includes a nonvolatile memory device as a storage medium and a control device for controlling the nonvolatile memory device.

A memory cell in a nonvolatile memory device may program (write) data to or read data from the memory cell by applying a corresponding voltage (e.g., a program voltage or a read voltage) to a word line connected thereto. During the process of manufacturing the word lines, the resistance values or the leakage currents of the word lines may be different due to the difference in the physical structures of the word lines (in each group of wafers or each die).

In some practical applications, the word line testing method can only determine the magnitude relationship between the resistance value or the leakage current value of the word line and a predetermined reference value, and it is difficult to pre-determine the specific value of the resistance value or the leakage current value of the word line.

Disclosure of Invention

The application provides a word line testing method of a nonvolatile memory device. The word line testing method comprises the following steps: applying a charging voltage to at least one test word line to bring the voltage of the test word line to a target voltage; after the first time node, reducing the voltage of the test word line from the target voltage; and determining a resistance value or a leakage current value of the test word line according to a target voltage and an interval between the first time node and a second time node when the voltage of the test word line is reduced to a predetermined reference voltage.

In some embodiments, the voltage of the test word line is reduced from the target voltage by grounding the test word line; and determining a resistance value of the test word line according to the interval and the target voltage.

In some embodiments, the voltage of the test word line is lowered from the target voltage by floating the test word line; determining the resistance value of the test word line according to the interval and the target voltage; and determining the leakage current value of the test word line according to the resistance value and the target voltage.

In some embodiments, the resistance value R of the test word line is determined according to the following rule:

wherein U (t) is the voltage of the test word line at the second time node, U_tragetThe target voltage, C the equivalent capacitance of the test word line, and t the spacing.

In some embodiments, after the first time node, a time point when the voltage is lowered to the reference voltage is determined as the second time node by acquiring the voltage of the test word line and comparing with the reference voltage.

In some embodiments, after the second time node, the acquiring of the voltage of the test word line is stopped.

In some embodiments, after the second time node, a flag signal indicating a test complete status is output.

In some embodiments, the flag signal is configured to be in a resistance test complete state, and the inverted signal of the flag signal is configured to be in a leakage current test complete state.

In some embodiments, the test word lines include storage word lines and bridge word lines for electrically connecting the separate storage word lines.

The present application provides a nonvolatile memory device including: a voltage generator configured to provide a test voltage pattern to at least one test word line after a first time node; a comparison module configured to obtain a voltage of the test word line and compare the voltage of the test word line with a predetermined reference voltage after the first time node; a first switch connected between the voltage generator and the test word line; and a second switch, a first end of the second switch being connected between the first switch and the voltage generator, a second end of the second switch being connected to the test module, the first switch and the second switch being configured such that after the first time node, while the voltage generator provides the test voltage pattern, the comparison module obtains the voltage of the test word line and compares the voltage of the test word line with the reference voltage.

The present application also provides a nonvolatile memory device including: at least one test word line; and peripheral circuitry electrically connected to the test word line configured to: applying a charging voltage to the test word line to bring the voltage of the test word line to a target voltage; after the first time node, reducing the voltage of the test word line from the target voltage; and determining a resistance value or a leakage current value of the test word line according to a target voltage and an interval between the first time node and a second time node when the voltage of the test word line is reduced to a predetermined reference voltage.

The present application also provides a nonvolatile memory system including: a non-volatile storage device, comprising: a voltage generator configured to provide a test voltage to at least one test word line after a first time node; a comparison module configured to obtain a voltage of the test word line and compare the voltage of the test word line with a predetermined reference voltage after the first time node; a first switch connected between the voltage generator and the test word line; the first end of the second switch is connected between the first switch and the voltage generator, and the second end of the second switch is connected with the test module; the first switch and the second switch are configured to enable the voltage generator to provide the test voltage mode after the first time node, and the comparison module obtains the voltage of the test word line and compares the voltage of the test word line with the reference voltage; a control device configured to be electrically connected to the nonvolatile memory device and to control the nonvolatile memory device to perform the word line test method of any of the embodiments as described above.

The present application further provides a computer device, comprising: a processor; and a non-volatile storage system communicatively coupled to the processor, wherein the non-volatile storage system stores a program executable by the processor, and the processor is capable of performing the word line testing method of any of the embodiments as described above when the program is executed by the processor.

The present application also provides a computer readable medium storing a computer program, wherein the computer program, when executed by a processor, implements the word line testing method of any of the embodiments as described above.

According to the word line testing method of the nonvolatile memory device, the nonvolatile memory system computer device, and the computer readable medium of the embodiment of the present application, the voltage of the test word line is continuously obtained in the testing stage after the test word line reaches the target voltage, and the resistance value or the leakage current value of the test word line is determined by using the target voltage and the interval between the time node when the voltage of the test word line is reduced to the reference voltage and the time node when the voltage of the test word line starts to be reduced, which is beneficial to screening of each word line having different resistance values or leakage current values, and also reduces the operation complexity of the word line test, and simultaneously shortens the testing time of the word line test.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a functional block diagram of a non-volatile storage device according to an embodiment of the present application;

FIGS. 2A and 2B are schematic top views of dies in an array of memory cells according to an embodiment of the present application;

FIG. 3 is an equivalent circuit schematic of a memory block according to an embodiment of the present application;

FIG. 4 is a circuit schematic of peripheral circuitry of a non-volatile memory device according to an embodiment of the present application;

FIG. 5 is a flowchart of a word line testing method of a nonvolatile memory device according to an embodiment of the present application;

fig. 6 is a timing diagram according to a word line test method of the nonvolatile memory device shown in fig. 5;

FIG. 7 is a flowchart of a word line test method of a non-volatile memory device according to another embodiment of the present application;

fig. 8 is a timing diagram according to a word line test method of the nonvolatile memory device shown in fig. 7; and

fig. 9 is a functional block diagram of a non-volatile storage system according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a functional block diagram of a nonvolatile memory device 100 according to an embodiment of the present application. As shown in fig. 1, the nonvolatile memory device 100 may include a memory cell array 110 and peripheral circuits including a page buffer 121, a row decoder 122, a column decoder 123, a voltage generator 124, a logic control module 125, a status register 126, an I/O module 127, and a data bus 128, for example. It should be understood that the operations performed by the above described circuit modules described in this application may be performed by processing circuitry. Alternatively, the processing circuitry may include, but is not limited to, hardware of logic circuitry or a hardware/software combination of a processor executing software.

The memory cell array 110 may be connected to a row decoder 122, e.g., by Word Lines (WL), and a column decoder 123, e.g., by Bit Lines (BL). Illustratively, the storage cell array 110 may include several dies (Die/LUNs), which may be a basic unit for receiving and executing, for example, a program command, a read command. Each die may include several memory planes (planes), each of which may include several memory blocks (blocks), each of which may include several pages (pages) corresponding to word lines. Illustratively, the nonvolatile memory device 100 performs an erase operation in units of memory blocks, and performs a program operation or a read operation in units of pages. It is to be noted that at least one word line in the memory cell array 110 may be used as a test word line in a word line test method to be described below.

The page buffer (or referred to as "sense amplifier") 121 may be configured to read data from the memory cell array 110 or program (write) data to the memory cell array 110 according to a control signal from the logic control module 125. In one example, the page buffer 121 may store data to be programmed to one page of the memory cell array 110. In another example, the page buffer 121 may sense a low power signal of data stored in memory cells of the memory cell array 110 in a read operation and amplify a small voltage swing to an identifiable logic level.

The row decoder 122 may be configured to be controlled by the logic control module 125 and select a memory block in the memory cell array 110, further selecting a page in the memory block. For example, row decoder 122 may be configured to select a page by driving a word line using a voltage generated by voltage generator 124.

The column decoder 123 may be configured to be controlled by the logic control module 125 and select one or more memory strings by applying the bit line voltages generated by the voltage generator 124.

The voltage generator 124 may be configured to be controlled by the logic control module 125 and generate a word line voltage (e.g., a charging voltage, a ground voltage, a read voltage, a program voltage, a pass voltage, a verify voltage, etc.), a bit line voltage, a source line voltage, and the like, to be supplied into the memory cell array 110.

Logic control module 125 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit, and logic control module 125 may perform the operating methods of at least partial word line testing described below.

Status register 126 may be coupled to logic control module 125 for storing status information that controls the operation of each peripheral circuit. Optionally, for example, a command register and an address register are coupled to the logic control module 125.

I/O circuitry 127 may be coupled to logical control module 125 to forward control commands received from a host or control device (not shown) to logical control module 125 and to forward status information received from logical control module 125 (e.g., status register 126) to the host or control device.

Fig. 2A and 2B are schematic top views of dies 200 and 300 in an array of memory cells according to an embodiment of the present application. As shown in fig. 2A, die 200 may be one example of a portion of memory cell array 110 shown in fig. 1. Die 200 may include two

storage planes

210 and 220. In other examples, die 200 may include multiple memory planes (e.g., four), which are not specifically limited by this application.

In some embodiments, each storage plane (e.g., 210) may include a first storage region 201, a second storage region 202, and a staircase region 203 located in the x-direction (e.g., word line direction) between the first storage region 201 and the second storage region 202. The first storage area 201 and the second storage area 202 may include a plurality of storage blocks (e.g., 211). It should be noted that the arrangement and number of the memory blocks in the memory plane 210 shown in fig. 2 are only examples, and the scope of the present disclosure is not limited thereto.

In some embodiments, a plurality of word lines (not shown) extending in the x-direction in the memory plane 210 may be divided into two parts, i.e., a plurality of first memory word lines and a plurality of second memory word lines, by a staircase structure (not shown) provided in the staircase region 203. The plurality of first storage word lines and the plurality of second storage word lines may be electrically connected by a plurality of bridge word lines in a bridge structure (not shown) provided in the staircase region 203. For example, the first storage word line, the second storage word line, and the bridge word line at the same height are physically connected, thereby achieving electrical connection of the first storage word line, the second storage word line, and the bridge word line at the same height. Illustratively, the staircase structure within the staircase region 203 may be used for wordline (including the first storage wordline, the second storage wordline, and the bridge wordline) pull-out, and memory cells connected by the first storage wordline and the second storage wordline located at the same height may be driven bi-directionally (in both the positive x-direction and the negative x-direction) to improve control uniformity of memory cells located within the first storage region and the second storage region.

In other embodiments, as shown in FIG. 2B, die 300 may be an example of a portion of memory cell array 110 shown in FIG. 1. Each storage plane (e.g., 310) may include a storage region 301 and staircase regions 302-1 and 302-2 located on either side of the storage region 301. Illustratively, the staircase structure within the staircase region 302-1 may be used for word line extraction, and memory cells connected by storage word lines located at the same height may be driven unidirectionally (in the positive x-direction or the negative x-direction). In this example, since the memory word lines are not divided, a bridge word line is not provided. Similarly, the storage area 301 may include a plurality of storage blocks (e.g., 311).

Fig. 3 is an equivalent circuit schematic diagram of a memory block 400 according to an embodiment of the present application. As shown in fig. 3, memory block 400 may be one example of a portion of die 200 shown in fig. 2A or die 300 shown in fig. 2B.

In some embodiments, the memory block 400 may include a plurality of memory strings, such as MS 1-MS 4. The plurality of memory strings MS 1-MS 4 may be arranged in a two-dimensional array on the xy plane. Each memory string (e.g., MS1) may extend in the z-direction and may include, in turn, a top select transistor TST1, a memory cell MC, and a bottom select transistor BST with source and drain terminals connected in series with one another. Alternatively, the memory cell MC may be a charge trapping memory cell, which can change its threshold voltage by using a tunneling effect so as to put the memory cell MC in a different memory state or erase state. Alternatively, the memory cell MC may include one of an SLC capable of storing 1-bit data, an MLC capable of storing 2-bit data, a TLC capable of storing 8-bit data, or a QLC capable of storing 16-bit data. For example, for an SLC, one memory cell MC has two memory states, for example, according to the number of carriers (e.g., electrons) in a charge trapping layer.

It should be noted that the numbers of the select transistors TST/BST and the memory cells MC in each memory string (e.g., MS1) are merely exemplary, and the number of the above structures is not specifically limited in the present application.

In some embodiments, multiple memory strings in memory block 400 (e.g., MS 1-MS 4) may be connected to a common source line CSL. For example, the source terminal of the bottom select transistor BST at the end of each memory string (e.g., MS 1-MS 4) may be connected to a common source line CSL.

In some embodiments, the gate terminals of memory cells (e.g., MC 11-MC 14) in a plurality of memory strings (e.g., MS 1-MS 4) located at the same height or a similar height from the common source line CSL may be connected to the same word line (e.g., WL 1). Illustratively, at least one word line (e.g., WL1) of the plurality of word lines WL may be used as a test word line in a word line test method to be described hereinafter.

In some embodiments, the gate terminals of the top select transistors (e.g., TST1 and TST2) located at the same height or a similar height from the common source line CSL in the memory strings MS1 and MS2 arranged in the y-direction may be connected to the same top select line TSL 1. Similarly, the gate terminals of the top select transistors (e.g., TST3 and TST4) located at the same height or a similar height from the common source line CSL in the memory strings MS3 and MS4 arranged in the y-axis direction may be connected to the same top select line TSL 2.

In some embodiments, the gate terminals of bottom transistors BST in the plurality of memory strings (e.g., MS 1-MS 4) located at the same height or a similar height from the common source line CSL may be connected to the same bottom select line BSL. In other embodiments, similar to the top select lines TSL1 and TSL2, the gate terminals of the bottom select transistors BST in the memory strings arranged in the y-axis direction, e.g., MS1 and MS2, located at the same height or at a similar height from the common source line CSL may be connected to the same bottom select line BSL1 (not shown). The gate terminals of the bottom select transistors BST located at the same height or a similar height from the common source line CSL in the memory strings arranged in the y-axis direction, for example, MS3 and MS4, may be connected to the same bottom select line BSL2 (not shown).

In some embodiments, the drain terminals of the top select transistors TST1 and TST3 located at the same height from the common source line CSL or at a similar height in the memory strings MS1 and MS3 arranged in the x-axis direction may be connected to the same bit line BL 1. The memory strings MS2 and MS4 arranged in the x-axis direction are located at the same height or a similar height from the common source line CSL, and the drain terminals of the top select transistors TST2 and TST4 located at the ends may be connected to the same bit line BL 2.

In some embodiments, the extension direction of the bit lines (e.g., BL1 and BL2) may be perpendicular to the extension direction of the top select lines (e.g., TSL1 and TSL2) according to the structure as described above.

It should be noted that the number of memory strings, word lines, bit lines, and select lines in the memory block 400 shown in fig. 3 is only an example, and the number of the above structures is not specifically limited in the present application.

In some example embodiments, word lines (e.g., including memory word lines and bridge word lines) may be fabricated using conductive materials and using conductive structures such as conductive contacts, interconnect layers of a staircase structure to make connections (both physically and electrically) with the word lines. Due to the influence of the fabrication process of the above-described structure, there may be a difference in the physical structure of each word line. In addition, each memory cell on the memory string described above can be configured using a channel structure and a part of each conductive layer corresponding thereto (another part of the conductive layer as a word line of a plurality of connected memory cells). Since the critical dimension of the channel structure is different in the height direction, the physical structure of the word lines corresponding to the memory cells arranged along the extension direction of the channel structure may also be different. It is understood that word lines may be equivalent to serially connected resistors and capacitors, which may cause, for example, differences in resistance values between the respective word lines due to differences in physical structures of the word lines, and such differences may cause, for example, program operations, program times of read operations, and read times of the read operations performed using the word lines to be affected. On the other hand, in the case where the step region is disposed in the middle of the memory plane, the resistance value of the bridge word line may also affect the control uniformity of the memory cells located in the first memory region and the second memory region.

Fig. 4 is a circuit schematic of a peripheral circuit 500 according to an embodiment of the present application. As shown in fig. 4, the peripheral circuit 500 may be a part of the peripheral circuit in the nonvolatile memory device 100 shown in fig. 1, wherein the circuit connection relationship and the function of the voltage generator 524 are described above, and the test word line 510 is any one or more of the memory blocks 400 shown in fig. 3, and for the sake of brevity, the description of the present application is omitted here.

The comparison module 529 may be coupled to the logic control module 125 shown in fig. 1 for performing at least part of operations of a word line test method (including a word line resistance test method and a word line leakage current test method) to be described below under the control of the logic control module 529. The first switch SW1 may be connected between the voltage generator 524 and the test word line 510, a first terminal of the second switch SW2 may be connected between the voltage generator 524 and the first switch SW1, and a second terminal of the second switch SW2 may be connected with the comparison module 529. For example, the first switch SW1 and the second switch SW2 may both be transistors. Illustratively, the first switch SW1 and the second switch SW2 may be turned on and off at various stages of a wordline test, such as will be described below under the control of the logic control module 125 (referring to FIG. 1), to selectively turn on the voltage generator 524, the comparison module 529, and the test wordline 510 at various stages of the wordline test. The states of the first switch SW1 and the second switch SW2 at various stages in the word line test will be described in detail below.

Fig. 5 is a flow chart of a word line (resistance) testing method 1000 of a non-volatile memory device according to an embodiment of the present application. Fig. 6 is a timing diagram according to a word line test method 1000 of the nonvolatile memory device shown in fig. 5. It should be understood that the steps shown in the word line test method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 5. The following describes steps S110 to S130 in further detail with reference to the hardware structure of the nonvolatile memory device shown in fig. 1 to 4 and fig. 6.

As shown in FIG. 6, in some embodiments, the word line test method 1000 may include a pre-test phase and a test phase. The test word line may be, for example, at least one of the plurality of word lines shown in FIG. 3, such as WL 1. Wherein the solid line represents the case where the test word line has a small resistance value, and the dotted line represents the case where the test word line has a large resistance value.

After time node t0 of the pre-test phase, referring to FIG. 4, a first switch SW1 (e.g., a transistor) may be turned on so that the voltage generator 524 and the test wordline 510 are turned on. The test word line is supplied with a charging voltage, for example, 6V to 18V, by the voltage generator 524, so that the voltage of the test word line 510 is raised. In one example, a substantially linear charging voltage, for example, may be employed such that the voltage of the test word line is continuously increased. In another example, a segmented charging voltage, for example, may be employed such that the test word line is raised in segments.

After the pre-test phase (e.g., time nodes t 0-t 1) has elapsed, the voltage of the test word line reaches the target voltage. It should be noted that, for the test word line with a larger resistance value, the voltage on the test word line rises to the target voltage more gradually, as shown by the dotted line in fig. 6. Alternatively, referring to fig. 2A, in a case where the staircase region 203 is located between the first storage region 201 and the second storage region 202, the test word line may include a storage word line (a first storage word line and a second storage word line) and a bridge word line. In other words, since the storage word line and the bridge word line are physically connected, the storage word line and the bridge word line in the test word line share the charging voltage, so that the voltage of the test word line is raised to the target voltage according to the equivalent resistance common to the storage word line and the bridge word line in the test word line.

After the time node t1 of the test phase, referring to FIG. 4, a first switch SW1 (e.g., a transistor) may be turned on so that the voltage generator 524 and the test word line 510 remain turned on. The pass voltage generator 524 is used to ground the test wordline 510, causing the test wordline 510 to be lowered in voltage. Illustratively, the voltage generator 524 may be caused to provide the ground voltage for the test word line by asserting the ground signal, e.g., high, after time node t1 of the test phase. It should be noted that, for the test word line with a larger resistance value, the voltage on the test word line is gradually decreased, as shown by the dotted line in fig. 6.

After the time node t1 of the test phase, referring to fig. 4, with the first switch SW1 conductive, the second switch SW2 (e.g., a transistor) may be rendered conductive such that the test word line 510 and the comparison module 529 are turned on such that the comparison module 529 obtains a gradually decreasing voltage of the test word line. Illustratively, the comparison module 529 may be enabled to continuously obtain the voltage on the test word line after the time node t1 that provides the ground voltage for the test word line by asserting the obtain signal, e.g., high, after the time node t1 of the test phase. Meanwhile, the comparison module 529 may compare the acquired voltage of the test word line with a predetermined reference voltage, for example, through a comparator. Alternatively, the reference voltage Vref may be, for example, 1.8V, 2.0V, or 2.2V.

After time node t1 of the test phase, as the voltage of the test word line decreases, the time node t2/t 2' at which the voltage on the test word line decreases to the reference voltage Vref may be determined by, for example, a comparator in the comparison module 529. Illustratively, the determined time interval between time node t2/t 2' and time node t1 may be stored, for example, in a register (not shown) in the comparison module 529. Illustratively, since the test word line may be equivalent to a resistor and a capacitor (RC circuit) connected in series, the resistance value of the test word line may be determined according to the time interval between the time nodes t1 and t2/t 2' stored in the register and using the following formula (1).

By performing equivalent reasoning on equation (1), the resistance value R of the test word line, i.e.,

where U (t) is the voltage on the test word line after time node t1 of the test phase, R is the equivalent resistance of the test word line, C is the equivalent capacitance of the test word line, U (t) is the voltage on the test word line_targetTo test the target voltage that the word line reaches after the pre-test phase, t is the interval between test phase time nodes t 1-t 2/t 2'.

Illustratively, the interval between the time node t 2' and the time node t1 at which the test word line having the larger resistance value is lowered to the reference voltage Vref is greater than the interval between the time node t2 and the time node t1 at which the test word line having the smaller resistance value is lowered to the reference voltage Vref. For example, when the resistance of the test word line is 1k Ω, the interval between the time nodes t1 and t2 is 2 μ s; the interval between the time nodes t1 and t2 is 4 mus when the resistance value of the test word line is 2k omega, and the interval between the time nodes t1 and t2 is 10 mus when the resistance value of the test word line is 5k omega; the interval between time nodes t1 and t2 is 20 mus when the resistance value of the test word line is 10k omega. In other words, the greater the resistance value of the test word line, the longer the interval between the time nodes t2 and t 1.

After the time node t1 of the test phase, the comparator may output a flag signal, e.g., high, while the time node t2/t2 when the voltage on the test word line is determined to have dropped to the reference voltage Vref by, e.g., the comparator in the comparison module 529. The flag signal may be used to indicate the completion status of the word line test operation, e.g., a high level of the flag signal indicates the completion of the word line resistance test operation. Illustratively, in the case where the non-volatile memory device receives a 70h/78h command, for example, the status of the word line test operation may be sent to the host or the control device by obtaining a flag signal and sending the flag signal to the status register 126 (see FIG. 1).

In some embodiments, after the time node t2/t 2' of the test phase, the second switch SW2 (e.g., a transistor) may be turned off, causing the test word line 510 and the comparison module 529 to be disconnected, causing the comparison module 529 to stop obtaining the voltage of the test word line 510. In other words, after the time node t2/t 2' at which the flag signal toggles high (i.e., indicating that the word line resistance test operation is complete), the comparison module 529 no longer obtains the voltage of the test word line, thereby facilitating a reduction in the operating time of the word line test.

After time node t3 of the test phase, the respective signals may be restored to the state prior to the pretest in preparation for resistance testing of other tested word lines. It should be noted that the comparing module 529 can synchronously obtain the voltages of the plurality of test word lines, and therefore the word line resistance testing method according to the embodiment of the present disclosure can be synchronously applied to the plurality of word lines.

In some embodiments, during the pre-test phase and the test phase, the voltage generator 524 may keep providing the ground voltage to the untested word lines, for example, so that the untested word lines do not participate in the word line resistance test of this time.

In some example embodiments, after the pre-test phase, the ground voltage is supplied to the test word line for a predetermined time, for example, to reach the target voltage, so that the voltage of the test word line is lowered for the predetermined time. Acquiring the voltage of the test word line at a time node after a predetermined time elapses, determining the magnitude of a reference resistance value corresponding to the resistance value of the test word line and the reference voltage by comparing the acquired voltage of the test word line with a predetermined reference voltage, and generating a flag signal at the time node where the resistance value of the test word line is less than (Pass) or greater than (Fail).

As described above, since there is a difference in the physical structure of each word line (in each group of wafers (Lot) or each die), there may also be a difference in the resistance value of each word line. According to the word line resistance testing method provided by the exemplary embodiment, only information that the resistance value of the tested word line is larger or smaller than the reference resistance value can be determined, and it is difficult to determine the specific resistance value of each word line, and thus it is difficult to perform a function of screening out a word line having a high resistance value. On the other hand, the reference voltage (i.e., the corresponding reference resistance) needs to be set according to, for example, each word line in each group of wafers or each die, which increases the complexity of the word line resistance test operation and the test time of the word line resistance test.

According to the word line resistance testing method provided by the embodiment of the application, the voltage of the tested word line is continuously obtained in the testing stage after the tested word line reaches the target voltage, and the resistance value of the tested word line is determined by using the target voltage and the interval between the time node when the voltage of the tested word line is reduced to the reference voltage and the time node when the voltage of the tested word line starts to be reduced, so that screening of various word lines with different resistance values is facilitated, the operation complexity of word line resistance testing can be reduced, and meanwhile, the testing time of the word line resistance testing is shortened.

Referring again to fig. 4, in contrast to some exemplary embodiments in which the test wordline is connected to the voltage generator and the comparison module through a single-pole double-throw switch, in the embodiments of the present application, the test wordline 510 can be turned on by the voltage generator 524 and provide the test wordline 510 with the ground voltage, and the comparison module 529 can also be turned on by the test wordline 510 and continuously obtain the voltage of the test wordline 510, thereby providing a hardware circuit control basis for the wordline test method 1000 described above. In addition, since the comparing module 529 is used as a part of the peripheral circuit of the nonvolatile memory device, the word line testing method 1000 may be applied to, for example, wafer testing, post-package testing before shipping, or testing during actual use of the nonvolatile memory device, which is beneficial to improving the flexibility of the word line testing.

In some example embodiments, as described above, where word lines (e.g., including memory word lines and bridge word lines) may be fabricated using conductive materials, a dielectric layer is disposed between adjacent conductive layers (i.e., word lines). As the distance between adjacent conductive layers decreases, a problem of a word line leaking to a substrate or a defect (leakage current) short-circuiting to an adjacent word line may be caused. Similarly, since there may be a difference in the physical structure of each word line, in the case of leakage current in a word line, the leakage current of each word line is different.

Fig. 7 is a flow chart of a word line (leakage) test method 2000 for a non-volatile memory device according to another embodiment of the present application. Fig. 8 is a timing diagram according to a word line test method 2000 of the nonvolatile memory device shown in fig. 7. It should be understood that the steps shown in the word line test method 2000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 7. The following further describes steps S210 to S230 with reference to the hardware structure of the nonvolatile memory device shown in fig. 1 to 4 and fig. 8. The same contents compared with the timing diagram shown in fig. 6 are not described herein again.

As shown in FIG. 8, in some embodiments, the word line testing method 2000 may include a pre-test phase and a test phase. The test word line may be, for example, at least one of the plurality of word lines shown in FIG. 3, such as WL 1. Wherein the solid line represents the case where the test word line has a small drain current value, and the dotted line represents the case where the test word line has a large drain current value.

After the pre-test phase (e.g., time nodes t 0-t 1) has elapsed, the voltage of the test word line reaches the target voltage. In comparison with the timing chart of the word line test method 1000 shown in fig. 6, the resistance values of the test word lines having different drain current values may be the same or substantially the same, and therefore, the voltage waveforms of the test word lines having different drain current values may be the same or substantially the same in the pre-test stage.

After the time node t1 of the test phase, referring to FIG. 4, a first switch SW1 (e.g., a transistor) may be turned on so that the voltage generator 524 and the test word line 510 remain turned on. The test word line is floated by the voltage generator 524. In the case where the test word line has a leakage current, the test word line is short-circuited with, for example, an adjacent word line or the substrate, so that the voltage thereof is lowered. Illustratively, the voltage generator 524 may be enabled to float the test word line by asserting the float signal, e.g., high, after time node t1 of the test phase. It should be noted that, for the test word line having a smaller drain current value, the voltage variation of the test word line decreases more gradually, as shown by the solid line in fig. 8.

After the time node t1 of the test phase, referring to fig. 4, with the first switch SW1 conductive, the second switch SW2 (e.g., a transistor) may be rendered conductive such that the test word line 510 and the comparison module 529 are turned on such that the comparison module 529 obtains a gradually decreasing voltage of the test word line. Illustratively, the comparison module 529 may be enabled to continuously obtain the voltage on the test word line after the time node t1 of floating the test word line by asserting the obtain signal, e.g., high, after the time node t1 of the test phase. Meanwhile, the comparison module 529 may compare the acquired voltage of the test word line with a predetermined reference voltage, for example, through a comparator.

After time node t1 of the test phase, as the voltage of the test word line decreases, the time node t2/t 2' at which the voltage on the test word line decreases to the reference voltage Vref may be determined by, for example, a comparator in the comparison module 529. Illustratively, the determined time interval between time node t2/t 2' and time node t1 may be stored, for example, in a register (not shown) in the comparison module 529. Illustratively, the resistance value of the test word line may be determined from the time interval of the time nodes t1 and t2/t 2' stored in the register and using equation (1) described above. Further, the voltage drop U of the test word line at the time nodes t 1-t 2/t 2' and the determined resistance value U can be used to determine the leakage current value I of the test word line as U/R.

Illustratively, the interval between the time node t2 and the time node t1 at which the test word line having the larger drain current value is lowered to the reference voltage Vref is smaller than the interval between the time node t 2' and the time node t1 at which the test word line having the smaller drain current value is lowered to the reference voltage Vref. For example, when the leakage current of the test word line is 8000nA, the interval between the time nodes t1 and t2 is 1 μ s; when the leakage current of the test word line is 2000nA, the interval between the time nodes t1 and t2 is 4 mus, and when the leakage current of the test word line is 1000nA, the interval between the time nodes t1 and t2 is 10 mus; the interval between the time nodes t1 and t2 is 20 mus when the test word line has a leakage current of 400 nA. In other words, the smaller the leakage current value of the test word line, the longer the interval between the time nodes t2 and t 1.

After the time node t1 of the test phase, the comparator may output a flag signal, e.g., high, while the time node t2/t 2' when the voltage on the test word line is determined to have dropped to the reference voltage Vref by, e.g., the comparator in the comparison module 529. The inverted signal of the flag signal may be used to indicate the completion status of the word line test operation, e.g., a low level of the flag signal indicates the completion of the word line leakage test operation. Illustratively, in the case where the non-volatile memory device receives a 70h/78h command, for example, the status of the word line test may be sent to the host or the control device by obtaining the flag signal and sending it to the status register 126 (see fig. 1). The test completion state is represented by the marking signal and the inverted signal of the marking signal in the word line resistance test and the word line leakage current test respectively, so that the two word line test methods are compatible.

After time node t3 of the test phase, the respective signals may be restored to the state prior to the pretest in preparation for performing the leakage current test for the other tested word lines.

In some example embodiments, the test word line is floated after the pre-test phase. In the case where the test word line has a leakage current, the voltage of the test word line is made to decrease. Acquiring the voltage of the test word line at a fixed time node of a stage of making the test word line float, comparing the acquired voltage of the test word line with a preset reference voltage to determine the magnitude of a reference leakage current value of the test word line corresponding to the reference voltage, and generating a marking signal of which the leakage current value of the test word line is less than (Pass) or greater than (Fail) at the time node.

As described above, since there is a difference in the physical structure of each word line in each group of wafers (Lot) or each die, there may be a difference in the leakage current value of each word line. According to the word line leakage current testing method provided by the exemplary embodiment, only information that the leakage current value of the tested word line is larger or smaller than the reference leakage current value can be determined, and it is difficult to determine the specific leakage current value of each word line, and further it is difficult to screen out the word line with a large leakage current value. On the other hand, it is necessary to set a reference voltage (i.e., a corresponding reference leakage current value) according to, for example, each group of wafers or each word line in each die, which increases the complexity of the word line leakage current test operation and the test time of the word line leakage current test.

According to the word line leakage current testing method provided by the embodiment of the application, the voltage of the tested word line is continuously obtained in the testing stage after the tested word line reaches the target voltage, and the leakage current value of the tested word line is determined by utilizing the interval between the time node when the voltage of the tested word line is reduced to the reference voltage and the time node when the voltage of the tested word line starts to be reduced and the target voltage, so that screening of various word lines with different leakage current values is facilitated, the operation complexity of word line leakage current testing can be reduced, and meanwhile, the testing time of the word line leakage current testing is shortened.

Fig. 9 is a functional block diagram of a non-volatile storage system 2000 according to an embodiment of the present application. As shown in fig. 9, the nonvolatile memory system 2000 includes a nonvolatile memory device 2100 and a control device 2200. Alternatively, the non-volatile storage system 2000 may be, for example, a solid state disk.

The non-volatile memory device 2100 may be the same as the non-volatile memory device described in any of the above embodiments, and will not be described in detail herein.

The control device 2200 may control the nonvolatile memory device 2100 through, for example, a channel CH, and the nonvolatile memory device 2100 may perform an operation based on the control of the control device 2200 in response to a request from the host 3000, for example. The nonvolatile memory device 2100 may receive a command and an address from the control device 2200 through the channel CH and access a region selected from the memory cell array 110 (refer to fig. 1) in response to the address. In other words, the nonvolatile memory device 2100 may perform an internal operation corresponding to a command on a region selected by an address. More specifically, the control device 2200 transmits a command for executing the word line test method (including the word line resistance test method 1000 and the word line leakage current test method 2000) described in any of the above embodiments and an address through the channel CH, so that the nonvolatile memory device 2100 executes the word line test method.

Embodiments of the present application also provide a computer device 10000, for example, a mobile phone, MP3 player, laptop computer, desktop computer, game console, television, or in-vehicle infotainment system. As shown in fig. 9, the computer apparatus includes: at least one processor 3100; and a non-volatile storage system 2000 communicatively connected to the at least one processor 3100; the non-volatile memory system 2000 has stored therein instructions executable by the at least one processor 3100, the instructions being executable by the at least one processor 3100 to enable the at least one processor 3100 to perform the wordline testing method as mentioned in the embodiments above.

The non-volatile memory system 2000 and the processor 3100 may be coupled by a bus that couples one or more of the various circuits of the processor 3100 and the non-volatile memory system 2000 together.

The processor 3100 is responsible for managing the bus and general processing, and may provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Non-volatile memory system 2000 may be used to store data used by processor 3100 in performing operations.

Embodiments of the present application also provide a computer-readable storage medium, such as the non-volatile storage system 2000 described above. Which stores a computer program. The computer program, when executed by a processor, implements the word line testing method mentioned in the above embodiments.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A word line testing method of a nonvolatile memory device, comprising:

applying a charging voltage to at least one test word line to bring the voltage of the test word line to a target voltage;

after a first time node, reducing a voltage of the test word line from the target voltage; and

and determining the resistance value or the leakage current value of the test word line according to the target voltage and the interval between the first time node and a second time node when the voltage of the test word line is reduced to the preset reference voltage.

2. The word line testing method of claim 1,

reducing a voltage of the test word line from the target voltage by grounding the test word line; and

and determining the resistance value of the test word line according to the interval and the target voltage.

3. The word line testing method of claim 1,

lowering a voltage of the test word line from the target voltage by floating the test word line;

determining a resistance value of the test word line according to the interval and the target voltage; and

and determining the leakage current value of the test word line according to the resistance value and the target voltage.

4. The word line testing method of claim 2 or 3, wherein the resistance value R of the test word line is determined according to the following rule:

wherein U (t) is the voltage of the test word line at the second time node, U_tragetC is the equivalent capacitance of the test word line, and t is the interval.

5. The word line testing method of claim 1,

determining a point in time when the voltage is lowered to the reference voltage as the second time node by acquiring the voltage of the test word line and comparing with the reference voltage after the first time node.

6. The word line testing method of claim 5,

stopping acquiring the voltage of the test word line after the second time node.

7. The word line testing method of claim 1,

after the second time node, a flag signal indicating a test completion status is output.

8. The word line test method of claim 7, wherein the flag signal is configured as a resistance test completion state and an inverted signal of the flag signal is configured as a leakage current test completion state.

9. The word line testing method of claim 1, wherein the test word line comprises a storage word line and a bridge word line for electrically connecting the separate storage word lines.

10. A non-volatile storage device, comprising:

a voltage generator configured to provide a test voltage pattern to at least one test word line after a first time node;

a comparison module configured to obtain a voltage of the test word line and compare the voltage of the test word line with a predetermined reference voltage after a first time node;

a first switch connected between the voltage generator and the test word line; and

a second switch, a first end of the second switch is connected between the first switch and the voltage generator, a second end of the second switch is connected with the comparison module,

the first switch and the second switch are configured such that after the first time node, while the voltage generator is caused to provide a test voltage pattern, the comparison module obtains a voltage of the test word line and compares the voltage of the test word line with the reference voltage.

11. A non-volatile storage device, comprising:

at least one test word line; and

peripheral circuitry electrically connected to the test word line configured to:

applying a charging voltage to the test word line to bring a voltage of the test word line to a target voltage;

12. A non-volatile storage system, comprising:

a non-volatile storage device, comprising:

a first switch connected between the voltage generator and the test word line;

a second switch, a first end of the second switch is connected between the first switch and the voltage generator, and a second end of the second switch is connected with the comparison module;

the first switch and the second switch are configured such that after the first time node, while the voltage generator is caused to provide a test voltage pattern, the comparison module obtains a voltage of the test word line and compares the voltage of the test word line with the reference voltage; and

a control device configured to be electrically connected to the nonvolatile memory device and control the nonvolatile memory device to perform the word line test method according to any one of claims 1 to 9.

13. A computer device, comprising:

a processor; and

a non-volatile memory system communicatively coupled to the processor, wherein the non-volatile memory system stores a program executable by the processor, and wherein the processor is capable of performing the word line testing method of any of claims 1 to 9 when the program is executed by the processor.

14. Computer readable medium, in which a computer program is stored which, when being executed by a processor, carries out the word line testing method as claimed in any one of claims 1 to 9.