CN114372440A - Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure - Google Patents

Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure Download PDF

Info

Publication number
CN114372440A
CN114372440A CN202111565374.4A CN202111565374A CN114372440A CN 114372440 A CN114372440 A CN 114372440A CN 202111565374 A CN202111565374 A CN 202111565374A CN 114372440 A CN114372440 A CN 114372440A
Authority
CN
China
Prior art keywords
layout image
integrated circuit
circuit structure
dimensional integrated
layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111565374.4A
Other languages
Chinese (zh)
Inventor
曲晨冰
王力纬
孙宸
恩云飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Electronic Product Reliability and Environmental Testing Research Institute
Original Assignee
China Electronic Product Reliability and Environmental Testing Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Electronic Product Reliability and Environmental Testing Research Institute filed Critical China Electronic Product Reliability and Environmental Testing Research Institute
Priority to CN202111565374.4A priority Critical patent/CN114372440A/en
Publication of CN114372440A publication Critical patent/CN114372440A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention relates to a layout image acquisition method and system of a three-dimensional integrated circuit structure. The method for acquiring the layout image of the three-dimensional integrated circuit structure comprises the following steps: acquiring three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure; establishing a coordinate system, acquiring coordinate information of each hardware unit in the coordinate system, and determining an effective layout image range of each hardware unit; respectively acquiring a layout image of each hardware unit based on the determined effective layout image range; splicing the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph; and obtaining a layout image of the three-dimensional integrated circuit structure based on the splicing graph. The problems that time cost of high-precision shooting is wasted in a layout-free area, and the layout image splicing difficulty and the alignment difficulty are increased in the layout-free area are solved, so that the acquisition of the layout image of the three-dimensional integrated circuit structure is more efficient and accurate, and the acquisition efficiency of the chip layout image is improved.

Description

Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a layout image acquisition method and system of a three-dimensional integrated circuit structure.
Background
In recent years, integrated circuits have been regarded as the core of modern information equipment, and have a very high intellectual property value. Therefore, in order to protect the rights and interests of the chips and avoid the proprietary layout design from being infringed, the similarity between the layout of the competitive product chip and the layout of the chips of the company needs to be judged. The three-dimensional integrated circuit adopts a separated manufacturing and heterogeneous integration mode, improves the performance and size optimization of the integrated circuit and the system, and simultaneously avoids the safety problems of counterfeiting of the integrated circuit and placement of a hardware Trojan horse in a manufacturing supply chain to a certain extent. Because the layer-by-layer photographing cost is related to the photographing magnification, in order to obtain the layout of the high-resolution competitive product chip, photographing on the heterogeneously integrated bare chip layers of different process technologies needs to adopt high-cost photographing equipment and a data processing method. The vertical interconnection structure and high integration of the three-dimensional integrated circuit cause greater technical obstruction in the study and judgment of patent infringement of competitive chips, and increase the extraction time of layout images and the cost of money.
Based on the above problems, in the existing industrialized shooting method, in the process of shooting a scanning electron microscope of a chip with a layer removed, an image in the middle of a three-dimensional bare chip presents a large number of layout-free areas, redundant blank layout-free areas waste time cost of high-precision shooting, a large number of layout-free image data storage volumes are generated, storage hardware cost and data processing difficulty are increased, and an invalid area increases splicing difficulty and alignment technology difficulty of the layout images with the same layer. Therefore, the traditional method for acquiring the layout image of the two-dimensional planar packaging integrated circuit cannot meet the requirement for acquiring the layout of the large-scale three-dimensional integrated circuit.
Disclosure of Invention
In order to solve the technical problem, the invention designs a layout image acquisition method and system of a three-dimensional integrated circuit structure so as to quickly and accurately acquire the layout image of the three-dimensional integrated circuit structure.
The invention designs a layout image acquisition method of a three-dimensional integrated circuit structure, which comprises the following steps:
acquiring three-dimensional structure information of a three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure;
establishing a coordinate system, and acquiring coordinate information of each hardware unit in the coordinate system to determine an effective layout image range of each hardware unit;
respectively acquiring a layout image of each hardware unit based on the determined effective layout image range;
splicing the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph;
and obtaining a layout image of the three-dimensional integrated circuit structure based on the splicing graph.
In one embodiment, the establishing a coordinate system, and obtaining coordinate information of each hardware unit in the coordinate system to determine an effective layout image range of each hardware unit includes:
establishing a coordinate system and determining the origin of the coordinate system;
respectively determining coordinates of two diagonal points of each hardware unit in the coordinate system;
and determining the effective layout image range of each hardware unit based on the coordinates of two diagonal points of each hardware unit in the coordinate system.
In one embodiment, the hardware unit includes a bare chip, an interposer and a substrate, the substrate is electrically connected to the interposer, and the bare chip is located on a side of the interposer away from the substrate; the acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit in the three-dimensional integrated circuit structure comprises:
obtaining the architecture of the hardware unit based on 3D X photo-development;
and acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit.
In one embodiment, the obtaining the layout images of the hardware units based on the determined effective layout image range includes:
and respectively acquiring the layout images of the hardware units layer by layer based on the determined effective layout image range.
In one embodiment, the three-dimensional integrated circuit structure further comprises: the micro-bumps, the rewiring layer, the silicon through holes, the welding spots and the wiring structure; the redistribution layer is positioned on the surface opposite to the adapter plate; the through silicon via is positioned in the adapter plate, penetrates through the adapter plate along the thickness direction, and is connected with the redistribution layer positioned on the opposite surface of the adapter plate; the micro-bumps are positioned between the bare chip and the rewiring layer so as to electrically connect the bare chip and the rewiring layer; the wiring structure is positioned on the surface of the substrate adjacent to the adapter plate; the welding spot is positioned between the substrate and the rewiring layer so as to electrically connect the rewiring layer with the wiring structure; the step of respectively acquiring the layout images of the hardware units layer by layer based on the determined effective layout image range comprises the following steps:
shooting the micro-bumps based on the determined effective domain image range of the bare chip to obtain domain images of the micro-bumps;
shooting the rewiring layer and the through silicon via based on the determined effective layout image range of the adapter plate to obtain a layout image of the rewiring layer and a layout image of the through silicon via;
shooting the welding spot based on the determined effective layout image range of the adapter plate to obtain a layout image of the welding spot;
and acquiring a layout image of the wiring structure based on the determined effective layout image range of the substrate.
In one embodiment, the obtaining a layout image of the three-dimensional integrated circuit structure based on the mosaic pattern includes:
and obtaining the layout image of the three-dimensional integrated circuit structure based on the splicing graph, the layout image of the micro-convex points, the layout image of the rewiring layer, the layout image of the through silicon via, the layout image of the welding points and the layout image of the wiring structure.
In one embodiment, the obtaining the layout image of the three-dimensional integrated circuit structure based on the mosaic pattern, the layout image of the micro-bumps, the layout image of the redistribution layer, the layout image of the through silicon via, the layout image of the solder joints, and the layout image of the wiring structure includes:
and carrying out image alignment on the splicing graph, the domain image of the micro-convex points, the domain image of the redistribution layer, the domain image of the through silicon via, the domain image of the welding points and the domain image of the wiring structure to obtain the domain image of the three-dimensional integrated circuit structure.
The invention also provides a layout image acquisition system of the three-dimensional integrated circuit structure, which comprises the following steps:
the system comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure;
the second acquisition module is connected with the first acquisition module and used for establishing a coordinate system and acquiring coordinate information of each hardware unit in the coordinate system so as to determine the effective layout image range of each hardware unit;
the third acquisition module is connected with the second acquisition module and is used for respectively acquiring the layout image of each hardware unit based on the determined effective layout image range;
the splicing module is respectively connected with the second acquisition module and the third acquisition module, and splices the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph;
and the integration module is connected with the splicing module and is used for obtaining a layout image of the three-dimensional integrated circuit structure based on the spliced graph.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the layout image acquisition method of the three-dimensional integrated circuit structure when executing the computer program.
The present invention also provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the layout image acquisition method for a three-dimensional integrated circuit structure according to any one of the above.
The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the method for obtaining a layout image of a three-dimensional integrated circuit structure as described in any one of the above.
The invention has the following beneficial effects:
the invention relates to a layout image acquisition method and a layout image acquisition system of a three-dimensional integrated circuit structure, wherein the layout image acquisition method of the three-dimensional integrated circuit structure acquires three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure, establishes a coordinate system, acquires the coordinate information of each hardware unit in the coordinate system, and determines the effective layout image range of each hardware unit so as to reduce redundant image data of the three-dimensional integrated circuit layout in the shooting, splicing and aligning processes; the method comprises the steps of respectively obtaining layout images of the hardware units based on a determined effective layout image range, splicing the layout images of the hardware units based on coordinate information of the hardware units to obtain a spliced graph, and obtaining the layout image of the three-dimensional integrated circuit structure based on the spliced graph, so that the problems that a redundant blank layout-free area wastes time cost for high-precision shooting, a large amount of layout-free image data storage capacity is generated, the hardware storage cost and the data processing difficulty are increased, and an invalid area increases the same-layer layout image splicing difficulty and the alignment technology difficulty are solved, the obtaining of the layout image of the three-dimensional integrated circuit structure can be more efficient and accurate, the obtaining efficiency of the chip layout image is improved, and the flow of integrated circuit intellectual property protection is accelerated.
Drawings
FIG. 1 is a schematic flow chart of a layout image acquisition method for a three-dimensional integrated circuit structure according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a layout image obtaining method of a three-dimensional integrated circuit structure according to an embodiment of the present invention, in which a coordinate system is established to obtain coordinate information of each hardware unit in the coordinate system, so as to determine an effective layout image range of each hardware unit;
FIG. 3 is a schematic structural diagram of a three-dimensional integrated circuit structure of a layout image acquisition method of the three-dimensional integrated circuit structure according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for acquiring a layout image of a three-dimensional integrated circuit structure according to an embodiment of the present invention, in which the method is based on an architecture of a hardware unit in the three-dimensional integrated circuit structure to acquire three-dimensional structure information of the three-dimensional integrated circuit structure;
fig. 5 is a schematic flow chart of a layout image obtaining method of a three-dimensional integrated circuit structure according to an embodiment of the present invention, in which the layout images of each hardware unit are obtained layer by layer based on a determined effective layout image range;
FIG. 6 is a schematic diagram of establishing a coordinate system for a layout image acquisition method of a three-dimensional integrated circuit structure according to an embodiment of the present invention; wherein, the A area is an effective layout image area of the substrate; the B area is an effective layout image area of the adapter plate; the C area is an effective layout image area of one of the bare chips; the D area is an effective layout image area of another bare chip; the area E is an effective layout image area of another bare chip;
FIG. 7 is a diagram illustrating a layout image of a bare chip obtained by the method for obtaining a layout image of a three-dimensional integrated circuit structure according to an embodiment of the present invention; the C area is an effective layout image area of one of the bare chips;
fig. 8 is a schematic diagram of obtaining a layout image of an interposer according to the layout image obtaining method of the three-dimensional integrated circuit structure in one embodiment of the present invention; the B area is an effective layout image area of the adapter plate;
fig. 9 is a schematic diagram of obtaining a layout image of a substrate surface according to the layout image obtaining method of the three-dimensional integrated circuit structure in one embodiment of the present invention; wherein, the A area is an effective layout image area of the substrate;
FIG. 10 is a schematic diagram of a layout image acquisition system for a three-dimensional integrated circuit structure, in accordance with an embodiment of the present invention;
fig. 11 is an internal structural diagram of a computer device in one embodiment of the present invention.
Description of reference numerals:
1. a substrate; 2. welding spots; 3. an adapter plate; 4. a rewiring layer; 5. a through silicon via; 6. micro-bumps; 7. a bare chip; 11. a first acquisition module; 12. a second acquisition module; 13. a third obtaining module; 14. a splicing module; 15. and integrating the modules.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In recent years, integrated circuits have been regarded as the core of modern information equipment, and have a very high intellectual property value. Therefore, in order to protect the rights and interests of the chips and avoid the proprietary layout design from being infringed, the similarity between the layout of the competitive product chip and the layout of the chips of the company needs to be judged. The three-dimensional integrated circuit adopts a separated manufacturing and heterogeneous integration mode, improves the performance and size optimization of the integrated circuit and the system, and simultaneously avoids the safety problems of counterfeiting of the integrated circuit and placement of a hardware Trojan horse in a manufacturing supply chain to a certain extent. Because the layer-by-layer photographing cost is related to the photographing magnification, in order to obtain the layout of the high-resolution competitive product chip, photographing on the heterogeneously integrated bare chip layers of different process technologies needs to adopt high-cost photographing equipment and a data processing method. The vertical interconnection structure and high integration of the three-dimensional integrated circuit cause greater technical obstruction in the study and judgment of patent infringement of competitive chips, and increase the extraction time of layout images and the cost of money.
Based on the above problems, in the existing industrialized shooting method, in the process of shooting a scanning electron microscope of a chip with a layer removed, an image in the middle of a three-dimensional bare chip presents a large number of layout-free areas, redundant blank layout-free areas waste time cost of high-precision shooting, a large number of layout-free image data storage volumes are generated, storage hardware cost and data processing difficulty are increased, and an invalid area increases splicing difficulty and alignment technology difficulty of the layout images with the same layer. Therefore, the traditional method for acquiring the layout image of the two-dimensional planar packaging integrated circuit cannot meet the requirement for acquiring the layout of the large-scale three-dimensional integrated circuit.
In order to solve the technical problem, the invention designs a layout image acquisition method and system of a three-dimensional integrated circuit structure so as to quickly and accurately acquire the layout image of the three-dimensional integrated circuit structure.
The invention designs a layout image acquisition method of a three-dimensional integrated circuit structure, as shown in figure 1, the layout image acquisition method of the three-dimensional integrated circuit structure comprises the following steps:
s101: acquiring three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure;
s102: establishing a coordinate system, and acquiring coordinate information of each hardware unit in the coordinate system to determine an effective layout image range of each hardware unit;
s103: respectively acquiring a layout image of each hardware unit based on the determined effective layout image range;
s104: splicing the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph;
s105: and obtaining a layout image of the three-dimensional integrated circuit structure based on the splicing graph.
The invention relates to a layout image acquisition method of a three-dimensional integrated circuit structure, which is characterized in that three-dimensional structure information of the three-dimensional integrated circuit structure is acquired based on the architecture of a hardware unit in the three-dimensional integrated circuit structure, a coordinate system is established, the coordinate information of each hardware unit in the coordinate system is acquired, and the effective layout image range of each hardware unit is determined, so that redundant image data of a three-dimensional integrated circuit layout is reduced in the processes of shooting, splicing and aligning; the method comprises the steps of respectively obtaining layout images of all hardware units based on a determined effective layout image range, splicing the layout images of all hardware units based on coordinate information of all hardware units to obtain a spliced graph, and obtaining the layout image of the three-dimensional integrated circuit structure based on the spliced graph.
In one embodiment, as shown in fig. 2, establishing a coordinate system, and acquiring coordinate information of each hardware unit in the coordinate system to determine an effective layout image range of each hardware unit includes:
s201: establishing a coordinate system and determining the origin of the coordinate system;
s202: respectively determining coordinates of two diagonal points of each hardware unit in a coordinate system;
s203: and determining the effective layout image range of each hardware unit based on the coordinates of two diagonal points of each hardware unit in a coordinate system.
In one embodiment, the three-dimensional integrated circuit structure further includes a plastic package layer, at least part of the hardware units are located in the plastic package layer, and the plastic package layer may be an epoxy resin layer; before the coordinates of the two diagonal points of each hardware unit in the coordinate system are respectively determined, the method can further comprise the step of removing the plastic package layer to expose each hardware unit.
In one embodiment, the step of respectively obtaining the layout images of the hardware units based on the determined effective layout image range includes the step of respectively obtaining the layout images of the hardware units layer by layer based on the determined effective layout image range.
In one embodiment, as shown in fig. 3, a hardware unit in a three-dimensional integrated circuit structure includes a bare chip 7, an interposer 3, and a substrate 1, where the substrate 1 is electrically connected to the interposer 3, and the bare chip 7 is located on a side of the interposer 3 away from the substrate 1; with reference to fig. 4 in conjunction with fig. 1, acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit in the three-dimensional integrated circuit structure includes:
s401: obtaining a hardware unit architecture based on 3D X photo-development;
s402: and acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit.
With continued reference to fig. 3, in one embodiment, the three-dimensional integrated circuit structure further comprises: the structure comprises a micro bump 6, an RDL (redistribution layer 4), a silicon through hole 5, a welding spot 2 and a wiring structure; the rewiring layer 4 is positioned on the surface opposite to the adapter plate 3; the through silicon via 5 is positioned in the adapter plate 3, penetrates through the adapter plate 3 along the thickness direction, and is connected with the redistribution layer 4 positioned on the opposite surface of the adapter plate 3; the micro bumps 6 are positioned between the bare chip 7 and the rewiring layer 4 to electrically connect the bare chip 7 and the rewiring layer 4; the wiring structure is positioned on the surface of the substrate 1 adjacent to the adapter plate 3; the solder joints 2 are positioned between the substrate 1 and the rewiring layer 4 to electrically connect the rewiring layer 4 with the wiring structure; referring to fig. 1 to 4 in combination with fig. 5, acquiring the layout image of each hardware unit layer by layer based on the determined effective layout image range includes:
s501: shooting the micro-bumps 6 based on the determined effective domain image range of the bare chip 7 to obtain domain images of the micro-bumps 6;
s502: shooting the redistribution layer 4 and the through silicon via 5 based on the determined effective layout image range of the adapter plate 3 to obtain a layout image of the redistribution layer 4 and a layout image of the through silicon via 5;
s503: shooting the welding spot 2 based on the determined effective layout image range of the adapter plate 3 to obtain a layout image of the welding spot 2;
s504: a layout image of the wiring structure is acquired based on the determined effective layout image range of the substrate 1.
Specifically, the layer-by-layer shooting is to shoot one layer, and remove one layer to shoot the next layer; for example, after the bare chip 7 is photographed, the bare chip 7 may be removed by grinding or the like to expose the micro bumps 6; shooting the adapter plate 3, the through silicon via 5, the welding spot 2 and the like layer by layer in sequence.
It should be noted that the layout image obtaining method of the three-dimensional integrated circuit structure of the present invention is not limited to the three-dimensional integrated circuit structure in the above embodiment, but is also applicable to all other types of three-dimensional integrated circuit structures, and the circuit structure presented in the above embodiment is not used to limit the application scope of the present invention.
In one embodiment, the obtaining of the layout image of the three-dimensional integrated circuit structure based on the mosaic pattern comprises the step of obtaining the layout image of the three-dimensional integrated circuit structure based on the mosaic pattern, the layout image of the micro-bumps 6, the layout image of the redistribution layer 4, the layout image of the through silicon vias 5, the layout image of the welding spots 2 and the layout image of the wiring structure.
In one embodiment, obtaining the layout image of the three-dimensional integrated circuit structure based on the mosaic graph, the layout image of the micro-bumps 6, the layout image of the redistribution layer 4, the layout image of the through silicon vias 5, the layout image of the welding spots 2 and the layout image of the wiring structure comprises the step of performing image alignment on the mosaic graph, the layout image of the micro-bumps 6, the layout image of the redistribution layer 4, the layout image of the through silicon vias 5, the layout image of the welding spots 2 and the layout image of the wiring structure to obtain the layout image of the three-dimensional integrated circuit structure.
Specifically, the image alignment includes: aligning the image with a plurality of positioning points; the positioning points include positioning points determined by the position relationship between the bare chip and the micro-bump 6, positioning points determined by the position relationship between the micro-bump 6 and the silicon-based substrate, positioning points determined by the position relationship between the silicon-based substrate and the solder joint 2, positioning points determined by the position relationship between the solder joint 2 and the substrate 1, and the like. For convenience of use, the data of the positioning points can be arranged into coordinate points in the z-axis direction.
Specifically, the three-dimensional structure information includes the number and size of the bare chips 7, the overall layout of the silicon interposer 3 interconnections, and the like.
Specifically, the bare chip 7 may include, but is not limited to: an FPGA (Field-Programmable Gate Array) bare chip, a processor chip, a reduced instruction set computer chip, a digital signal processing technology chip, a memory chip, an interface circuit chip, a digital-to-analog conversion chip, an AI chip or a radio frequency chip.
Specifically, the material of the rewiring layer 4 may include, but is not limited to, copper, aluminum, or gold; the material of the microbump 6 may include, but is not limited to, aluminum, tin, aluminum-tin alloy, copper-tin alloy, nickel, or silver; the material of the solder joint 2 may include, but is not limited to, nickel, gold, copper, or solder alloy.
In one embodiment, the through-silicon via 5 includes a ring-shaped isolation layer therein, and the material of the ring-shaped isolation layer may include, but is not limited to, silicon dioxide, benzocyclobutene, or polyimide resin; also included within the through silicon via 5 is a fill material, which may include, but is not limited to, copper, aluminum, or tungsten; the shape of the filler material may be cylindrical.
In one embodiment, before the coordinate system is established and the coordinate information of each hardware unit in the coordinate system is obtained to determine the effective layout image range of each hardware unit, the method further comprises the steps of cutting and polishing the vertical section of the three-dimensional integrated circuit structure, shooting the section image, collecting the section information of the three-dimensional integrated circuit in the z-axis direction, and obtaining the process and material information of each hardware unit of the layout of the three-dimensional integrated circuit structure. Specifically, the process information mainly includes a process type, a process size, and the like; specifically, the process information includes process information of the bare chip 7, process information of the through-silicon via 5, and the like; the process information of the bare chip 7 may include, but is not limited to, a CMOS (Complementary Metal-Oxide-Semiconductor) process, a BiCMOS process, a SiN process, and a GaAs process; the process information of the through silicon via 5 may include, but is not limited to, a via-first process and a via-last process; the process size comprises the material and thickness of the substrate 1, the thickness of the adapter plate 3, the thickness of the rewiring layer 4, the diameter size of the through silicon via 5, the welding spot 2 and the micro bump 6, the thickness of the annular isolation layer of the through silicon via 5, and the height and diameter of the metal column of the filling material of the through silicon via 5.
For convenience of understanding, in an embodiment, the three-dimensional integrated circuit structure may be a silicon stacked interconnection FPGA structure, and a schematic structural diagram of the silicon stacked interconnection FPGA structure still refers to fig. 3, in this embodiment, the bare chip 7 employs an FPGA bare chip, and the interposer 3 employs a silicon interposer, and the layout image acquisition method based on the three-dimensional integrated circuit structure of the present invention performs image acquisition on the layout of the silicon stacked interconnection FPGA structure, and a hardware unit of the silicon stacked interconnection FPGA structure includes the bare chip 7, the micro bumps 6, the redistribution layer 4, the interposer 3, the solder joints 2, and the substrate 1.
Referring to fig. 3, the silicon stacked interconnect FPGA structure is, in order from top to bottom: the structure comprises a bare chip 7, micro bumps 6, through silicon vias 5, a rewiring layer 4, an adapter plate 3, welding spots 2 and a substrate 1; the rewiring layer 4 is positioned on the surface opposite to the adapter plate 3; the through silicon via 5 is positioned in the adapter plate 3, penetrates through the adapter plate 3 along the thickness direction, and is connected with the redistribution layer 4 positioned on the opposite surface of the adapter plate 3; the micro bumps 6 are positioned between the bare chip 7 and the rewiring layer 4 to electrically connect the bare chip 7 and the rewiring layer 4; the wiring structure is positioned on the surface of the substrate 1 adjacent to the adapter plate 3; the solder joints 2 are positioned between the substrate 1 and the rewiring layer 4 to electrically connect the rewiring layer 4 with the wiring structure; in this embodiment, the steps of obtaining the layout image of the silicon stacked interconnection FPGA structure by using the layout image obtaining method of the three-dimensional integrated circuit structure of the present invention are as follows:
step one, acquiring architectures of a bare chip 7, a micro bump 6, a first rewiring layer 4, a silicon adapter plate 3, a second rewiring layer 4, a welding spot 2 and a substrate 1 by adopting 3D X photo-development, and acquiring three-dimensional structure information of a silicon stack interconnection FPGA structure based on the architectures of hardware units; the three-dimensional structure information includes the number and size of the bare chips 7, the overall layout of the interconnection of the interposer 3, and the like;
cutting and polishing the vertical section of the silicon stacked interconnection FPGA structure, shooting a section graph, and collecting profile information of a z-axis to obtain process and material information of each hardware unit of the silicon stacked interconnection FPGA structure; the process information mainly comprises a process type, a process size and the like; specifically, in this embodiment, the through silicon via 5 includes both the through silicon via 5 obtained by the first through hole process and the through silicon via 5 obtained by the last through hole process; the adapter plate 3 is a silicon adapter plate 3;
establishing a coordinate system, and acquiring coordinate information of each hardware unit in the coordinate system to determine an effective layout image range of each hardware unit; firstly, establishing a coordinate system and determining the origin of the coordinate system; secondly, respectively determining coordinates of two diagonal points of each hardware unit in a coordinate system; then determining the effective layout image range of each hardware unit based on the coordinates of two diagonal points of each hardware unit in a coordinate system;
as shown in fig. 6, in which the two diagonal coordinates of the substrate 1 are (x1, y1) and (x2, y2), respectively, the effective layout image range of the substrate 1 is the region a composed of (x1, y1) and (x2, y 2); the coordinates of two diagonal points of the adapter plate 3 are (x3, y3) and (x4, y4), namely the effective layout image range of the adapter plate 3 is a region B consisting of (x3, y3) and (x4, y 4); the coordinates of two diagonal points of one bare chip 7 are (x5, y5) and (x6, y6), the effective layout image range of the bare chip 7 is a region C consisting of (x5, y5) and (x6, y6), the length of the region C is (y6-y5), and the width of the region C is (x6-x 5); similarly, the effective layout image range of the die 7 at other positions can be shown as the regions D and E in fig. 6.
Step four, respectively acquiring layout images of each hardware unit layer by layer based on the determined effective layout image range; fig. 7 is a schematic diagram of obtaining a layout image of the bare chip 7; fig. 8 is a schematic diagram illustrating obtaining a layout image of the interposer 3; fig. 9 is a schematic diagram showing the acquisition of a layout image of the surface of the substrate 1; in the process, a layer-by-layer shooting mode is adopted, for example, after the bare chip 7 is shot, the bare chip 7 can be removed through grinding and other processes to expose the micro bumps 6; shooting the adapter plate 3, the through silicon via 5, the welding spot 2 and the like sequentially layer by layer;
splicing the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph; carrying out image alignment on the spliced graph and the layout image of each hardware unit to obtain a layout image of the three-dimensional integrated circuit structure; for example, the layout image may be aligned by using a plurality of positioning points, such as positioning points determined by the positional relationship between the bare chip and the micro bump 6, positioning points determined by the positional relationship between the micro bump 6 and the silicon-based substrate, positioning points determined by the positional relationship between the silicon-based substrate and the solder joint 2, and positioning points determined by the positional relationship between the solder joint 2 and the substrate 1.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
Based on the same inventive concept, the invention also provides a layout image acquisition system of the three-dimensional integrated circuit structure, and the implementation scheme for solving the problems provided by the system is similar to the implementation scheme recorded in the layout image acquisition method of the three-dimensional integrated circuit structure, so the specific limitations in the layout image acquisition system embodiment of the three-dimensional integrated circuit structure provided below can be referred to the limitations of the layout image acquisition method of the three-dimensional integrated circuit structure in the above, and are not described herein again.
As shown in fig. 10, the present invention further provides a layout image acquisition system of a three-dimensional integrated circuit structure, the acquisition system including:
a first obtaining module 11, configured to obtain three-dimensional structure information of a three-dimensional integrated circuit structure based on an architecture of a hardware unit in the three-dimensional integrated circuit structure;
the second obtaining module 12 is connected with the first obtaining module 11, and is configured to establish a coordinate system and obtain coordinate information of each hardware unit in the coordinate system, so as to determine an effective layout image range of each hardware unit;
the third obtaining module 13 is connected to the second obtaining module 12, and is configured to obtain the layout images of the hardware units based on the determined effective layout image range;
the splicing module 14 is connected with the second acquisition module 12 and the third acquisition module 13 respectively, and splices the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph;
and the integration module 15 is connected with the splicing module 14 and obtains a layout image of the three-dimensional integrated circuit structure based on the spliced graph.
All modules in the layout image acquisition system of the three-dimensional integrated circuit structure can be completely or partially realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
The invention relates to a layout image acquisition method and a layout image acquisition system of a three-dimensional integrated circuit structure, wherein the layout image acquisition method of the three-dimensional integrated circuit structure acquires three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure, establishes a coordinate system, acquires the coordinate information of each hardware unit in the coordinate system, and determines the effective layout image range of each hardware unit so as to reduce redundant image data of the three-dimensional integrated circuit layout in the processes of shooting, splicing and aligning; the method comprises the steps of respectively obtaining layout images of all hardware units based on a determined effective layout image range, splicing the layout images of all hardware units based on coordinate information of all hardware units to obtain a spliced graph, and obtaining the layout image of the three-dimensional integrated circuit structure based on the spliced graph. In addition, the layout image acquisition system of the three-dimensional integrated circuit structure of the invention acquires the three-dimensional structure information of the three-dimensional integrated circuit structure through the first acquisition module 1 based on the architecture of the hardware units in the three-dimensional integrated circuit structure, establishes a coordinate system through the second acquisition module 2 and acquires the coordinate information of each hardware unit in the coordinate system to determine the effective layout image range of each hardware unit, respectively acquires the layout image of each hardware unit through the third acquisition module 3 based on the determined effective layout image range, splices the layout images of each hardware unit through the splicing module 4 based on the coordinate information of each hardware unit to obtain a spliced graph, and obtains the layout image of the three-dimensional integrated circuit structure through the integration module 5 based on the spliced graph, so that the acquisition of the layout image of the three-dimensional integrated circuit structure can be more efficient and accurate, the efficiency of obtaining chip layout images is improved, and the process of protecting intellectual property of the integrated circuit is accelerated.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 11. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a method of obtaining a layout image of a three-dimensional integrated circuit structure. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 11 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the layout image acquisition method of the three-dimensional integrated circuit structure when executing the computer program.
The present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the layout image acquisition method for a three-dimensional integrated circuit structure of any one of the above.
The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the above-described methods for obtaining a layout image of a three-dimensional integrated circuit structure.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (11)

1. A layout image acquisition method of a three-dimensional integrated circuit structure is characterized by comprising the following steps:
acquiring three-dimensional structure information of a three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure;
establishing a coordinate system, and acquiring coordinate information of each hardware unit in the coordinate system to determine an effective layout image range of each hardware unit;
respectively acquiring a layout image of each hardware unit based on the determined effective layout image range;
splicing the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph;
and obtaining a layout image of the three-dimensional integrated circuit structure based on the splicing graph.
2. The layout image obtaining method of a three-dimensional integrated circuit structure according to claim 1, wherein the establishing a coordinate system, obtaining coordinate information of each hardware unit in the coordinate system, and determining an effective layout image range of each hardware unit comprises:
establishing a coordinate system and determining the origin of the coordinate system;
respectively determining coordinates of two diagonal points of each hardware unit in the coordinate system;
and determining the effective layout image range of each hardware unit based on the coordinates of two diagonal points of each hardware unit in the coordinate system.
3. The layout image acquisition method of the three-dimensional integrated circuit structure according to claim 2, wherein the hardware unit comprises a bare chip, an interposer and a substrate, the substrate is electrically connected to the interposer, and the bare chip is located on a side of the interposer away from the substrate; the acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit in the three-dimensional integrated circuit structure comprises:
obtaining the architecture of the hardware unit based on 3D X photo-development;
and acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of the hardware unit.
4. The method of claim 3, wherein the obtaining the layout image of each hardware unit based on the determined effective layout image range comprises:
and respectively acquiring the layout images of the hardware units layer by layer based on the determined effective layout image range.
5. The method of claim 4, wherein the three-dimensional integrated circuit structure further comprises: the micro-bumps, the rewiring layer, the silicon through holes, the welding spots and the wiring structure; the redistribution layer is positioned on the surface opposite to the adapter plate; the through silicon via is positioned in the adapter plate, penetrates through the adapter plate along the thickness direction, and is connected with the redistribution layer positioned on the opposite surface of the adapter plate; the micro-bumps are positioned between the bare chip and the rewiring layer so as to electrically connect the bare chip and the rewiring layer; the wiring structure is positioned on the surface of the substrate adjacent to the adapter plate; the welding spot is positioned between the substrate and the rewiring layer so as to electrically connect the rewiring layer with the wiring structure; the step of respectively acquiring the layout images of the hardware units layer by layer based on the determined effective layout image range comprises the following steps:
shooting the micro-bumps based on the determined effective domain image range of the bare chip to obtain domain images of the micro-bumps;
shooting the rewiring layer and the through silicon via based on the determined effective layout image range of the adapter plate to obtain a layout image of the rewiring layer and a layout image of the through silicon via;
shooting the welding spot based on the determined effective layout image range of the adapter plate to obtain a layout image of the welding spot;
and acquiring a layout image of the wiring structure based on the determined effective layout image range of the substrate.
6. The method of claim 5, wherein obtaining the layout image of the three-dimensional integrated circuit structure based on the stitched pattern comprises:
and obtaining the layout image of the three-dimensional integrated circuit structure based on the splicing graph, the layout image of the micro-convex points, the layout image of the rewiring layer, the layout image of the through silicon via, the layout image of the welding points and the layout image of the wiring structure.
7. The method of claim 6, wherein obtaining the layout image of the three-dimensional integrated circuit structure based on the stitching pattern, the layout image of the micro-bumps, the layout image of the redistribution layer, the layout image of the through silicon vias, the layout image of the solder joints, and the layout image of the wiring structure comprises:
and carrying out image alignment on the splicing graph, the domain image of the micro-convex points, the domain image of the redistribution layer, the domain image of the through silicon via, the domain image of the welding points and the domain image of the wiring structure to obtain the domain image of the three-dimensional integrated circuit structure.
8. A layout image acquisition system for a three-dimensional integrated circuit structure, the acquisition system comprising:
the system comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring the three-dimensional structure information of the three-dimensional integrated circuit structure based on the architecture of a hardware unit in the three-dimensional integrated circuit structure;
the second acquisition module is connected with the first acquisition module and used for establishing a coordinate system and acquiring coordinate information of each hardware unit in the coordinate system so as to determine the effective layout image range of each hardware unit;
the third acquisition module is connected with the second acquisition module and is used for respectively acquiring the layout image of each hardware unit based on the determined effective layout image range;
the splicing module is respectively connected with the second acquisition module and the third acquisition module, and splices the layout images of the hardware units based on the coordinate information of the hardware units to obtain a spliced graph;
and the integration module is connected with the splicing module and is used for obtaining a layout image of the three-dimensional integrated circuit structure based on the spliced graph.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
11. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 7 when executed by a processor.
CN202111565374.4A 2021-12-20 2021-12-20 Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure Pending CN114372440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111565374.4A CN114372440A (en) 2021-12-20 2021-12-20 Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111565374.4A CN114372440A (en) 2021-12-20 2021-12-20 Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure

Publications (1)

Publication Number Publication Date
CN114372440A true CN114372440A (en) 2022-04-19

Family

ID=81140023

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111565374.4A Pending CN114372440A (en) 2021-12-20 2021-12-20 Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure

Country Status (1)

Country Link
CN (1) CN114372440A (en)

Similar Documents

Publication Publication Date Title
US9508688B2 (en) Semiconductor packages with interposers and methods of manufacturing the same
KR101617900B1 (en) Die stack having small diameter, high density through-wafer via and method for manufacturing of the same
US20180130782A1 (en) Stacked semiconductor package
US8450856B2 (en) Semiconductor device and method of forming the same
CN107690700B (en) Interposer for package-on-package structure
US9847285B1 (en) Semiconductor packages including heat spreaders and methods of manufacturing the same
JP2014072524A (en) Semiconductor package
US9922920B1 (en) Semiconductor package and method for fabricating the same
CN113410223B (en) Chip set and method for manufacturing the same
JP2023543035A (en) Wafer alignment design method, wafer bonding structure and chip bonding structure
CN110379798B (en) Chip stack package
US20220223512A1 (en) Semiconductor package structure
WO2012082092A1 (en) Inter-die connection within an integrated circuit formed of a stack of circuit dies
US8823171B2 (en) Semiconductor package, semiconductor device having the same, and method of manufacturing the same
US20240136295A1 (en) Front end of line interconnect structures and associated systems and methods
US11080460B2 (en) Method of modeling high speed channel in semiconductor package, method of designing semiconductor package using the same and method of manufacturing semiconductor package using the same
CN116034474A (en) Forming interconnects between dies using cross-over die and die vias
CN117751436A (en) Chip stacking structure, manufacturing method thereof, chip packaging structure and electronic equipment
CN114372440A (en) Layout image acquisition method and acquisition system of three-dimensional integrated circuit structure
US9806015B1 (en) Semiconductor packages including through mold ball connectors on elevated pads and methods of manufacturing the same
US20230052194A1 (en) Fan-out semiconductor package
US11631644B2 (en) High density pillar interconnect conversion with stack to substrate connection
US20220068820A1 (en) Front end of line interconnect structures and associated systems and methods
US10879170B2 (en) Semiconductor package and manufacturing method thereof
CN114008777A (en) Computer device and method of manufacturing computer device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination