CN114361297A - Preparation method of solar cell - Google Patents
Preparation method of solar cell Download PDFInfo
- Publication number
- CN114361297A CN114361297A CN202210128981.2A CN202210128981A CN114361297A CN 114361297 A CN114361297 A CN 114361297A CN 202210128981 A CN202210128981 A CN 202210128981A CN 114361297 A CN114361297 A CN 114361297A
- Authority
- CN
- China
- Prior art keywords
- layer
- line electrode
- grid line
- forming
- seed layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a preparation method of a solar cell, which comprises the following steps: providing a semiconductor substrate layer, further comprising: forming a transparent conductive film on at least one side of the semiconductor substrate layer; forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer; forming a mask layer on the surface of part of the seed layer, which is far away from the semiconductor substrate layer, wherein the pattern of the mask layer corresponds to an area where a grid line electrode does not need to be formed; electroplating a grid line electrode on the surface of the seed layer exposed by the mask layer; after the grid line electrode is formed, removing the mask layer; and removing the seed layer on the side part of the grid line electrode after removing the mask layer. Because the seed layer is whole before the grid line electrode is formed, no patterning is carried out, the seed layer is easier to form, the binding force between the grid line electrode and the transparent conductive film is better, and the phenomenon that the grid line electrode is separated from the transparent conductive film is prevented.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a preparation method of a solar cell.
Background
A HeteroJunction (HJT) cell is an important solar cell, and based on photovoltaic effect, solar energy is directly converted into electric energy. The heterojunction structure is a solar cell technology with market competitiveness, wherein an N-type monocrystalline silicon substrate is used as a center, and a P-type amorphous silicon layer and an N-type amorphous silicon layer are respectively arranged on two sides of the N-type monocrystalline silicon substrate, so that a PN junction and a high-low junction are formed.
Based on the current carrier generated by the heterojunction structure, the vertical collection is realized through the transparent conductive film, and the current carrier is transmitted through the metal grid line. In the prior art, a metal grid line of a solar cell is printed with low-temperature conductive silver paste by a screen printing mode, and is subjected to surface drying and curing to form an electrode, however, the low-temperature conductive silver paste is high in cost, and for an M6 monolithic cell with 166mm as an example, the silver paste with the consumption of more than 200mg is required for preparing the metal grid line, which accounts for more than 40% of the non-silicon cost of the solar cell.
In order to reduce the cost of the grid line, the prior art provides a scheme for replacing a silver grid line with a copper-tin alloy, but the lattice matching between the copper-tin alloy and the transparent conductive film is poor, so that the bonding force between the grid line electrode and the transparent conductive film is poor, and the copper-tin alloy is easy to fall off, so that the grid line electrode of the solar cell provided by the prior art needs to be improved.
Disclosure of Invention
The invention aims to solve the technical problem that a grid line electrode and a transparent conductive film of a solar cell provided by the prior art are poor in binding force and easy to fall off, and therefore the invention provides a preparation method of the solar cell.
The invention provides a preparation method of a solar cell, which comprises the following steps: providing a semiconductor substrate layer, further comprising: forming a transparent conductive film on at least one side of the semiconductor substrate layer; forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer; forming a mask layer on the surface of part of the seed layer, which is far away from the semiconductor substrate layer, wherein the pattern of the mask layer corresponds to an area where a grid line electrode does not need to be formed; electroplating a grid line electrode on the surface of the seed layer exposed by the mask layer; after the grid line electrode is formed, removing the mask layer; and removing the seed layer on the side part of the grid line electrode after removing the mask layer.
Optionally, the step of forming a transparent conductive film on at least one side of the semiconductor substrate layer includes: forming a first transparent conductive film on one side of the semiconductor substrate layer and/or forming a second transparent conductive film on the other side of the semiconductor substrate layer; the step of forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer, comprises the following steps: forming a first seed layer on the surface of one side, away from the semiconductor substrate layer, of the first transparent conductive film, and/or forming a second seed layer on the surface of one side, away from the semiconductor substrate layer, of the second transparent conductive film; the step of forming a mask layer on the surface of part of the seed layer departing from the semiconductor substrate layer comprises the following steps: forming a first mask layer on the surface of one side, away from the first transparent conductive film, of the first seed layer, and/or forming a second mask layer on the surface of one side, away from the second transparent conductive film, of the second seed layer; the step of electroplating the grid line electrode on the surface of the seed layer exposed by the mask layer comprises the following steps: electroplating a first grid line electrode on the surface of the first mask layer exposed out of the first seed layer, and/or electroplating a second grid line electrode on the surface of the second mask layer exposed out of the second seed layer; after the gate line electrode is formed, the step of removing the mask layer includes: removing the first mask layer after the first grid line electrode is formed, and/or removing the second mask layer after the second grid line electrode is formed; after removing the mask layer, the step of removing the seed layer at the side of the gate line electrode includes: and removing the first seed layer at the side part of the first grid line electrode after removing the first mask layer, and/or removing the second seed layer at the side part of the second grid line electrode after removing the second mask layer.
Optionally, the process of forming the mask layer includes an inkjet printing process.
Optionally, the material of the mask layer includes paraffin.
Optionally, the process for removing the mask layer includes a thermal treatment process or a chemical stripping process.
Optionally, the temperature of the heat treatment process is 50-150 ℃.
Optionally, when the mask layer is removed by using a chemical stripping process, a stripping solution used for removing the mask layer includes a sodium hydroxide solution or a potassium hydroxide solution.
Optionally, the process of forming the seed layer includes an electroplating process.
Optionally, the material of the seed layer includes copper or nickel.
Optionally, the thickness of the seed layer is 50nm to 150 nm.
Optionally, the process for removing the seed layer includes a chemical stripping process.
Optionally, the stripping solution used for removing the seed layer includes a sodium hydroxide solution or a potassium hydroxide solution.
Optionally, the step of electroplating the gate line electrode on the surface of the seed layer exposed by the mask layer includes: electroplating a bottom grid line electrode on the surface of the seed layer exposed by the mask layer; forming a top grid line electrode on the surface of one side, away from the semiconductor substrate layer, of the bottom grid line electrode; the melting point of the top grid line electrode is smaller than that of the bottom grid line electrode, and the electric conductivity of the bottom grid line electrode is larger than that of the top grid line electrode.
Optionally, the material of the bottom gate line electrode includes copper, and the material of the top gate line electrode includes tin.
Optionally, the thickness of the bottom gate line electrode is 3 μm to 15 μm; the thickness of the top grid line electrode is 0.3-3 mu m.
Optionally, the method further includes: and after removing the mask layer, forming a conductive protection layer on the surface of the side wall of the bottom grid line electrode.
Optionally, the process of forming the conductive protection layer includes an electroless plating process.
Optionally, the material of the conductive protection layer is the same as that of the top gate line electrode.
Optionally, the material of the conductive protection layer includes tin.
Optionally, the thickness of the conductive protection layer is 0.5 μm to 2 μm.
Optionally, after the conductive protection layer is formed, the conductive protection layer is heated, so that the conductive protection layer forms a conductive covering layer covering the sidewall surface and the top surface of the gate line electrode.
Optionally, after removing the seed layer on the side of the gate line electrode, forming the conductive protection layer; or, after the conductive protection layer is formed, the seed layer on the side portion of the gate line electrode is removed.
Optionally, the ratio of the thickness of the mask layer to the thickness of the bottom gate line electrode is 1: 0.95-1: 1.05.
Optionally, before forming the transparent conductive film, the method further includes: forming a first intrinsic semiconductor layer on one side surface of the semiconductor substrate layer; forming a first conductivity type semiconductor layer on one side surface of the first intrinsic semiconductor layer, which faces away from the semiconductor substrate layer; forming a second intrinsic semiconductor layer on the surface of one side, away from the first intrinsic semiconductor layer, of the semiconductor substrate layer; forming a second conductive type semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic semiconductor layer; the second conductive type semiconductor layer is opposite in conductivity type to the first conductive type semiconductor layer.
The technical scheme of the invention has the following beneficial effects:
1. according to the preparation method of the solar cell, the seed layer is formed on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer, and the seed layer is not patterned because the whole surface is formed before the grid line electrode is formed, so that the seed layer is easier to form, the bonding force between the seed layer and the transparent conductive film is good, and the film quality of the seed layer is higher. After the grid line electrode is formed, the seed layer on the side part of the grid line electrode is removed, and the light transmittance of the solar cell is not influenced by the seed layer. And electroplating a grid line electrode on the surface of the seed layer exposed by the mask layer, wherein the grid line electrode is indirectly connected with the transparent conductive film through the seed layer, so that the binding force between the grid line electrode and the transparent conductive film is better, and the phenomenon that the grid line electrode is separated from the transparent conductive film is prevented.
2. Furthermore, the process for forming the mask layer comprises an ink-jet printing process, so that the pattern precision of the mask layer is high, the position and the appearance of the grid line electrode are good, and the seed layer and the transparent conductive film cannot be damaged by the ink-jet printing process.
3. Furthermore, the melting point of the top grid line electrode is smaller than that of the bottom grid line electrode, and the electric conductivity of the bottom grid line electrode is larger than that of the top grid line electrode; the bottom grid line electrode has good conductivity, can better conduct the current of the solar cell, has a small melting point, can be easily welded with a welding strip in the subsequent assembly forming process of the cell, and plays a role of an adhesive layer between the bottom grid line electrode and the welding strip.
Furthermore, the material of the bottom grid line electrode comprises copper, the material of the top grid line electrode comprises tin, and the grid line electrode avoids using silver which is a material with higher cost, so that the cost of the solar cell is reduced.
4. Further, a conductive protection layer is formed on the surface of the side wall of the bottom grid line electrode, and the conductive protection layer can prevent the bottom grid line electrode from being oxidized, so that the reliability of the grid line electrode is improved.
5. Furthermore, the thickness of the conductive protection layer is thin, so that the space of the transparent conductive film between adjacent grid line electrodes is hardly occupied, and sunlight is prevented from being blocked from entering the solar cell. Because the conductive protective layer is formed after the seed layer on the side part of the grid line electrode is removed, the conductive protective layer can be prevented from being etched and damaged in the process of removing the seed layer, and the reliability of the grid line electrode is improved.
6. Furthermore, the ratio of the thickness of the mask layer to the thickness of the bottom grid line electrode is 1: 0.95-1: 1.05, the thickness of the mask layer is basically consistent with that of the bottom grid line electrode, the poor appearance of the grid line electrode caused by too low thickness of the mask layer is avoided, and the waste of mask layer materials caused by too high thickness of the mask layer is also avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a solar cell according to an embodiment of the present invention;
fig. 2 to 9 are schematic structural diagrams illustrating a process of manufacturing a solar cell according to an embodiment of the present invention;
fig. 10 to 17 are schematic structural views illustrating a process of manufacturing a solar cell according to another embodiment of the present invention.
Reference numerals:
1-a semiconductor substrate layer; 1 a-a semiconductor substrate layer; 2-a first intrinsic semiconductor layer; 2 a-a first intrinsic semiconductor layer; 3-a second intrinsic semiconductor layer; 3 a-a second intrinsic semiconductor layer; 4-a first conductivity type semiconductor layer; 4 a-a first conductivity type semiconductor layer; 5-a second conductivity type semiconductor layer; 5 a-a second conductivity type semiconductor layer; 6-a first transparent conductive film; 6 a-first transparent conductive film; 7-a second transparent conductive film; 7 a-a second transparent conductive film; 8-a first seed layer; 9-a second seed layer; 10-a first mask layer; 10 a-a first mask layer; 11-a second mask layer; 12-a first bottom layer gate line electrode; 12 a-a first bottom gate line electrode; 13-a second bottom gate line electrode; 14-a first top gate line electrode; 14 a-a first top gate line electrode; 15-a second top gate line electrode; 16-a first conductive protection layer; 16 a-a first conductive protection layer; 16 b-a first conductive cover layer; 16 c-a first conductive cover layer; 17-a second conductive protection layer; 17 b-a second conductive cover layer; 18 a-silver grid line electrode.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The present embodiment provides a method for manufacturing a solar cell, please refer to fig. 1, which includes the following steps:
and S1, providing a semiconductor substrate layer.
The semiconductor substrate layer comprises an N-type monocrystalline silicon substrate.
And S2, forming a transparent conductive film on at least one side of the semiconductor substrate layer.
In this embodiment, the transparent conductive film may be, for example, indium tin oxide.
And S3, forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer.
And S4, forming a mask layer on the surface of part of the seed layer departing from the semiconductor substrate layer, wherein the pattern of the mask layer corresponds to the area where the grid line electrode does not need to be formed.
And S5, electroplating a grid line electrode on the surface of the seed layer exposed by the mask layer.
In this embodiment, the gate line electrode includes a main gate line and a thin gate line, that is, the main gate line and the thin gate line are formed at the same time.
And S6, removing the mask layer after the grid line electrode is formed.
And S7, removing the mask layer, and removing the seed layer at the side part of the grid line electrode.
The seed layer at the side part of the gate line electrode, namely the seed layer at two sides of the bottom part of the gate line electrode, does not comprise the seed layer at the bottom part of the gate line electrode, and after the seed layer at the side part of the gate line electrode is removed, no seed layer exists between the adjacent gate line electrodes.
The step of forming a transparent conductive film on at least one side of the semiconductor substrate layer includes: and forming a first transparent conductive film on one side of the semiconductor substrate layer and/or forming a second transparent conductive film on the other side of the semiconductor substrate layer. In this embodiment, a first transparent conductive film is formed on one side of the semiconductor substrate layer and a second transparent conductive film is formed on the other side of the semiconductor substrate layer.
The step of forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer, comprises the following steps: forming a first seed layer on the surface of one side, away from the semiconductor substrate layer, of the first transparent conductive film, and/or forming a second seed layer on the surface of one side, away from the semiconductor substrate layer, of the second transparent conductive film; that is, when only the first transparent conductive film is formed, only the first seed layer is formed; when only the second transparent conductive film is formed, only the second seed layer is formed; when the first transparent conductive film and the second transparent conductive film are formed, a first seed layer and a second seed layer are formed. In this embodiment, a first seed layer is formed on a side surface of the first transparent conductive film away from the semiconductor substrate layer, and a second seed layer is formed on a side surface of the second transparent conductive film away from the semiconductor substrate layer.
The step of forming a mask layer on the surface of part of the seed layer departing from the semiconductor substrate layer comprises the following steps: forming a first mask layer on the surface of one side, away from the first transparent conductive film, of the first seed layer, and/or forming a second mask layer on the surface of one side, away from the second transparent conductive film, of the second seed layer; that is, when only the first seed layer is formed, only the first mask layer is formed; when only the second seed layer is formed, only the second mask layer is formed; when the first seed layer and the second seed layer are formed, a first mask layer and a second mask layer are formed. In this embodiment, a first mask layer is formed on a surface of the first seed layer facing away from the first transparent conductive film, and a second mask layer is formed on a surface of the second seed layer facing away from the second transparent conductive film.
The step of forming a gate line electrode on the surface of the seed layer exposed by the mask layer includes: forming a first grid line electrode on the surface of the first mask layer exposed out of the first seed layer, and/or forming a second grid line electrode on the surface of the second mask layer exposed out of the second seed layer; that is, when only the first mask layer is formed, only the first gate line electrode is formed, when only the second mask layer is formed, only the second gate line electrode is formed, and when the first mask layer and the second mask layer are formed, the first gate line electrode and the second gate line electrode are formed. In this embodiment, a first gate line electrode is formed on the surface of the first mask layer exposed by the first seed layer, and a second gate line electrode is formed on the surface of the second mask layer exposed by the second seed layer.
After the gate line electrode is formed, the step of removing the mask layer includes: removing the first mask layer after the first grid line electrode is formed, and/or removing the second mask layer after the second grid line electrode is formed; that is, when only the first gate line electrode is formed, only the first mask layer is removed; when only the second grid line electrode is formed, only the second mask layer is removed; and when the first grid line electrode and the second grid line electrode are formed, removing the first mask layer and the second mask layer. In this embodiment, the first mask layer is removed after the first gate line electrode is formed, and the second mask layer is removed after the second gate line electrode is formed.
After removing the mask layer, the step of removing the seed layer at the side of the gate line electrode includes: removing the first seed layer at the side part of the first grid line electrode after removing the first mask layer, and/or removing the second seed layer at the side part of the second grid line electrode after removing the second mask layer, namely, only removing the first seed layer at the side part of the first grid line electrode when only forming the first seed layer; when only the second seed layer is formed, only the second seed layer at the side of the second gate line electrode is removed; when the first seed layer and the second seed layer are formed, the first seed layer at the side of the first gate line electrode and the second seed layer at the side of the second gate line electrode are removed. In this embodiment, the first seed layer at the side portion of the first gate line electrode is removed after removing the first mask layer, and the second seed layer at the side portion of the second gate line electrode is removed after removing the second mask layer.
The process of forming the mask layer includes an inkjet printing process. The pattern precision of the mask layer is high, the position and the appearance of the grid line electrode are good, and the seed layer and the transparent conductive film cannot be damaged by the ink-jet printing process.
In this embodiment, the material of the mask layer includes paraffin.
The process for removing the mask layer comprises a heat treatment process or a chemical stripping process.
The temperature of the heat treatment process is 50 ℃ to 150 ℃, for example, 50 ℃, 70 ℃, 90 ℃, 110 ℃, 130 ℃ or 150 ℃.
When the mask layer is removed by adopting a chemical stripping process, a stripping solution used for removing the mask layer comprises a sodium hydroxide solution or a potassium hydroxide solution.
The process of forming the seed layer includes an electroplating process.
The material of the seed layer comprises copper or nickel. Preferably, nickel is selected, so that the electroplating grid line electrode has a better isolation effect.
The thickness of the seed layer is 50nm to 150nm, for example, 50nm, 80nm, 100nm, 120nm, or 150 nm.
The process for removing the seed layer comprises a chemical stripping process.
The stripping solution used for removing the seed layer comprises a sodium hydroxide solution or a potassium hydroxide solution.
The step of electroplating the grid line electrode on the surface of the seed layer exposed by the mask layer comprises the following steps: electroplating a bottom grid line electrode on the surface of the seed layer exposed by the mask layer; forming a top grid line electrode on the surface of one side, away from the semiconductor substrate layer, of the bottom grid line electrode; the melting point of the top grid line electrode is smaller than that of the bottom grid line electrode, and the electric conductivity of the bottom grid line electrode is larger than that of the top grid line electrode. The bottom grid line electrode has good conductivity, can better conduct the current of the solar cell, has a small melting point, can be easily welded with a welding strip in the subsequent assembly forming process of the cell, and plays a role of an adhesive layer between the bottom grid line electrode and the welding strip.
The material of the bottom grid line electrode comprises copper, and the material of the top grid line electrode comprises tin. In the embodiment, the grid line electrode replaces the traditional thin silver grid line and the traditional main silver grid line, the grid line electrode avoids using silver which is a material with higher cost, and the cost of the solar cell is reduced.
The thickness of the bottom grid line electrode is 3-15 μm, for example, 3, 5, 7, 9, 11, 13 or 15 μm; if the bottom grid line electrode is too thin, the conductivity of the grid line electrode is weaker, and if the bottom grid line electrode is too thick, the unnecessary cost of the grid line electrode is increased; the thickness of the top grid line electrode is 0.3-3 μm, for example, 0.3 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm, if the top grid line electrode is too thin, the bonding effect between the bottom grid line electrode and the solder strip is poor, and if the top grid line electrode is too thick, the unnecessary cost of the grid line electrode is increased.
The method for manufacturing a solar cell further comprises: and after removing the mask layer, forming a conductive protection layer on the surface of the side wall of the bottom grid line electrode.
In this embodiment, the bottom gate line electrode is made of copper, the top gate line electrode is made of tin, and the process of forming the conductive protection layer includes a chemical plating process. In this embodiment, because the conductive protection layer is made of tin, the redox reaction only occurs on the side wall of the bottom gate line electrode, and the top gate line electrode does not participate in the redox reaction, so that the conductive protection layer is only formed on the surface of the side wall of the bottom gate line electrode. The conductive protective layer formed by the chemical plating process is relatively uniform.
The material of the conductive protection layer is the same as that of the top grid line electrode.
In this embodiment, the material of the conductive protection layer includes tin.
The thickness of the conductive protective layer is 0.5 μm to 2 μm, for example, 0.5 μm, 1 μm, 1.5 μm, or 2 μm.
And after the conductive protective layer is formed, heating the conductive protective layer, wherein the conductive protective layer flows in a molten state, so that the conductive protective layer forms a conductive covering layer covering the side wall surface and the top surface of the grid line electrode. Therefore, the conductive covering layer is uniformly covered on the surface of the grid line electrode and has good appearance.
After removing the seed layer on the side part of the grid line electrode, forming the conductive protective layer; or, after the conductive protection layer is formed, the seed layer on the side portion of the gate line electrode is removed. Preferably, after removing the seed layer at the side of the gate line electrode, a conductive protection layer is formed.
In this embodiment, after the seed layer on the side of the gate line electrode is removed, a conductive protection layer is formed, and the conductive protection layer has a small thickness, so that the space of the transparent conductive film between adjacent gate line electrodes is hardly occupied, and sunlight is prevented from being blocked from entering the solar cell. Because the conductive protective layer is formed after the seed layer on the side part of the grid line electrode is removed, the conductive protective layer can be prevented from being etched and damaged in the process of removing the seed layer, and the reliability of the grid line electrode is improved.
The ratio of the thickness of the mask layer to the thickness of the bottom grid line electrode is 1: 0.95-1: 1.05, for example, 1:0.95, 1:1 or 1: 1.05. The thickness of the mask layer is basically consistent with that of the bottom grid line electrode, the poor appearance of the grid line electrode caused by the excessively low thickness of the mask layer is avoided, and the waste of mask layer materials caused by the excessively high thickness of the mask layer is also avoided.
In this embodiment, before forming the transparent conductive film, the method further includes:
and (5) performing texturing cleaning on the semiconductor substrate layer.
And forming a first intrinsic semiconductor layer on one side surface of the semiconductor substrate layer.
And forming a first conductivity type semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the first intrinsic semiconductor layer.
And forming a second intrinsic semiconductor layer on the surface of one side, away from the first intrinsic semiconductor layer, of the semiconductor substrate layer.
Forming a second conductive type semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic semiconductor layer; the second conductive type semiconductor layer is opposite in conductivity type to the first conductive type semiconductor layer.
After the grid line electrode is formed, the solar cell is cured at low temperature, and then the photoelectric performance of the solar cell is tested.
Referring to fig. 2 to 9, a schematic structural diagram of a process for manufacturing a solar cell according to the present embodiment is described below.
Referring to fig. 2, a semiconductor substrate layer 1 is provided.
After the etching cleaning treatment is carried out on the semiconductor substrate layer 1, a first intrinsic semiconductor layer 2 and a second intrinsic semiconductor layer 3 are deposited on two sides of the semiconductor substrate layer 1; forming a first conductivity type semiconductor layer 4 on a side of the first intrinsic semiconductor layer 2 facing away from the semiconductor substrate layer 1; forming a second conductivity type semiconductor layer 5 on a side of the second intrinsic semiconductor layer 3 facing away from the semiconductor substrate layer 1; forming a first transparent conductive film 6 on a side of the first conductivity-type semiconductor layer 4 facing away from the semiconductor substrate layer 1; a second transparent conductive film 7 is formed on a side of the second conductivity type semiconductor layer 5 facing away from the semiconductor substrate layer 1.
Referring to fig. 3, a first seed layer 8 is formed on the surface of the first transparent conductive film 6 away from the semiconductor substrate layer 1, and a second seed layer 9 is formed on the surface of the second transparent conductive film 7 away from the semiconductor substrate layer 1.
Referring to fig. 4, a first mask layer 10 is formed on a surface of a portion of the first seed layer 8 facing away from the first transparent conductive film 6, and a second mask layer 11 is formed on a surface of a portion of the second seed layer 9 facing away from the second transparent conductive film 7 by an inkjet printing process.
Referring to fig. 5, a first bottom gate line electrode 12 is formed on the surface of the first mask layer 10 exposed by the first seed layer 8 and a second bottom gate line electrode 13 is formed on the surface of the second mask layer 11 exposed by the second seed layer 9 by an electroplating process.
Referring to fig. 6, a first top gate line electrode 14 is formed on a surface of the first bottom gate line electrode 12 away from the first seed layer 8 and a second top gate line electrode 15 is formed on a surface of the second bottom gate line electrode 13 away from the second seed layer 9 by an electroplating process.
Referring to fig. 7, the first mask layer 10 and the second mask layer 11 are removed, after the first mask layer 10 and the second mask layer 11 are removed, the first seed layer 8 on the side portion of the first bottom gate line electrode 12 is removed, and the second seed layer 9 on the side portion of the second bottom gate line electrode 13 is removed.
Referring to fig. 8, a first conductive passivation layer 16 is formed on the sidewall surface of the first bottom gate line electrode 12, and a second conductive passivation layer 17 is formed on the sidewall surface of the second bottom gate line electrode 13.
Referring to fig. 9, the first conductive passivation layer 16 and the second conductive passivation layer 17 are heated, so that the first conductive passivation layer 16 forms a first conductive cap layer 16b covering the entire surface of the first gate line electrode, and the second conductive passivation layer 17 forms a second conductive cap layer 17b covering the entire surface of the second gate line electrode. The first conductive capping layer 16b covers a sidewall surface and a top surface of the first gate line electrode, and the second conductive capping layer 17b covers a sidewall surface and a top surface of the second gate line electrode.
It should be noted that in other embodiments, the first conductive protection layer 16 and the second conductive protection layer 17 may not be heated.
It should be noted that, in other embodiments, the following may be used: after the first mask layer 10 and the second mask layer 11 are removed and before the first seed layer 8 and the second seed layer 9 are removed, a first conductive protection layer is formed on the surface of the side wall of the first bottom gate line electrode 12, and a second conductive protection layer is formed on the surface of the side wall of the second bottom gate line electrode 13. In this case, when the first and second conductive protective layers are heated, the step of heating the first and second conductive protective layers is provided before the first and second seed layers 8 and 9 are removed or after the first and second seed layers 8 and 9 are removed.
Referring to fig. 10 to 17, a schematic structural diagram of a solar cell manufacturing process according to another embodiment is described below.
Referring to fig. 10, a semiconductor substrate layer 1a is provided.
After the etching cleaning treatment is carried out on the semiconductor substrate layer 1a, a first intrinsic semiconductor layer 2a and a second intrinsic semiconductor layer 3a are deposited on two sides of the semiconductor substrate layer 1 a; forming a first conductivity type semiconductor layer 4a on a side of the first intrinsic semiconductor layer 2a facing away from the semiconductor substrate layer 1 a; forming a second conductivity type semiconductor layer 5a on a side of the second intrinsic semiconductor layer 3a facing away from the semiconductor substrate layer 1 a; forming a first transparent conductive film 6a on a side of the first conductivity-type semiconductor layer 4a facing away from the semiconductor substrate layer 1 a; a second transparent conductive film 7a is formed on a side of the second conductivity-type semiconductor layer 5a facing away from the semiconductor substrate layer 1 a. The first conductive type semiconductor layer 4a is a P-type doped semiconductor layer, and the second conductive type semiconductor layer 5a is an N-type doped semiconductor layer.
Referring to fig. 11, a first seed layer 8a is formed on the surface of the first transparent conductive film 6a away from the semiconductor substrate layer 1 a.
Referring to fig. 12, a first mask layer 10a is formed on a surface of a portion of the first seed layer 8a away from the first transparent conductive film 6a by an inkjet printing process.
Referring to fig. 13, a first bottom gate line electrode 12a is formed on the surface of the first mask layer 10a exposing the first seed layer 8a through an electroplating process.
Referring to fig. 14, a first top gate line electrode 14a is formed on a surface of the first bottom gate line electrode 12a away from the first seed layer 8a by an electroplating process.
Referring to fig. 15, the first mask layer 10a is removed, and after the first mask layer 10a is removed, the first seed layer 8a on the side of the first bottom gate line electrode 12a is removed.
Referring to fig. 16, a first conductive passivation layer 16a is formed on the sidewall surface of the first bottom gate line electrode 12 a; a silver gate line electrode 18a is formed on a surface of a part of the second transparent conductive film 7a on a side facing away from the second conductivity-type semiconductor layer 5a by a screen printing process.
Referring to fig. 17, the first conductive passivation layer 16a is heated to form a first conductive covering passivation layer 16c covering the entire surface of the first gate line electrode on the first conductive passivation layer 16 a. The first conductive capping layer 16c covers the sidewall surface and the top surface of the first gate line electrode.
It should be noted that in other embodiments, the first conductive protection layer 16a may not be heated.
It should be noted that, in other embodiments, the following may be used: after removing the first mask layer 10a and before removing the first seed layer 8, a first conductive protection layer is formed on the sidewall surface of the first bottom gate line electrode 12 a. In this case, when the first conductive protective layer is heated, the step of heating the first conductive protective layer is provided before the first seed layer 8a is removed or after the first seed layer 8a is removed.
In yet another embodiment, the first conductivity type semiconductor layer is a P-type doped semiconductor layer, the second conductivity type semiconductor layer is an N-type doped semiconductor layer, a second seed layer is formed on a surface of the second transparent conductive film, which faces away from the semiconductor substrate layer, and a second mask layer is formed on a portion of the surface of the second seed layer, which faces away from the second transparent conductive film, through an inkjet printing process. Forming a second bottom layer grid line electrode on the surface of the second mask layer exposed out of the second seed layer through an electroplating process; forming a second top grid line electrode on the surface of the second bottom grid line electrode, which is far away from the second seed layer, through an electroplating process; then, removing the second mask layer; after the second mask layer is removed, removing the second seed layer on the side part of the gate line electrode at the second bottom layer; and forming a silver grid line electrode on one side surface of part of the first transparent conductive film, which is far away from the first conductive type semiconductor layer, by a screen printing process. Further, the method can also comprise the following steps: forming a second conductive protective layer on the surface of the side wall of the second bottom grid line electrode; and heating the second conductive protective layer to form a second conductive covering protective layer covering the whole surface of the second grid line electrode. The second conductive capping layer covers a sidewall surface and a top surface of the second gate line electrode. It should be noted that in other embodiments, the first conductive protection layer may not be heated. It should be noted that, in other embodiments, the following may be used: and after the second mask layer is removed and before the second seed layer is removed, forming a second conductive protective layer on the surface of the side wall of the second bottom grid line electrode. In this case, when the second conductive protective layer is heated, the step of heating the second conductive protective layer is provided before the second seed layer is removed or after the second seed layer is removed.
According to the preparation method of the solar cell, the seed layer is formed on the surface, away from the semiconductor substrate layer, of the transparent conductive film, and the seed layer is not patterned due to the fact that the whole surface of the seed layer is formed before the grid line electrode is formed, the seed layer is easy to form, the bonding force between the seed layer and the transparent conductive film is good, and the film quality of the seed layer is high. After the grid line electrode is formed, the seed layer on the side part of the grid line electrode is removed, and the light transmittance of the solar cell is not influenced by the seed layer. And electroplating a grid line electrode on the surface of the seed layer exposed by the mask layer, wherein the grid line electrode is indirectly connected with the transparent conductive film through the seed layer, so that the binding force between the grid line electrode and the transparent conductive film is better, and the phenomenon that the grid line electrode is separated from the transparent conductive film is avoided.
In the solar cell formed by the method for manufacturing the solar cell provided by the embodiment, the main grid lines and the fine grid lines are simultaneously completed in the electroplating process, so that the method not only has the effect of reducing cost, but also has the effect of improving efficiency, and the following is a result comparison table obtained by testing the solar cells manufactured in different modes. In the table, "Isc" represents a short-circuit current, "Voc" represents an open-circuit voltage, "FF" represents a fill factor, "Eta" represents conversion efficiency, and "Irev 2" represents a leakage current.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A method of fabricating a solar cell, comprising: providing a semiconductor substrate layer, further comprising:
forming a transparent conductive film on at least one side of the semiconductor substrate layer;
forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer;
forming a mask layer on the surface of part of the seed layer, which is far away from the semiconductor substrate layer, wherein the pattern of the mask layer corresponds to an area where a grid line electrode does not need to be formed;
electroplating a grid line electrode on the surface of the seed layer exposed by the mask layer;
after the grid line electrode is formed, removing the mask layer;
and removing the seed layer on the side part of the grid line electrode after removing the mask layer.
2. The method of claim 1, wherein the step of forming a transparent conductive film on at least one side of the semiconductor substrate layer comprises: forming a first transparent conductive film on one side of the semiconductor substrate layer and/or forming a second transparent conductive film on the other side of the semiconductor substrate layer;
the step of forming a seed layer on the surface of the transparent conductive film, which is far away from the semiconductor substrate layer, comprises the following steps: forming a first seed layer on the surface of one side, away from the semiconductor substrate layer, of the first transparent conductive film, and/or forming a second seed layer on the surface of one side, away from the semiconductor substrate layer, of the second transparent conductive film;
the step of forming a mask layer on the surface of part of the seed layer departing from the semiconductor substrate layer comprises the following steps: forming a first mask layer on the surface of one side, away from the first transparent conductive film, of the first seed layer, and/or forming a second mask layer on the surface of one side, away from the second transparent conductive film, of the second seed layer;
the step of electroplating the grid line electrode on the surface of the seed layer exposed by the mask layer comprises the following steps: electroplating a first grid line electrode on the surface of the first mask layer exposed out of the first seed layer, and/or electroplating a second grid line electrode on the surface of the second mask layer exposed out of the second seed layer;
after the gate line electrode is formed, the step of removing the mask layer includes: removing the first mask layer after the first grid line electrode is formed, and/or removing the second mask layer after the second grid line electrode is formed;
after removing the mask layer, the step of removing the seed layer at the side of the gate line electrode includes: and removing the first seed layer at the side part of the first grid line electrode after removing the first mask layer, and/or removing the second seed layer at the side part of the second grid line electrode after removing the second mask layer.
3. The method of claim 1, wherein the process of forming the mask layer comprises an inkjet printing process;
preferably, the material of the mask layer includes paraffin.
4. The method according to claim 1, wherein the process of removing the mask layer comprises a thermal treatment process or a chemical stripping process;
preferably, the temperature of the heat treatment process is 50-150 ℃;
preferably, when a chemical stripping process is used for removing the mask layer, the stripping solution used for removing the mask layer includes a sodium hydroxide solution or a potassium hydroxide solution.
5. The method according to claim 1, wherein the process of forming the seed layer comprises an electroplating process;
preferably, the material of the seed layer comprises copper or nickel;
preferably, the thickness of the seed layer is 50 nm-150 nm;
preferably, the process for removing the seed layer comprises a chemical stripping process;
preferably, the stripping solution used for removing the seed layer comprises a sodium hydroxide solution or a potassium hydroxide solution.
6. The method of claim 1, wherein the step of electroplating the gate line electrode on the surface of the seed layer exposed by the mask layer comprises: electroplating a bottom grid line electrode on the surface of the seed layer exposed by the mask layer; forming a top grid line electrode on the surface of one side, away from the semiconductor substrate layer, of the bottom grid line electrode; the melting point of the top grid line electrode is smaller than that of the bottom grid line electrode, and the electric conductivity of the bottom grid line electrode is larger than that of the top grid line electrode;
preferably, the material of the bottom grid line electrode comprises copper, and the material of the top grid line electrode comprises tin;
preferably, the thickness of the bottom grid line electrode is 3-15 μm; the thickness of the top grid line electrode is 0.3-3 mu m.
7. The method for manufacturing a solar cell according to claim 6, further comprising: after the mask layer is removed, forming a conductive protection layer on the surface of the side wall of the bottom grid line electrode;
preferably, the process of forming the conductive protection layer includes an electroless plating process;
preferably, the material of the conductive protection layer is the same as that of the top grid line electrode;
preferably, the material of the conductive protection layer includes tin;
preferably, the thickness of the conductive protection layer is 0.5-2 μm;
preferably, after the conductive protection layer is formed, the conductive protection layer is heated to form a conductive coating layer covering the sidewall surface and the top surface of the gate line electrode.
8. The method for manufacturing a solar cell according to claim 7, wherein the conductive protection layer is formed after removing the seed layer on the side of the gate line electrode; or, after the conductive protection layer is formed, the seed layer on the side portion of the gate line electrode is removed.
9. The method for manufacturing the solar cell according to claim 6, wherein the ratio of the thickness of the mask layer to the thickness of the bottom grid line electrode is 1: 0.95-1: 1.05.
10. The method for manufacturing a solar cell according to any one of claims 1 to 9, further comprising, before forming the transparent conductive film:
forming a first intrinsic semiconductor layer on one side surface of the semiconductor substrate layer;
forming a first conductivity type semiconductor layer on one side surface of the first intrinsic semiconductor layer, which faces away from the semiconductor substrate layer;
forming a second intrinsic semiconductor layer on the surface of one side, away from the first intrinsic semiconductor layer, of the semiconductor substrate layer;
forming a second conductive type semiconductor layer on the surface of one side, away from the semiconductor substrate layer, of the second intrinsic semiconductor layer; the second conductive type semiconductor layer is opposite in conductivity type to the first conductive type semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210128981.2A CN114361297A (en) | 2022-02-11 | 2022-02-11 | Preparation method of solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210128981.2A CN114361297A (en) | 2022-02-11 | 2022-02-11 | Preparation method of solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114361297A true CN114361297A (en) | 2022-04-15 |
Family
ID=81092902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210128981.2A Pending CN114361297A (en) | 2022-02-11 | 2022-02-11 | Preparation method of solar cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114361297A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117265608A (en) * | 2023-09-27 | 2023-12-22 | 安徽华晟新能源科技有限公司 | Electroplating method and electroplating device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701410A (en) * | 2013-12-10 | 2015-06-10 | 泉州市博泰半导体科技有限公司 | Manufacturing method of metal grating on silicon-based heterojunction cell |
| CN106816498A (en) * | 2015-12-02 | 2017-06-09 | 钧石(中国)能源有限公司 | A kind of method that mask layer is removed in solar cell metal grid lines preparation process |
| CN109148615A (en) * | 2017-06-16 | 2019-01-04 | 福建金石能源有限公司 | A kind of production method of heterojunction solar battery electrode |
| CN110634971A (en) * | 2018-05-31 | 2019-12-31 | 福建金石能源有限公司 | Back contact heterojunction solar cell and manufacturing method thereof |
| CN113130671A (en) * | 2019-12-30 | 2021-07-16 | 国家电投集团科学技术研究院有限公司 | Silicon heterojunction solar cell and preparation method thereof |
-
2022
- 2022-02-11 CN CN202210128981.2A patent/CN114361297A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701410A (en) * | 2013-12-10 | 2015-06-10 | 泉州市博泰半导体科技有限公司 | Manufacturing method of metal grating on silicon-based heterojunction cell |
| CN106816498A (en) * | 2015-12-02 | 2017-06-09 | 钧石(中国)能源有限公司 | A kind of method that mask layer is removed in solar cell metal grid lines preparation process |
| CN109148615A (en) * | 2017-06-16 | 2019-01-04 | 福建金石能源有限公司 | A kind of production method of heterojunction solar battery electrode |
| CN110634971A (en) * | 2018-05-31 | 2019-12-31 | 福建金石能源有限公司 | Back contact heterojunction solar cell and manufacturing method thereof |
| CN113130671A (en) * | 2019-12-30 | 2021-07-16 | 国家电投集团科学技术研究院有限公司 | Silicon heterojunction solar cell and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117265608A (en) * | 2023-09-27 | 2023-12-22 | 安徽华晟新能源科技有限公司 | Electroplating method and electroplating device |
| CN117265608B (en) * | 2023-09-27 | 2024-06-11 | 安徽华晟新能源科技有限公司 | Electroplating method and electroplating device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10115840B2 (en) | Solar cell and method for producing thereof | |
| JP5174903B2 (en) | Method for manufacturing solar battery cell | |
| CN105449014A (en) | Solar cell with electroplated metal grid | |
| US20200091362A1 (en) | Solar cell module and method for producing same | |
| JP2013507781A (en) | Devices including electrical contacts and manufacturing processes thereof | |
| US20100147368A1 (en) | Photovoltaic cell with shallow emitter | |
| WO2008141415A1 (en) | Photovoltaic cell with shallow emitter | |
| CN112397596A (en) | Low-cost high-efficiency solar cell and preparation method thereof | |
| CN104025308A (en) | Solar Cell Apparatus And Method Of Fabricating The Same | |
| CN104157742A (en) | Solar cell and manufacturing method thereof | |
| JP2015153934A (en) | photoelectric conversion device | |
| CN114361297A (en) | Preparation method of solar cell | |
| CN115020525A (en) | Back junction solar cell and preparation method thereof | |
| US20110011437A1 (en) | Solar cell and method for manufacturing solar cell | |
| US8852990B2 (en) | Method of fabricating solar cell | |
| US9391215B2 (en) | Device for generating photovoltaic power and method for manufacturing same | |
| CN114420796A (en) | Preparation method of electrode and preparation method of solar cell | |
| CN102468369B (en) | Method for forming metal electrode on surface of solar cell | |
| WO2010150749A1 (en) | Solar cell, solar cell with wiring sheet attached, and solar cell module | |
| JP3006711B2 (en) | Solar cell module | |
| CN212257425U (en) | Improved perovskite solar component | |
| JP7502873B2 (en) | Solar cell and method for manufacturing solar cell | |
| TWI492400B (en) | Solar cell, method for manufacturing the same and solar cell module | |
| CN113437161A (en) | Solar cell, preparation method thereof and photovoltaic module | |
| CN113380902A (en) | Monocrystalline silicon heterojunction solar cell and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |