CN114360605B - Ternary content addressing memory - Google Patents
Ternary content addressing memory Download PDFInfo
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- CN114360605B CN114360605B CN202210029995.9A CN202210029995A CN114360605B CN 114360605 B CN114360605 B CN 114360605B CN 202210029995 A CN202210029995 A CN 202210029995A CN 114360605 B CN114360605 B CN 114360605B
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- pressure control
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- 239000002184 metal Substances 0.000 claims abstract description 62
- 238000011156 evaluation Methods 0.000 claims abstract description 18
- 238000007599 discharging Methods 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 101150032602 mls-1 gene Proteins 0.000 description 9
- 101100023518 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DAL7 gene Proteins 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 101100260020 Caenorhabditis elegans mls-1 gene Proteins 0.000 description 2
- 238000012854 evaluation process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Landscapes
- Static Random-Access Memory (AREA)
Abstract
The invention discloses a ternary content addressable memory, which comprises a match line connected with a TCAM unit, wherein a comparison unit is arranged in the TCAM unit; the comparison unit is provided with a discharge circuit for discharging the matching line, and the discharge circuit is provided with a 2-level NMOS tube; the matching line is connected with a negative-pressure circuit through a discharge circuit; the negative pressure circuit includes: a first metal wire connected with the discharge circuit, and a negative pressure control unit connected with the first metal wire; the negative pressure control unit sets the first metal wire to negative pressure during the evaluation of the match line. The invention can pull down the first metal wire to be negative pressure when the matching line evaluates, and can increase VGS voltage of NMOS tube in the discharging circuit after the first metal wire is pulled down to be negative pressure, thereby increasing discharging current, increasing discharging speed of the matching line, further increasing evaluating speed of the matching line, improving searching operation efficiency, and further improving working frequency and performance of the tri-state content addressing memory.
Description
Technical Field
The present invention relates to a ternary content addressable memory.
Background
The ternary content addressable memory TCAM (Ternary Content Addressable Memory) was developed from the content addressable memory CAM (Content Addressable Memory). One memory cell of the TCAM may store one of the states 0, 1, or X. The key is connected to the entry (entry) stored in the TCAM via a search line SL (Search Line). After entering the key, the TCAM stores that each entry in the entire column matches the key at the same time, an operation called search, also called evaluation of match line ML (Match Line). If the key matches the same entry, the corresponding match line ML remains high and the corresponding sense amplifier SA (Sense Amplifier) outputs a high "1", indicating that the entry matches the key. If the key is not matched with the entry, the corresponding match line ML is discharged by the non-matched TCAM bit (bit), the match line ML voltage is discharged below the sense amplifier threshold voltage, and the sense amplifier outputs a low level "0" indicating that the entry is not matched with the key. The operating frequency of TCAM depends on the speed of the search operation, and the core depends on the speed of the discharge (i.e., evaluation) of the match line ML.
Disclosure of Invention
The invention aims to provide a ternary content addressable memory, which comprises a match line connected with a TCAM unit, wherein a comparison unit is arranged in the TCAM unit; the comparison unit is provided with a discharge circuit for discharging the matching line, and the discharge circuit is provided with a 2-level NMOS tube; the matching line is connected with a negative-pressure circuit through a discharge circuit;
The negative pressure circuit includes: a first metal wire connected with the discharge circuit, and a negative pressure control unit connected with the first metal wire;
The negative pressure control unit sets the first metal wire to negative pressure during the evaluation of the match line.
Preferably, the negative pressure control unit presets the first metal line to a low level before the match line is evaluated.
Preferably, the second metal line is parallel to the first metal line, and the second metal line is equal in length to the first metal line.
The specific structure of the negative pressure control unit and the specific control method of the negative pressure circuit are shown in the embodiment.
The invention has the advantages and beneficial effects that: a three-state content addressing memory is provided, which can pull down a first metal wire to be negative pressure when a match line is evaluated, and can increase VGS voltage of NMOS tube in a discharge circuit after the first metal wire is pulled down to be negative pressure, thereby increasing discharge current, enabling the discharge speed of the match line to be fast, further enabling the evaluation speed of the match line to be fast, improving the efficiency of searching operation, and further improving the working frequency and performance of the three-state content addressing memory.
The time point (timing at which the negative pressure control signal line is turned to a high level) at which the negative pressure is turned on during the evaluation of the match line can be adjusted.
The second metal wire and the first metal wire form a coupling capacitor, and the size of the coupling capacitor is determined by the length of the metal wire and can be changed along with the length of the first metal wire. The use of metal line capacitors does not add additional area.
The traditional MOS capacitor not only occupies extra area, but also reduces the negative voltage effect along with the length increase of the matching line. The negative pressure effect of the invention can be accurately regulated, and the effect can not be reduced because the matching line is lengthened.
The scheme of the invention is applicable to all NOR-type CAMs.
The traditional NOR-type architecture goes through a 2-stage NMOS transistor (i.e., a 2-stage NMOS transistor of a discharge circuit) from the match line to ground. The new architecture of the present invention adds a level one NMOS (zeroth NMOS) transistor, and the leakage current from the match line to ground is reduced due to the MOS stack effect.
Drawings
Fig. 1 is a schematic diagram of the present invention.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings and examples. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
The invention provides a ternary content addressable memory, which comprises a match line connected with a TCAM unit, wherein a comparison unit is arranged in the TCAM unit; the comparison unit is provided with a discharge circuit for discharging the matching line, and the discharge circuit is provided with a 2-level NMOS tube; the matching line is connected with a negative-pressure circuit through a discharge circuit;
The negative pressure circuit includes: a first metal wire connected with the discharge circuit, and a negative pressure control unit connected with the first metal wire;
The negative pressure control unit presets the first metal wire to be low level before the evaluation of the matching wire;
The negative pressure control unit is used for setting the first metal wire as negative pressure in the matching wire evaluation process; after the first metal wire is set to be negative pressure, VGS voltage of NMOS tube in the discharge circuit can be increased, so that discharge current can be increased, discharge speed of the matching line can be increased, evaluation speed of the matching line can be increased, searching operation efficiency is improved, and working frequency and performance of the ternary content addressing memory are improved.
Specific embodiments of the invention are as follows:
As shown in fig. 1, a ternary content addressable memory comprising: a match line ML and search lines SL0 to SLn and SLB0 to SLBn connected to the TCAM cell, a sense amplifier SA connected to the match line ML, and a first PMOS transistor P1 controlled by an evaluation enable signal CMPEN; the source electrode of the first PMOS tube P1 is connected with a power supply, the drain electrode of the first PMOS tube P1 is connected with a matching line ML, and the grid electrode of the first PMOS tube P1 is controlled by an evaluation enabling signal CMPEN; the TCAM unit is provided with a comparison unit and 2 SRAM units; the comparison unit is provided with a discharge circuit for discharging the match line ML, and the discharge circuit is provided with a 2-level NMOS tube; one NMOS tube in the 2-level NMOS tube is controlled by a storage node of a single SRAM unit, and the other NMOS tube in the 2-level NMOS tube is controlled by a single search line;
The matching line ML is connected with a negative voltage circuit through a discharging circuit (namely, the matching line ML is connected with the negative voltage circuit through a 2-level NMOS tube); the negative pressure circuit includes: the negative pressure control signal line NEN, the inverter DN1, the zeroth NMOS tube N0, a first metal line MLS1 connected with the discharge circuit and a second metal line MLS2 forming a coupling capacitor with the first metal line MLS 1; the negative pressure control signal line NEN is connected with the input end of the inverter DN 1; the output end of the inverter DN1 is connected with the second metal line MLS2, and the output end of the inverter DN1 is also connected with the grid electrode of the zeroth NMOS tube N0; the drain electrode of the zeroth NMOS tube N0 is connected with the first metal line MLS1, and the source electrode of the zeroth NMOS tube N0 is grounded.
Preferably, the second metal line MLS2 is parallel to the first metal line MLS1, and the second metal line MLS2 is equal in length to the first metal line MLS 1.
The control method of the negative pressure circuit comprises the following steps:
In the initial state, the evaluation enable signal CMPEN and the negative pressure control signal line NEN are both low level; at this time, the first PMOS transistor P1 is turned on, the second metal line MLS2 is set to a high level by the inverter DN1, and the zeroth NMOS transistor N0 is turned on; the matching line ML is connected with a power supply through a first PMOS tube P1, and the voltage of the matching line ML is precharged to a high level (VDD); the first metal line MLS1 is grounded through a zeroth NMOS tube N0, and the first metal line MLS1 is preset to be at a low level;
When searching is needed, before the search lines SL0 to SLn and SLB0 to SLBn are started, the evaluation enabling signal CMPEN is turned to a high level, so that the first PMOS tube P1 is cut off; after the search lines SL0 to SLn and SLB0 to SLBn are started for a certain time, the negative pressure control signal line NEN is turned to be high level, the second metal line MLS2 is turned to be low level, the zeroth NMOS tube N0 is cut off (after the search line is started, the matching evaluation process is started, the matching line ML discharges to the ground through a discharge circuit of a non-matching TCAM unit and the conducted zeroth NMOS tube N0, after a certain time, the zeroth NMOS tube N0 is cut off, and the matching line ML is pulled down to approximately the value of VDD); since the second metal line MLS2 and the first metal line MLS1 form a coupling capacitor, the second metal line MLS2 at a low level pulls down the voltage of the first metal line MLS1 at a low level through the coupling capacitor, and pulls down the first metal line MLS1 to a negative voltage lower than the ground voltage; after the first metal line MLS1 is pulled down to be negative voltage, VGS voltage of an NMOS tube in a discharge circuit can be increased, so that discharge current can be increased, the discharge speed of the matching line ML can be increased, and the evaluation speed of the matching line ML can be increased;
and restoring the initial state after the search is completed.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that it will be apparent to those skilled in the art that several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the scope of the invention.
Claims (6)
1. A ternary content addressing memory comprises a match line connected with a TCAM unit, wherein a comparison unit is arranged in the TCAM unit; the comparison unit is provided with a discharge circuit for discharging the matching line, and the discharge circuit is provided with a 2-level NMOS tube; the device is characterized in that the matching line is connected with a negative-pressure circuit through a discharge circuit;
The negative pressure circuit includes: a first metal wire connected with the discharge circuit, and a negative pressure control unit connected with the first metal wire;
The negative pressure control unit includes: the negative pressure control signal line, the inverter, the zeroth NMOS tube and the second metal line which forms a coupling capacitor with the first metal line; the negative pressure control signal line is connected with the input end of the phase inverter; the output end of the inverter is connected with the second metal wire, and the output end of the inverter is also connected with the grid electrode of the zeroth NMOS tube; the drain electrode of the zeroth NMOS tube is connected with the first metal wire, and the source electrode of the zeroth NMOS tube is grounded;
The negative pressure control unit sets the first metal wire to negative pressure during the evaluation of the match line.
2. The ternary content addressable memory of claim 1, wherein the negative pressure control unit presets the first metal line to a low level prior to evaluation of the match line.
3. The ternary content addressable memory of claim 2, wherein the match line is further configured with a first PMOS transistor controlled by an evaluate enable signal; the source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with a matching line, and the grid electrode of the first PMOS tube is controlled by an evaluation enabling signal.
4. A ternary content addressable memory according to claim 3, wherein the negative pressure circuit is controlled by:
In the initial state, the evaluation enabling signal and the negative pressure control signal line are all low level; at this time, the first PMOS transistor is turned on, the second metal line is set to a high level, and the zeroth NMOS transistor is turned on; the match line is connected with a power supply through a first PMOS tube, and the voltage of the match line is precharged to a high level; the first metal wire is grounded through a zeroth NMOS (N-channel metal oxide semiconductor) and preset to be at a low level;
When searching is needed, turning an evaluation enabling signal to be high level before a search line is started, and cutting off a first PMOS tube; after the search line is started for a certain time, the negative pressure control signal line is turned to be high level, so that the second metal line is turned to be low level, and the zeroth NMOS tube is cut off; the second metal wire pulls down the voltage of the first metal wire through the coupling capacitor, and the first metal wire is set to be negative pressure;
and restoring the initial state after the search is completed.
5. The ternary content addressable memory of claim 2, wherein the second metal line is parallel to the first metal line.
6. The ternary content addressable memory of claim 5, wherein the second metal line is of equal length as the first metal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210029995.9A CN114360605B (en) | 2022-01-12 | 2022-01-12 | Ternary content addressing memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210029995.9A CN114360605B (en) | 2022-01-12 | 2022-01-12 | Ternary content addressing memory |
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| Publication Number | Publication Date |
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| CN114360605A CN114360605A (en) | 2022-04-15 |
| CN114360605B true CN114360605B (en) | 2024-07-12 |
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Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331942B1 (en) * | 2000-09-09 | 2001-12-18 | Tality, L.P. | Content addressable memory cell and design methodology utilizing grounding circuitry |
| US6822886B2 (en) * | 2001-09-24 | 2004-11-23 | Micron Technology, Inc. | Reducing signal swing in a match detection circuit |
| US10714181B2 (en) * | 2016-11-30 | 2020-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory cell |
| KR102367338B1 (en) * | 2017-09-11 | 2022-02-25 | 삼성전자주식회사 | A tcam device and an operating method thereof |
| US10937475B1 (en) * | 2019-10-24 | 2021-03-02 | Renesas Elelctronics Corporation | Content addressable memory |
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- 2022-01-12 CN CN202210029995.9A patent/CN114360605B/en active Active
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| CN114360605A (en) | 2022-04-15 |
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