CN114360424B

CN114360424B - Signal processing circuit, display device and signal processing method

Info

Publication number: CN114360424B
Application number: CN202111670287.5A
Authority: CN
Inventors: 杜含笑; 请求不公布姓名; 林森
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2023-11-03
Anticipated expiration: 2041-12-31
Also published as: CN114360424A

Abstract

The embodiment of the application provides a signal processing circuit, a display device and a signal processing method. The signal processing circuit includes: a first switching unit and a charge sampling conversion unit; the first end and the second end of the first switch unit are respectively used for receiving a first voltage and an excitation voltage signal, and the first voltage is obtained based on electric charges generated by sensing biological signals; and the charge sampling conversion unit is used for correspondingly outputting a first group of differential signals from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage when the excitation voltage signal is at a first level, and the first end and the third end of the first switch unit are communicated with the second end and the fourth end of the first switch unit. The embodiment of the application can sample twice in one excitation voltage period, reduces low-frequency noise in the sampled data, improves the accuracy of the sampled data, and reduces the power consumption or area required by a signal processing circuit by multiplexing the charge sampling conversion unit.

Description

Signal processing circuit, display device and signal processing method

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a signal processing circuit, a display device, and a signal processing method.

Background

In a display device, a signal processing circuit mainly includes a charge amplifier, an integrator, a sampling circuit, an analog-to-digital converter, etc., and these circuits or modules are single-ended output or unidirectional amplification. At present, the signal processing circuit only samples once in a signal of one period, so that low-frequency noise in sampled data is larger, and the accuracy of the sampled data is reduced.

Meanwhile, the existing signal processing circuit needs to be realized by adopting two sampling and holding amplifiers, but the sampling capacitor and the holding capacitor need larger area, so that the problem of larger power consumption and larger area is often brought, and the application condition with higher requirements on the power consumption and the area is not suitable.

Disclosure of Invention

Aiming at the defects of the prior art, the application provides a signal processing circuit, a display device and a signal processing method, which are used for solving the technical problems that the signal processing circuit samples only once in a signal of one period in the prior art, so that low-frequency noise in sampled data is larger, the accuracy of the sampled data is reduced, or the arbitrary power consumption and the area of the signal processing circuit are larger.

In a first aspect, an embodiment of the present application provides a signal processing circuit, including: a first switching unit and a charge sampling conversion unit;

The first end and the second end of the first switch unit are respectively used for receiving a first voltage and an excitation voltage signal, and the third end and the fourth end of the first switch unit are respectively and electrically connected with the reverse input end and the forward input end of the charge sampling conversion unit; the first voltage is derived based on the charge generated by sensing the biological signal;

the charge sampling conversion unit is used for correspondingly outputting a first group of differential signals from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage when the excitation voltage signal is at a first level and the first end and the second end of the first switch unit are communicated with the fourth end; when the excitation voltage signal is at a second level, the first end and the fourth end of the first switch unit and the second end and the third end are conducted, a second group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage.

In one possible implementation, the signal processing circuit further includes:

the control unit is electrically connected with the first switch unit and is used for controlling the first end and the third end of the first switch unit and the second end and the fourth end to be conducted when the excitation voltage signal is at a first level; when the exciting voltage signal is at the second level, the first end and the fourth end of the first switch unit are controlled to be conducted, and the second end and the third end are controlled to be conducted.

In one possible implementation, the first switching unit includes a first control switch, a second control switch, a third control switch, and a fourth control switch;

the first end of the first control switch and the first end of the third control switch are used as the second end of the first switch unit together;

the second end of the first control switch and the second end of the second control switch are used as a third end of the first switch unit together;

the first end of the second control switch and the first end of the fourth control switch are used as the first end of the first switch unit together;

the second end of the third control switch and the second end of the fourth control switch are used as the fourth end of the first switch unit together;

the control unit is electrically connected with the control ends of the first control switch, the second control switch, the third control switch and the fourth control switch and used for controlling the connection and disconnection of the first control switch, the second control switch, the third control switch and the fourth control switch.

In one possible implementation, the charge sampling conversion unit includes: the differential charge amplifier, the first reset module and the second reset module;

the differential charge amplifier comprises a forward input end, a reverse input end, a first output end and a second output end which are respectively used as the forward input end, the reverse input end, the first output end and the second output end of a charge sampling conversion unit;

The first end and the second end of the first reset module are respectively and electrically connected with the reverse input end and the first output end of the differential charge amplifier;

the first end and the second end of the second reset module are respectively and electrically connected with the positive input end and the second output end of the differential charge amplifier;

the first reset module comprises a first reset capacitor and a first reset switch, and a first end of the first reset capacitor and a first end of the first reset switch are used as a first end of the first reset module together; the second end of the first reset capacitor and the second end of the first reset switch are used as the second end of the first reset module together;

the second reset module comprises a second reset capacitor and a second reset switch, and the first end of the second reset capacitor and the first end of the second reset switch are used as the first end of the second reset module together; the second end of the second reset capacitor and the second end of the second reset switch are used as the second end of the second reset module together;

the control unit is electrically connected with the first reset switch and the second reset switch and is used for controlling the on and off of the first reset switch and the second reset switch.

In one possible implementation, the signal processing circuit further includes: a denoising capacitor;

The first end of the denoising capacitor is electrically connected with the reverse input end of the charge sampling conversion unit;

the second terminal of the denoising capacitor is used for receiving the excitation voltage signal.

In one possible implementation, the signal processing circuit further includes: a common mode level feedback unit and an operational amplifier;

the first input end and the second input end of the common mode level feedback unit are respectively and electrically connected with the first output end and the second output end of the charge sampling conversion unit; the output end of the common mode level feedback unit is electrically connected with the input end of the operational amplifier;

a common mode level feedback unit for outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage and a gate bias voltage; the set of differential signals comprises a first set of differential signals or a second set of differential signals, and the grid bias voltage is the grid bias voltage of a switching device connected with the input end of the operational amplifier.

In one possible implementation manner, the operational amplifier is configured to correspondingly output a third set of differential signals or a fourth set of differential signals from the first output end and the second output end of the operational amplifier based on the common mode level feedback signal; the average value of the differential signals of the third group of differential signals is a preset common mode voltage; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

In one possible implementation, the common mode level feedback unit includes: a first common mode level feedback sub-circuit;

the first common mode level feedback sub-circuit comprises a fifth control switch, a sixth control switch, a seventh control switch, an eighth control switch, a first capacitor and a second capacitor;

the first end of the fifth control switch, the first end of the sixth control switch and the first end of the seventh control switch are respectively used for receiving a preset common mode voltage, a grid bias voltage and one differential signal in a group of differential signals;

the second end of the fifth control switch and the second end of the seventh control switch are electrically connected with the first end of the first capacitor; the second end of the sixth control switch and the second end of the eighth control switch are electrically connected with the second end of the first capacitor;

the first end of the second capacitor is electrically connected with the first end of the seventh control switch, and the second end of the second capacitor is electrically connected with the first end of the eighth control switch and the output end of the common mode level feedback unit.

In one possible implementation, the common mode level feedback unit further includes: a second common mode level feedback sub-circuit;

the second common mode level feedback sub-circuit comprises a ninth control switch, a tenth control switch, an eleventh control switch, a twelfth control switch, a third capacitor and a fourth capacitor;

A first end of the ninth control switch, a first end of the tenth control switch, and a first end of the eleventh control switch are respectively configured to receive a predetermined common mode voltage, a gate bias voltage, and another differential signal of a set of differential signals;

the second end of the ninth control switch and the second end of the eleventh control switch are electrically connected with the first end of the fourth capacitor; the second end of the tenth control switch and the second end of the twelfth control switch are electrically connected with the second end of the fourth capacitor;

the first end of the third capacitor is electrically connected with the first end of the eleventh control switch, and the second end of the third capacitor is electrically connected with the first end of the twelfth control switch and the output end of the common mode level feedback unit.

In one possible implementation, the signal processing circuit further includes: a signal conversion unit;

the first input end and the second input end of the signal conversion unit are respectively used for being electrically connected with the first output end and the second output end of the charge sampling conversion unit;

and the signal conversion unit is used for comparing the third group of differential signals or the fourth group of differential signals to obtain a comparison result and converting the comparison result into a digital signal.

In a second aspect, an embodiment of the present application provides a display apparatus, including: a display panel and a signal processing circuit as in the first aspect;

The display panel comprises a plurality of touch electrodes, and the touch electrodes are electrically connected with the first end of the first switch unit.

In a third aspect, an embodiment of the present application provides a signal processing method, applied to the signal processing circuit of the first aspect, including:

in the first charge sampling conversion stage, when the excitation voltage signal is at a first level, when the excitation voltage signal is at the first level, the first end and the third end of the first switch unit are controlled to be conducted, and the second end and the fourth end of the first switch unit are controlled to be conducted, so that a first group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage;

in the second charge sampling conversion stage, when the excitation voltage signal is at a second level, the first end and the fourth end of the first switch unit are controlled to be conducted, and the second end and the third end of the first switch unit are controlled to be conducted, so that a second group of differential signals are correspondingly output from the first output end and the second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage.

In one possible implementation, controlling the first terminal and the third terminal of the first switching unit and the second terminal and the fourth terminal to be conductive includes:

the second control switch and the third control switch of the first switch unit are controlled to be on, and the first control switch and the fourth control switch of the first switch unit are controlled to be off;

Controlling the first end and the fourth end of the first switch unit and the second end and the third end to be conducted comprises:

the second control switch and the third control switch of the first switch unit are both turned off, and the first control switch and the fourth control switch of the first switch unit are both turned on.

In one possible implementation, the signal processing method further includes:

outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage, and a gate bias voltage; the group of differential signals comprises a first group of differential signals or a second group of differential signals, and the grid bias voltage is the grid bias voltage of a switching device connected with the input end of the operational amplifier;

outputting a third group of differential signals or a fourth group of differential signals correspondingly from a first output end and a second output end of the operational amplifier based on the common mode level feedback signals; the average value of the differential signals of the third group of differential signals is a preset common mode voltage; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

The technical scheme provided by the embodiment of the application has the beneficial technical effects that:

the signal processing circuit of the embodiment of the application comprises a first switch unit and a charge sampling conversion unit, wherein when an excitation voltage signal is a first level, a first end and a third end of the first switch unit and a second end and a fourth end of the first switch unit are conducted, and the first voltage is converted into a first group of differential signals based on the excitation voltage signal to be sampled once; and when the excitation voltage signal is at a second level, the first end and the fourth end of the first switch unit are conducted, the second end and the third end of the first switch unit are conducted, and the first voltage is converted into a second group of differential signals based on the excitation voltage signal to carry out second sampling. Therefore, the embodiment of the application can realize the multiplexing of the charge sampling conversion unit twice through the conduction of different ends of the first switch unit, can sample twice in one excitation voltage period, generates two groups of differential signals, is convenient for subsequent processing, greatly reduces low-frequency noise in sampled data, improves the accuracy of the sampled data, and is convenient for subsequent flexible signal processing.

Meanwhile, the embodiment of the application can directly adopt the charge sampling conversion unit, and an integrator and a sampling circuit adopted in the structure of the existing signal processing circuit are omitted, so that the power consumption or the area required by the signal processing circuit is greatly reduced.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram of a signal processing circuit according to an embodiment of the present application;

fig. 2 is a schematic diagram of another signal processing circuit according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a first switch unit and a charge sampling conversion unit of a signal processing circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a touch front end applied to a signal processing circuit according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a common mode level feedback unit of a signal processing circuit according to an embodiment of the present application;

Fig. 6 is a schematic diagram of an operational amplifier of a signal processing circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an application scenario of a signal processing circuit applied to a touch front end according to an embodiment of the present application

Fig. 8 is a flowchart of a signal processing method according to an embodiment of the present application.

Reference numerals:

1-a signal processing circuit;

10-first switch unit, 8-first control switch, 7-second control switch, 6-third control switch, 5-fourth control switch;

the device comprises a 20-charge sampling conversion unit, a 9-differential charge amplifier, a 21-first reset module, a 22-second reset module, a 10-first reset capacitor, a 11-first reset switch, a 12-second reset capacitor, a 13-second reset switch and a 4-denoising capacitor;

30-a control unit;

a 14-common mode level feedback unit;

141-fifth control switch, 142-sixth control switch, 143-seventh control switch, 144-eighth control switch, 145-ninth control switch, 146-tenth control switch, 147-eleventh control switch, 148-twelfth control switch;

17-signal conversion circuit, 171-analog-to-digital converter, 15-thirteenth control switch, 16-fourteenth control switch;

410-touch capacitance, 420-parasitic capacitance, 430-touch node

18-operational amplifier, 181-first current source module, 182-second current source module, 183-differential pair tube module, 184-floating current module, 185-first current mirror module, 186-second current mirror module.

Detailed Description

The present application is described in detail below, examples of embodiments of the application are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

The inventor of the present application studied and found that in a display device, a signal processing circuit mainly includes a charge amplifier, an integrator, a sampling circuit, an analog-to-digital converter, etc., and these circuits or modules are single-ended output or unidirectional amplification mode. When the existing signal processing circuit and the system framework thereof are adopted, the method is characterized in that analog data processing and integration are realized, the method is suitable for adopting a high-frequency analog-digital converter ADC, and digital filtering processing is difficult to be carried out on source data. Correlation double sampling is initially proposed in the technical field of photoelectric correlation, but no mature related technology application exists in a touch sampling system. A basic correlated double sampling specific example is provided before, and two sample and hold amplifiers are adopted to realize the method, but the sampling capacitor and the holding capacitor need larger area, so that although the matching performance of the method is good, the power consumption and the area are larger, and the method is not applicable to application conditions with higher requirements on the power consumption and the area.

The application provides a signal processing circuit, a display device and a signal processing method, which aim to solve the technical problems in the prior art.

The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments.

An embodiment of the present application provides a signal processing circuit, referring to fig. 1, the signal processing circuit 1 includes: a first switching unit 10 and a charge sampling conversion unit 20.

The first end and the second end of the first switch unit 10 are respectively used for receiving a first voltage and an excitation voltage signal, and the third end and the fourth end of the first switch unit 10 are respectively electrically connected with the reverse input end and the forward input end of the charge sampling conversion unit 20; the first voltage is derived based on the charge generated by sensing the biological signal.

The charge sampling conversion unit 20 is configured to, when the excitation voltage signal is at a first level, output a first set of differential signals from a first output terminal and a second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage when the first terminal and the third terminal of the first switch unit 10 and the second terminal and the fourth terminal of the first switch unit 10 are turned on; when the excitation voltage signal is at the second level, the first end and the fourth end of the first switch unit 10 and the second end and the third end of the first switch unit 10 are turned on, a second set of differential signals is correspondingly output from the first output end and the second output end of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the first set of differential signals comprises two differential signals; the second set of differential signals includes two differential signals. The charge sampling conversion unit 20 samples and converts the first voltage based on the principle of a charge amplifier to obtain a differential signal representing the first voltage information.

Optionally, the first level of the embodiment of the present application is lower than the second level, i.e. the first level is a low level and the second level is a high level. Similarly, the principle that the terminals of the first switch unit 10 are turned on is the same as that the first level is high and the second level is low.

Alternatively, the biological signal is a signal related to the body of the living being, which may be an autonomous signal that the user subconsciously controls, for example: the finger contacts the touch screen; the biological signal may also be a signal generated by a user from an autonomous body function, such as: including at least one of an electrocardiogram signal, an electroencephalogram signal, an electromyogram signal, an electrooculogram signal, a picopotential, or any other suitable type of bioelectric signal.

Alternatively, the first voltage may be obtained corresponding to the output charge C received by the touch electrode of the display panel, so as to convert the charge C into a voltage signal.

The embodiment of the application can realize the multiplexing of the charge sampling conversion unit twice by conducting different ends of the first switch unit 10, can sample twice in one excitation voltage period, and generates two groups of differential signals, thereby greatly reducing low-frequency noise in sampled data, improving the accuracy of the sampled data and being convenient for the subsequent flexible signal processing.

Meanwhile, the embodiment of the application can directly adopt the charge sampling conversion unit 20, so that an integrator and a sampling circuit adopted in the structure of the existing signal processing circuit are omitted, and the power consumption or the area required by the signal processing circuit is greatly reduced.

In the embodiment of the present application, in a period of an excitation voltage signal, the charge sampling conversion unit 20 is secondarily multiplexed by different combinations of controlling the switch to be turned off and turned on, including but not limited to the change of the switch combination logic control, which is all within the scope of protection of the present patent.

In some embodiments, referring to fig. 2, the signal processing circuit 1 further comprises: and a control unit 30.

The control unit 30 is electrically connected to the first switch unit 10, and the control unit 30 is configured to control the first end and the third end of the first switch unit 10 and the second end and the fourth end to be conducted when the excitation voltage signal is at a first level; when the excitation voltage signal is at the second level, the first terminal and the fourth terminal of the first switch unit 10 are controlled to be conducted, and the second terminal and the third terminal are controlled to be conducted.

Optionally, the first switch unit 10 is a combination of a plurality of control switches, and the different ends of the first switch unit 10 are turned on by controlling the form that the partial control switches are turned off and the partial control switches are turned on, so that the corresponding signals are input into the charge sampling conversion unit 20.

In some embodiments, referring to fig. 3, the first switching unit 10 includes a first control switch 8, a second control switch 7, a third control switch 6, and a fourth control switch 5.

The first end of the first control switch 8 and the first end of the third control switch 6 together serve as the second end of the first switch unit 10.

The second terminal of the first control switch 8 and the second terminal of the second control switch 7 together serve as a third terminal of the first switching unit 10.

The first end of the second control switch 7 and the first end of the fourth control switch 5 together serve as the first end of the first switch unit 10.

The second terminal of the third control switch 6 and the second terminal of the fourth control switch 5 together serve as the fourth terminal of the first switching unit 10.

The control unit 30 is electrically connected with the control ends of the first control switch 8, the second control switch 7, the third control switch 6 and the fourth control switch 5, and is used for controlling the on and off of the first control switch 8, the second control switch 7, the third control switch 6 and the fourth control switch 5.

Alternatively, the control unit 30 controls the conduction of the different terminals of the first switching unit 10 based on the excitation voltage signal and the sampling signal. The sampling signal is a signal that triggers the charge sampling conversion unit 20 to sample the signal of the first voltage.

Alternatively, the control unit 30 may be a logic control circuit that receives the excitation voltage signal and the sampling signal and outputs a control signal to the respective control switches of the first switching unit 10 according to the received excitation voltage signal and sampling signal. The person skilled in the art can select the signal connected to the input terminal of the control unit 30 according to the actual design, so that the control signal output by the control unit 30 can meet the above conditions.

Alternatively, the control terminals of the control switches in the embodiments of the present application may be electrically connected to the control unit 30, and the on/off of each control switch is controlled by the control timing of the control unit 30.

Alternatively, the first switching unit 10 may include only two control switches, and one control switch may control two paths. For example, one end of one control switch is electrically connected to the positive input terminal of the charge sampling conversion unit 20, and the other end may be electrically connected to the first end or the second end of the first switching unit 10; one end of a control switch is electrically connected to the inverting input terminal of the charge sampling conversion unit 20, and the other end may be electrically connected to the first end or the second end of the first switching unit 10.

Alternatively, as shown in fig. 3, vex represents the excitation voltage signal, high represents a High level (corresponding to the second level), and LOW represents a LOW level (corresponding to the first level). The excitation voltage signal Vex is a rectangular wave signal having a high-low level. V (V) _OP Representing the signal output by the first output terminal of the charge sampling conversion unit 20, V _ON Representing the signal output by the second output terminal of the charge sampling conversion unit 20, V _OP And V _ON A set of differential signals is formed. When the excitation voltage signal is at a first level, the output group of differential signals is a first group of differential signals; when the excitation voltage signal is at the second level, the output set of differential signals is the second set of differential signals.

Referring to fig. 3, when the exciting voltage signal Vex is at a low level in one period, the second control switch 7 and the third control switch 6 are turned on, the first control switch 8 and the fourth control switch 5 are turned off, the exciting voltage signal Vex is connected to the positive input terminal of the charge sampling conversion unit 20, and the first voltage V _I The signal is connected to the inverting input of the charge sampling conversion unit 20. Because the exciting voltage signal Vex is low at this time and is connected to the positive input terminal of the charge sampling conversion unit 20, V is generated _OP Greater than V _ON I.e. a first set of differential signal outputs.

Conversely, when the exciting voltage signal Vex is at a high level in one period, the second control switch 7 and the third control switch 6 of the switch component are turned off, the first control switch 8 and the fourth control switch 5 are turned on, the exciting voltage signal Vex is connected to the inverting input terminal of the charge sampling conversion unit 20, and the first voltage V _I The signal is connected to the positive input of the charge sampling conversion unit 20. Because the exciting voltage signal Vex is at high level and is connected to the inverting input terminal of the charge sampling conversion unit 20, V is generated _OP Less than V _ON I.e. a second set of differential signal outputs.

In some embodiments, referring to fig. 3, the charge sampling conversion unit 20 includes: a differential charge amplifier 9, a first reset module 21 and a second reset module 22.

The positive input terminal, the negative input terminal, the first output terminal, and the second output terminal of the differential charge amplifier 9 are respectively used as the positive input terminal, the negative input terminal, the first output terminal, and the second output terminal of the charge sampling conversion unit 20.

The first and second ends of the first reset module 21 are electrically connected to the inverting input terminal and the first output terminal of the differential charge amplifier 9, respectively.

The first end and the second end of the second reset module 22 are respectively electrically connected with the positive input end and the second output end of the differential charge amplifier 9.

The first reset module 21 comprises a first reset capacitor 10 and a first reset switch 11, and a first end of the first reset capacitor 10 and a first end of the first reset switch 11 are used as a first end of the first reset module 21 together; the second terminal of the first reset capacitor 10 and the second terminal of the first reset switch 11 together serve as the second terminal of the first reset module 21.

The second reset module 22 includes a second reset capacitor 12 and a second reset switch 13, where a first end of the second reset capacitor 12 and a first end of the second reset switch 13 are used together as a first end of the second reset module 22; the second terminal of the second reset capacitor 12 and the second terminal of the second reset switch 13 together serve as the second terminal of the second reset module 22.

The control unit 30 is electrically connected to the first reset switch 11 and the second reset switch 13, and is used for controlling the on and off of the first reset switch 11 and the second reset switch 13.

Alternatively, referring to fig. 3, CA denotes a differential charge amplifier 9, cfb1 denotes a first reset capacitor 10, cfb2 denotes a second reset capacitor 12, reset1 denotes a first reset switch 11, and reset2 denotes a second reset switch 13.

Optionally, a first voltage V _I The signal is connected to the positive and negative inputs of the differential charge amplifier 9 via the fourth control switch 5 and the second control switch 7, respectively, the positive and negative inputs of the differential charge amplifier 9The input end is connected with the exciting voltage signal Vex through the third control switch 6 and the first control switch 8. The inverting input of the differential charge amplifier 9 and the differential signal V _OP A capacitor Cfb1 and a reset switch reset1 are connected between the positive input end of the differential charge amplifier 9 and the differential signal V _ON The capacitor Cfb2 and the reset switch reset2 are connected therebetween. First voltage V _I The function realized to the output section of the differential charge amplifier 9 is to convert the charge into a voltage, realizing the generation of the detection signal.

Referring to fig. 3, when the exciting voltage signal Vex is in a low level stage in one period, a first charge sampling process is performed, since both ends of the differential charge amplifier 9 are inputted with the low level of the exciting voltage signal Vex, after the first reset switch 11 and the second reset switch 13 are reset, the capacitor Cfb2 acts on the forward input end and the second output end of the differential charge amplifier 9, and the second reset switch 13 is turned on, the charge on the capacitor Cfb2 is 0, and when the second reset switch 13 is turned off, a voltage difference exists between the reverse input end and the forward input end of the differential charge amplifier 9, and after the differential charge amplifier 9 amplifies, V is obtained _OP And V _ON Is a signal of (a). Because the exciting voltage signal Vex is low and connected to the positive input terminal, V is generated _OP Greater than V _ON Is provided. In contrast, when the excitation voltage signal Vex is in the high level stage in one period, the second charge sampling process is performed, similarly to the principle of the first charge sampling process. Because the exciting voltage signal Vex is at high level and connected to the inverting input terminal, V is generated _OP Less than V _ON Is provided.

Alternatively, as shown in FIG. 4, as an example, a first voltage V _I The first end of the first switch unit 10 is electrically connected to a touch output end of a touch front end structure, and the touch front end structure comprises a touch capacitor 410, a parasitic capacitor 420 and a touch node 430. In fig. 4, cf represents the touch capacitance 410, and cp represents the parasitic capacitance 420. The touch screen generates a touch capacitance Cf from the touch node 430 to ground when touched by a finger, and because the electronic device inevitably existsThe parasitic capacitance Cp refers to the sum of parasitic capacitances of the touch node 430 to the signal line, such as a Gate (Gate) line or a Data (Data) line, and to other touch nodes. In practical application, the voltage V output by the touch output end can be _I The charge C generated by the touch is considered.

Alternatively, the capacitance of the touch detection is mainly the capacitance of the touch node to the ground, as shown in fig. 3 and 4, that is, the capacitance of the touch detection is mainly the touch capacitance Cf, which is not large, and if the parasitic capacitance Cp is added, the total amount of the finally detected charges C becomes large, thereby causing a touch detection error.

Based on the above analysis, in some embodiments, the signal processing circuit 1 further comprises: and a denoising capacitor 4.

The first end of the denoising capacitor 4 is electrically connected with the reverse input end of the charge sampling conversion unit 20;

a second terminal of the denoising capacitor 4 is used for receiving the excitation voltage signal.

Optionally, the excitation voltage Signal Vex is also called a Guard Signal (Guard Signal) and is used to effectively eliminate the negative effect of parasitic capacitance on the touch capacitance.

Referring to fig. 3, ccencocle represents the denoising capacitor 4, vcancle represents the voltage signal received at the second terminal of the denoising capacitor 4, and Vcancle may be the excitation voltage signal Vex.

The embodiment of the application sets the excitation voltage signal V of the denoising capacitor 4 (namely the capacitor Ccancle) _EX The terminal can effectively eliminate the influence on the size of the touch capacitor Cf caused by the parasitic capacitor Cp, thereby reducing the touch detection error.

The first reset capacitor 10, the second reset capacitor 12 and the denoising capacitor 4 in the embodiment of the present application can be adjusted in capacitance, so that when the capacitance is correspondingly changed, the output voltage amplitude of the charge sampling conversion unit 20 is correspondingly changed, and thus the output signals of the charge sampling conversion unit 20 and the signal processing circuit are dynamically adjustable.

In some embodiments, as shown in connection with fig. 5 and 6, the signal processing circuit 1 further comprises: a common mode level feedback unit 14 and an operational amplifier 18.

The first input end and the second input end of the common mode level feedback unit 14 are respectively and electrically connected with the first output end and the second output end of the charge sampling conversion unit 20; the output of the common mode level feedback unit 14 is electrically connected to the input of an operational amplifier 18.

A common mode level feedback unit 14 for outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage and a gate bias voltage; the set of differential signals includes a first set of differential signals or a second set of differential signals, and the gate bias voltage is the gate bias voltage of a switching device connected to the input of the operational amplifier 18.

In some embodiments, referring to fig. 5, the common mode level feedback unit 14 includes: a first common mode level feedback sub-circuit.

The first common mode level feedback sub-circuit includes a fifth control switch 141, a sixth control switch 142, a seventh control switch 143, an eighth control switch 144, a first capacitance, and a second capacitance.

The first terminal of the fifth control switch 141, the first terminal of the sixth control switch 142, and the first terminal of the seventh control switch 143 are respectively configured to receive a predetermined common mode voltage, a gate bias voltage, and one differential signal of a set of differential signals.

The second end of the fifth control switch 141 and the second end of the seventh control switch 143 are electrically connected to the first end of the first capacitor; the second terminal of the sixth control switch 142 and the second terminal of the eighth control switch 144 are electrically connected to the second terminal of the first capacitor.

The first end of the second capacitor is electrically connected to the first end of the seventh control switch 143, and the second end of the second capacitor is electrically connected to the first end of the eighth control switch 144 and the output end of the common mode level feedback unit 14.

Optionally, the predetermined common mode voltage is an input common mode level of the subsequent analog-to-digital converter ADC.

In some embodiments, referring to fig. 5, the common mode level feedback unit 14 further includes: a second common mode level feedback sub-circuit.

The second common mode level feedback sub-circuit includes a ninth control switch 145, a tenth control switch 146, an eleventh control switch 147, a twelfth control switch 148, a third capacitance, and a fourth capacitance.

A first terminal of the ninth control switch 145, a first terminal of the tenth control switch 146, and a first terminal of the eleventh control switch 147 are respectively configured to receive a predetermined common mode voltage, a gate bias voltage, and another differential signal of the set of differential signals.

A second end of the ninth control switch 145 and a second end of the eleventh control switch 147 are electrically connected with the first end of the fourth capacitor; a second terminal of the tenth control switch 146, a second terminal of the twelfth control switch 148, and a second terminal of the fourth capacitor are all electrically connected.

The first end of the third capacitor is electrically connected to the first end of the eleventh control switch 147, and the second end of the third capacitor is electrically connected to the first end of the twelfth control switch 148 and the output end of the common mode level feedback unit 14.

Alternatively, as shown in fig. 5, VCM represents a predetermined common mode voltage, VBN1 represents a gate bias voltage, VOP1 (i.e., one differential signal corresponding to the output of the differential charge amplifier 9) represents one differential signal of a set of differential signals, VON1 represents one differential signal of a set of differential signals, i.e., another differential signal corresponding to the output of the differential charge amplifier 9, and VCMFB represents a common mode level feedback signal. The capacitor C1, the capacitor C2, the capacitor C3, and the capacitor C4 are a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, respectively.

Alternatively, as shown in fig. 5, VOP1 and VON1 are input signals to the common mode level feedback unit 14, and are connected to the output signal VCMFB through symmetrical capacitances. VCM is the input common mode level of the subsequent analog-to-digital converter ADC, i.e., the predetermined common mode voltage of embodiments of the present application. VBN1 is a gate bias voltage (bias voltage corresponding to gates of MN7 and MN8 in fig. 7), and all voltage signal terminals and capacitors are connected through sixth control switch 142, seventh control switch 143, eighth control switch 144, ninth control switch 145, tenth control switch 146, eleventh control switch 147, and twelfth control switch 148. In the phase phi 1, the fifth control switch 141 and the sixth control switch 142 are turned on, the ninth control switch 145 and the tenth control switch 146 are turned on, the lower plates of the two capacitors C1 and C4 are charged to the original bias voltage potential of VBN1, the upper plates of the two capacitors C1 and C4 are charged to the desired common mode level potential of VCM, and the VCM and bias voltage nodes are connected together in this phase. In the phase phi 2, i.e. the seventh control switch 143 and the eighth control switch 144 are turned on, the eleventh control switch 147 and the twelfth control switch 148 are turned on, the capacitor C1 is connected in parallel with the capacitor C2, the capacitor C3 is connected in parallel with the capacitor C4, and since the voltage on the capacitor cannot be suddenly changed, the voltage on the capacitor is basically unchanged provided that the phase period is sufficiently small. VBN1 is thus transferred to VCMFB, and VOP1 and VON2 are coupled to VCM via charged capacitors C1, C4 to obtain a common mode level feedback signal VCMFB, which is output to the input of op amp 18.

It should be appreciated by those skilled in the art that other common mode level feedback unit 14 techniques similar to those of the present embodiment or other techniques similar to those of the present patent principles, but in different implementations, are within the scope of the present patent.

In some embodiments, referring to fig. 6, the operational amplifier 18 is configured to output a third set of differential signals or a fourth set of differential signals from the first output terminal, the second output terminal, and the first output terminal of the operational amplifier 18, respectively, based on the common mode level feedback signal; the average value of the differential signals of the third group of differential signals is a preset common mode voltage; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

Optionally, referring to fig. 6, the first current source module 181 and the second current source module 182 are P-type current source and N-type current source respectively, and the first current source module 181 and the second current source module 182 may be in the form of Cascode amplifiers Cascode to provide current to the differential pair transistor module 183. The first current source module 181 is formed by connecting two PMOS transistors of MP3 and MP4 in series, the second current source module 182 is formed by connecting two NMOS transistors of MN3 and MN4 in series, and the differential pair tube module 183 includes MP1 and MN1, and MP2 and MN2.MP1 and MP2 source terminals are connected to the first current source module 181, MN1 and MN2 source terminals are connected to the second current source module 82, and when the input voltages INN and INP are low, the PMOS differential pair transistors are turned on, and the NMOS differential pair transistors are turned off or weakly turned on. When the input voltages INN and INP are both high, the NMOS differential pair is on and the PMOS differential pair is off or weakly on. The first current mirror module 185 and the second current mirror module 186 are respectively P-type and N-type cascoded current mirrors of cascoded amplifiers, and are used as loads of folded cascoded differential pair tubes. The floating current block 184 is a floating current portion, and the basic charge amplifier structure of the present embodiment has N-type and P-type input differential pair transistors, so that the common mode range of the input signal is very large, and can be from ground to power.

Alternatively, referring to fig. 6, the operational amplifier 18 according to the embodiment of the present application is a rail-to-rail operational amplifier basic example, and the first current source module 181 and the first current mirror module 185 are PMOS-configured cascode current mirrors, and provide a current load. The second current source module 182 and the second current mirror module 186 provide a current load for a cascode current mirror formed of NMOS. The gate terminal voltages of MP3 and MP4 are bias voltages VBP1 and VBP2, and MP5 and MP6 are common gates, the gate terminal voltages are bias voltages VBP3, MP7 and MP8 are common gates, and the gate terminal voltage is bias voltage VBP4. The gate voltages of MN3 and MN4 are bias voltages VBN2 and VBN1, MN5 and MN6 are common-gate, the gate voltages are bias voltages VBN3, MN7 and MN8 are common-gate, and the gate voltages are bias voltages VBN4. The differential pair tube module 183 is composed of two pairs of input pair tubes, MN1, MN2 and MP1, MP2, whose gate input voltages are INP, INN and INP, INN, respectively. MN1 and MN2 are common sources, and the source signal nvg is connected to the second current source module 182.MP1 and MP2 are commonly sourced, and a source signal pvg is coupled to the first current source module 181. The drain voltages p12, p11 of MN1, MN2 are connected to the drains of MP6, MP5, respectively. The drain voltages n12, n11 of MP1, MP2 are connected to the drains of MN8, MN7, respectively. A floating current module 184 is added between the first current mirror module 185 and the second current mirror module 186, and MP9, MN9, MP10, MN10 form a floating current, and the magnitude of the current is determined by the bias voltage input from the gate terminal. pmg, nmg are connected to the drain terminals of MP7, MN5, respectively, and pog, nog are connected to the drain terminals of MP8, MN6, respectively. The gates of the NMOS current mirror primary mirror MN7 and MN8 in the second current mirror module 186 are commonly used as the input of the operational amplifier 18 to receive the common mode level feedback signal VCMFB.

Alternatively, based on the circuit structures shown in fig. 5 and 6, the differential charge amplifier 9 adjusts the first differential signal set and the second differential signal set (corresponding to VON1 and VOP 1) based on the predetermined common mode level VCM, and then obtains the third differential signal set and the fourth differential signal set (corresponding to VON2 and VOP 2) for outputting for subsequent processing. The average value of the differential signals of the third group of differential signals is a predetermined common mode voltage VCM; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage VCM.

Alternatively, the operational amplifier 18 may be located within the charge sampling conversion unit 20.

In some embodiments, the signal processing circuit 1 further comprises: a signal conversion unit 17.

The first input terminal and the second input terminal of the signal conversion unit 17 are respectively electrically connected to the first output terminal and the second output terminal of the charge sampling conversion unit 20.

The signal conversion unit 17 is configured to compare the third set of differential signals or the fourth set of differential signals to obtain a comparison result, and convert the comparison result into a digital signal.

Optionally, the signal conversion unit 17 includes: a comparator and a converter.

The first input terminal and the second input terminal of the comparator are respectively used as the first input terminal and the second input terminal of the signal conversion circuit 17.

The output end of the comparator is electrically connected with the input end of the converter.

And the comparator is used for comparing the third group of differential signals or the fourth group of differential signals to obtain a comparison result and outputting the comparison result to the converter.

And a converter for converting the comparison result into a digital signal.

Consider that the signal processing circuits of the prior art are all single ended outputs, or unidirectional amplification. When the existing signal processing circuit and the system framework thereof are adopted, the method is characterized in that analog data processing and integration are realized, the method is suitable for adopting a high-frequency analog-digital converter, and the digital filtering processing of source data is difficult.

Based on the above problems existing in the prior art, the signal processing circuit of the present application performs two sampling in one excitation voltage period by using the charge sampling conversion unit 20, obtains two sets of sampling data after the analog-to-digital converter, and further filters, integrates and processes the source data by using the digital circuit, so as to effectively reduce the influence of the noise with medium and low frequency on the sampling data.

When the embodiment of the application adopts digital filtering, the area of a single analog-to-digital converter can be smaller, and the source data generated by the analog-to-digital converter can be very easily processed by the digital filtering to carry out algorithm processing, so that the application flexibility of the obtained data is higher, errors caused by deviation of the data can be obviously reduced, and the digital filtering can be well applied to a signal processing circuit with low speed requirement on the analog-to-digital converter, but small area and more flexible data is needed.

The signal processing circuit of the embodiment of the application can dynamically adjust the input voltage range, thereby greatly helping the performance of the analog-to-digital converter. When the performance of the analog-to-digital converter is deteriorated in some extreme cases, the amplitude of the input voltage range of the analog-to-digital converter is reduced, so that the actual conversion effective bit number of the analog-to-digital converter can be effectively improved. Moreover, the application of the double-sampling concept for realizing twice sampling in one excitation voltage period in the field of touch sampling can effectively filter noise with medium and low frequencies, and improve the noise immunity, stability, sensitivity and accuracy of the whole chip.

Alternatively, the functions of the comparator and the converter may be obtained by the design of the analog-to-digital converter ADC.

Optionally, the digital front-end unit includes a converter having a function of converting the comparison result into a digital signal. The converter is located in the digital front end unit. The comparison result output by the comparator is directly output to the digital front-end unit, and the digital front-end unit is used for converting the bit number. The digital front end unit may employ digital front end modules (Digital Front End, DFE).

Optionally, in the signal conversion circuit of the embodiment of the present application, after an input signal passes through the charge conversion circuit, the input signal is directly connected to the analog-to-digital converter ADC for analog-to-digital conversion without going through the function INT, and the converted digital signal is sent to the digital front end module DFE for digital integration processing and integration. The signal conversion circuit of the embodiment of the application is based on digital signal processing and integration, is easier to carry out digital filtering processing on source data, is suitable for being realized by adopting an analog-to-digital converter ADC, and has the defect of too many interactive signals between analog and digital.

Optionally, two groups of sampling data are obtained after the two groups of differential signals are subjected to analog-to-digital conversion, and the influence of middle-low frequency noise on the sampling data can be effectively reduced through further noise filtering, integration and processing of the digital circuit on the source data.

Those skilled in the art will appreciate that: the embodiment of the application can realize sampling twice in one period, so that two groups of data signals are obtained after the analog-digital converter, and the digital noise filtering mode can be used very flexibly. If an integral algorithm is adopted, averaging, weighted re-integration and the like are adopted, and high-pass filtering, low-pass filtering and the like can be adopted according to actual requirements, the noise influence can be effectively reduced, and the signal to noise ratio can be improved.

In some embodiments, the converter includes a plurality of digital signal outputs.

And the converter is used for converting the comparison result into a plurality of parallel digital signals with designed digits and outputting the digital signals through a plurality of digital signal output ends in a one-to-one correspondence manner.

Alternatively, since the signal processing circuit 1 of the present application does not perform integration processing, n analog-to-digital converters (Analog to Digital Converter, ADCs) are used for n touch nodes. Referring to fig. 7, the ADC has a plurality of digital signal output terminals, each ADC outputs 10 bits of data, and the total of the interaction signals becomes 10×n, which may cause too many interaction ports between the digital and analog circuits. The output of each converter becomes serial data, i.e. there is only 1 per converter output signal. The output of the comparator (serial data) can be directly input into the digital front-end unit, the serial data is converted into parallel data with 10 bit digits in the digital front-end unit, so that n digital signals of D9:0 can be reduced to n digital signals of D0, and the number of interaction signals is reduced by 10 times.

Optionally, the digital data generated by the analog-to-digital converter in the embodiment of the application can be freely selected in the digital front-end unit in a digital filtering mode, such as integrating in the figure, or performing averaging, weighted re-integration and the like, and the digital data generated by the analog-to-digital converter can be very easily processed through the digital filtering algorithm, so that the flexibility of the application of the obtained data is higher, and the error tolerance and error correction of the data, namely, the error of data deviation, can be obviously reduced.

Alternatively, referring to fig. 7, there is shown an application scenario of the signal processing circuit 1 and a specific structure of the signal processing circuit 1. The signal processing circuit 1 includes a first switching unit 10, a charge sampling conversion unit 20, a common mode level feedback unit 14, and a signal conversion circuit 17, which are electrically connected in this order. In fig. 7, CMFB denotes a common mode level feedback unit 14, adc denotes an analog-to-digital converter 171, and the signal conversion circuit 17 includes the analog-to-digital converter 171. The operational amplifier 18 is not shown, and may be located in the differential charge amplifier 9 of the charge sampling conversion unit 20, the first differential signal or the second differential signal output by the differential charge amplifier 9 is input to the common mode level feedback unit 14, the output end of the common mode level feedback unit 14 is electrically connected to the input end of the operational amplifier 18 in the charge sampling conversion unit 20, the common mode level feedback signal VCMFB is output to the operational amplifier 18, the third differential signal or the fourth differential signal generated by the operational amplifier 18 is output by the first output end and the second output end of the charge sampling conversion unit 20, and the first output end and the second output end of the operational amplifier 18 are correspondingly electrically connected to the first output end and the second output end of the charge sampling conversion unit 20, or may be electrically connected to the first output end and the second output end of the differential charge amplifier 9.

Alternatively, referring to fig. 7, the circuit structures of the first switch unit 10 and the charge sampling conversion unit 20 are the same as those of fig. 3, and the common mode level feedback unit 14 in fig. 7 may be selected from the circuit structures of the common mode level feedback unit 14 in fig. 5, the operational amplifier 18 is not shown, and the operational amplifier 18 structure in fig. 6 may be adopted, which is not repeated.

Optionally, referring to fig. 7, the signal conversion circuit 17 includes an analog-to-digital converter 171, a thirteenth control switch 15, and a fourteenth control switch 16, where a first end of the thirteenth control switch 15 and a first end of the fourteenth control switch 16 are electrically connected to a second output end and a first output end of the charge sampling conversion unit 20, respectively (i.e., electrically connected to a second output end and a first output end of the operational amplifier 18, respectively), and a second end of the thirteenth control switch 15 and a second end of the fourteenth control switch 16 are electrically connected to a first input end and a second input end of the analog-to-digital converter, respectively, and the first input end (positive input end) and the second input end (negative input end) of the analog-to-digital converter are respectively used as a first input end and a second input end of the comparator. The analog-to-digital converter comprises a comparator and a converter, wherein the converter comprises a plurality of digital signal output ends, and can convert a comparison result into a plurality of parallel digital signals with designed digits.

Alternatively V _INN And V _INP Is with V _OP And V _ON The control terminal of the thirteenth control switch 15 and the control terminal of the fourteenth control switch 16 are electrically connected to the control unit 130, and the control unit 130 is configured to control the thirteenth control switch 15 and the fourteenth control switch 16 to be turned on and off synchronously.

Based on the same inventive concept, an embodiment of the present application provides a display apparatus including: a display panel and a signal processing circuit 1 as in any of the embodiments of the present application;

the display panel includes a plurality of touch electrodes electrically connected to a first end of the first switching unit 10.

Optionally, the touch electrode is connected with the touch output end, and each touch electrode is connected with the touch output end through a touch lead.

Optionally, referring to fig. 7, an application scenario in the field of touch technology of a signal processing circuit is provided, a display panel includes a touch screen, a plurality of touch electrodes of the touch screen, the touch electrodes correspond to touch nodes 430, and are contacted with the touch nodes 430 through a human body to generate charge change, so as to form touch information, and the touch information of a finger is converted into identifiable digital information through technologies such as a sampling circuit, a conversion circuit, an amplifying circuit, and the like, so that the next display and response processing are performed.

The display device provided by the embodiment of the application can be widely applied to the fields of mobile phones, tablet computers, vehicle-mounted screens, touch televisions, touch electronics and the like with touch functions. Meanwhile, the signal processing circuit of the embodiment of the application can be applied to other similar devices for obtaining relevant information by sensing biological signals.

The display device of the embodiment of the application includes the signal processing circuit, so that the display device has the same beneficial effects as the signal processing circuit, and the description thereof is omitted.

Based on the same inventive concept, an embodiment of the present application provides a signal processing method, which is applied to the signal processing circuit 1 of any embodiment of the present application, as shown in fig. 8, and includes: step S801 to step S802.

In the first charge sampling conversion stage, when the excitation voltage signal is at the first level, the first terminal and the third terminal of the first switch unit 10 are controlled to be turned on, and the second terminal and the fourth terminal of the first switch unit 10 are controlled to be turned on, so that the charge sampling conversion unit 20 correspondingly outputs a first set of differential signals from the first output terminal and the second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the first level is a low level and the second level is a high level.

Optionally, the control unit 30 receives the excitation voltage signal Vex, and outputs a control signal to each control switch of the first switch unit 10 according to the received excitation voltage signal Vex and the sampling signal SHA, so as to control each control switch to be correspondingly turned on and off, thereby realizing different signal input to the charge sampling conversion unit 20.

Optionally, when the excitation voltage signal is at the first level, the control unit 30 controls the first terminal and the third terminal of the first switch unit 10 and the second terminal and the fourth terminal to be conductive, so that the charge sampling conversion unit 20 correspondingly outputs a first set of differential signals from the first output terminal and the second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

In the second charge sampling conversion stage, when the excitation voltage signal is at the second level, the first terminal and the fourth terminal of the first switch unit 10 are controlled to be turned on, and the second terminal and the third terminal of the first switch unit 10 are controlled to be turned on, so that the charge sampling conversion unit 20 correspondingly outputs a second set of differential signals from the first output terminal and the second output terminal of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the control unit 30 controls the first end and the fourth end of the first switch unit 10 and the second end and the third end to be conductive, so that the charge sampling conversion unit 20 correspondingly outputs a second set of differential signals from the first output end and the second output end of the charge sampling conversion unit 20 according to the excitation voltage signal and the first voltage.

Optionally, the first charge sampling conversion phase corresponds to a first half period of the excitation voltage signal, and the second charge sampling conversion phase corresponds to a second half period of the excitation voltage signal.

Alternatively, step S802 may be performed after step S801 is performed; step S801 may be performed after step S802 is performed.

In some embodiments, referring to fig. 3, controlling the first terminal and the third terminal of the first switching unit 10 and the second terminal and the fourth terminal to be conductive includes:

the second control switch 7 and the third control switch 6 controlling the first switching unit 10 are both on, and the first control switch 8 and the fourth control switch 5 of the first switching unit 10 are both off.

Controlling the first end and the fourth end of the first switch unit 10 and the second end and the third end to be conducted includes:

the second control switch 7 and the third control switch 6 controlling the first switching unit 10 are both turned off, and the first control switch 8 and the fourth control switch 5 of the first switching unit 10 are both turned on.

Optionally, the signal processing method further comprises:

in the first charge sampling conversion stage, when the excitation voltage signal is at the first level, the second reset module 22 is turned on and off with the forward input end and the first output end of the differential charge amplifier 9, so that a voltage difference exists between the reverse input end and the forward input end of the differential charge amplifier 9, and the first group of differential signals is obtained after the voltage difference is amplified by the differential charge amplifier 9.

Optionally, as shown in fig. 3, when the exciting voltage signal Vex is in a low level stage in one period, the first charge sampling process is performed, since the two ends of the differential charge amplifier 9 are both input with the low level of the exciting voltage signal Vex, after the first reset switch 11 and the second reset switch 13 are reset, the capacitor Cfb2 acts on the positive input end and the second output end of the differential charge amplifier 9, and starts to be conducted due to the second reset switch 13, the charge on the capacitor Cfb2 is 0, when the second reset switch 13 is turned off, since the voltage difference exists between the reverse input end and the positive input end of the differential charge amplifier 9, after the differential charge amplifier 9 amplifies, the voltage V is obtained _OP And V _ON Is a signal of (a). Because the exciting voltage signal Vex is low and connected to the positive input terminal, V is generated _OP Greater than V _ON Is provided.

In the second charge sampling conversion stage, when the excitation voltage signal is at the second level, the first reset module 21 is turned on and off with the reverse input end and the first output end of the differential charge amplifier 9, so that a voltage difference exists between the reverse input end and the forward input end of the differential charge amplifier 9, and the second group of differential signals is obtained after the voltage difference is amplified by the differential charge amplifier 9.

Optionally, the second charge sampling conversion stage is similar to the first charge sampling conversion stage, and the second charge sampling process is performed during the high level stage of the exciting voltage signal Vex in one period, and the second charge sampling process is performed during the first charge sampling processThe principle of sample processing is similar. Because the exciting voltage signal Vex is at high level and connected to the inverting input terminal, V is generated _OP Less than V _ON Is provided.

In some embodiments, the signal processing method further comprises:

outputting a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage, and a gate bias voltage; the set of differential signals includes a first set of differential signals or a second set of differential signals, and the gate bias voltage is the gate bias voltage of a switching device connected to the input of the operational amplifier 18.

Outputting a third set of differential signals or a fourth set of differential signals from the first output terminal and the second output terminal of the operational amplifier 18 correspondingly based on the common mode level feedback signal; the average value of the differential signals of the third group of differential signals is a preset common mode voltage; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

Alternatively, referring to fig. 5, a circuit based on the common mode level feedback unit 14 outputs a common mode level feedback signal based on a set of differential signals, a predetermined common mode voltage, and a gate bias voltage, including:

The fifth control switch 141 and the sixth control switch 142 are controlled to be turned on, and the ninth control switch 145 and the tenth control switch 146 are controlled to be turned on, so that the lower plates of the first capacitor and the fourth capacitor are charged to the VBN1 original bias voltage potential, and the upper plates of the two first capacitors and the fourth capacitor are charged to the desired VCM common mode level potential.

The seventh control switch 143 and the eighth control switch 144 are controlled to be turned on, the eleventh control switch 147 and the twelfth control switch 148 are controlled to be turned on, the first capacitor and the second capacitor are connected in parallel, and the third capacitor and the fourth capacitor are connected in parallel.

Optionally, after the above switch control, VBN1 is sent to VCMFB, and VOP1 and VON1 connect their common mode potential to VCM through the charged first capacitor and fourth capacitor, to obtain a common mode level feedback signal VCMFB, and output to the input terminal of the operational amplifier 18.

Optionally, the signal processing method further comprises: in the signal conversion stage, the control unit 30 controls the thirteenth control switch 15 and the fourteenth control switch 16 to be turned on in synchronization. In connection with fig. 7, a specific signal conversion will be described by taking the case where the converter is located in the digital front-end unit DFE.

Optionally, after the control unit 30 controls the thirteenth control switch 15 and the fourteenth control switch 16 to be turned on synchronously, the method further includes:

The output of each converter is converted into serial data, and the serial data is converted into parallel data of 10 bits in a digital module.

Through the signal conversion process, n digital signals of D9:0 can be reduced to n digital signals of D0, and the number of interactive signals is reduced by 10 times, so that two groups of data signals are obtained based on the first group of differential signals and the second group of differential signals.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

(1) The charge sampling conversion unit 20 of the embodiment of the application can realize the conversion of charge sampling into differential output voltage signals in one period, and can realize the charge sampling twice in one period by switching on different switch combinations through the circuit architecture of the switch sampling channel of the cross conversion input end, so that two groups of sampling data can be obtained after the subsequent analog-digital converter 171, and the influence of middle-low frequency noise on the sampling data can be effectively reduced through further noise filtering, integration and processing of the digital circuit on the source data.

(2) The embodiment of the application does not adopt a sample-and-hold amplifier, omits the area of the sample amplifier and the related sample capacitor and hold capacitor, and simultaneously, the power consumption of the part of the signal processing circuit 1 can be greatly reduced because only one differential charge amplifier 9 is used.

(3) The embodiment of the application adopts the realization method of the common mode feedback circuit, so that charges can be directly sampled twice in one period and converted into differential signals with preset common mode voltage, and the application of the double sampling concept in the field of touch sampling can effectively filter noise with medium and low frequencies, and improve the noise resistance, stability, sensitivity and accuracy of the whole chip.

(4) The analog-to-digital converter 171 of the embodiment of the present application can convert serial data into parallel data of 10 bits in a digital module by converting the output of the converter into serial data, and reduce the number of interactive signals by 10 times, thereby obtaining two sets of data signals based on the first set of differential signals and the second set of differential signals.

Those of skill in the art will appreciate that the various operations, methods, steps in the flow, acts, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed herein may be alternated, altered, rearranged, disassembled, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.

Claims

1. A signal processing circuit, comprising: a first switching unit and a charge sampling conversion unit;

The charge sampling conversion unit comprises a differential charge amplifier, wherein the forward input end, the reverse input end, the first output end and the second output end of the differential charge amplifier are respectively used as the forward input end, the reverse input end, the first output end and the second output end of the charge sampling conversion unit; when the excitation voltage signal is at a first level, a first end and a third end of the first switch unit and a second end and a fourth end of the first switch unit are conducted, a first group of differential signals are correspondingly output from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage; when the excitation voltage signal is at a second level, a first end and a fourth end of the first switch unit are conducted, and a second end and a third end of the first switch unit are conducted, a second group of differential signals are correspondingly output from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage;

the signal processing circuit further includes: a common mode level feedback unit and an operational amplifier; the operational amplifier is located within the differential charge amplifier;

The operational amplifier comprises a first current source module, a second current source module, a differential pair tube module, a first current mirror module, a second current mirror module and a floating current module which is electrically connected with the first current mirror module and the second current mirror module; the first current source module is a P-type current source with a common-source and common-gate structure, and the second current source module is an N-type current source with a common-source and common-gate structure so as to provide current for the differential pair tube module; the first current mirror module is a P-type current mirror with a common-source common-gate structure, and the second current mirror module is an N-type current mirror with a common-source common-gate structure, so as to be used as a load of the differential pair tube module; the differential pair tube module comprises a P-type differential pair tube and an N-type differential pair tube; and the common gate end of each main image tube in the second current mirror module is used as the input end of the operational amplifier.

2. The signal processing circuit of claim 1, further comprising:

the control unit is electrically connected with the first switch unit and is used for controlling the first end and the third end of the first switch unit and the second end and the fourth end to be conducted when the excitation voltage signal is at a first level; when the excitation voltage signal is at a second level, the first end and the fourth end of the first switch unit are controlled to be conducted, and the second end and the third end are controlled to be conducted.

3. The signal processing circuit of claim 2, wherein the first switching unit comprises a first control switch, a second control switch, a third control switch, and a fourth control switch;

a first end of the second control switch and a first end of the fourth control switch are used as a first end of the first switch unit together;

4. The signal processing circuit of claim 2, wherein the charge sampling conversion unit further comprises a first reset module and a second reset module;

the control unit is electrically connected with the first reset switch and the second reset switch and is used for controlling the connection and disconnection of the first reset switch and the second reset switch.

5. The signal processing circuit of claim 1, further comprising: a denoising capacitor;

the second end of the denoising capacitor is used for receiving an excitation voltage signal.

6. The signal processing circuit of claim 1, wherein the signal processing circuit comprises a logic circuit,

the common mode level feedback unit is used for outputting a common mode level feedback signal based on a group of differential signals, a preset common mode voltage and a grid bias voltage; the set of differential signals comprises a first set of differential signals or a second set of differential signals, and the grid bias voltage is the grid bias voltage of a switching device connected with the input end of the operational amplifier.

7. The signal processing circuit according to claim 6, wherein the operational amplifier is configured to output a third set of differential signals or a fourth set of differential signals from the first output terminal and the second output terminal of the operational amplifier, respectively, based on the common mode level feedback signal; the average value of the differential signals of the third group of differential signals is a preset common mode voltage; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.

8. The signal processing circuit of claim 7, wherein the common mode level feedback unit comprises: a first common mode level feedback sub-circuit;

9. The signal processing circuit of claim 8, wherein the common mode level feedback unit further comprises: a second common mode level feedback sub-circuit;

the first end of the ninth control switch, the first end of the tenth control switch and the first end of the eleventh control switch are respectively used for receiving a preset common mode voltage, a grid bias voltage and another differential signal in a group of differential signals;

10. The signal processing circuit of claim 7, further comprising: a signal conversion unit;

The signal conversion unit is used for comparing the third group of differential signals or the fourth group of differential signals to obtain a comparison result, and converting the comparison result into a digital signal.

11. A display device, comprising: a display panel and a signal processing circuit as claimed in any one of claims 1 to 10;

12. A signal processing method applied to a signal processing circuit according to any one of claims 1 to 10, comprising:

in a first charge sampling conversion stage, when an excitation voltage signal is at a first level, controlling a first end and a third end of the first switch unit and a second end and a fourth end to be conducted, so that a first group of differential signals are correspondingly output from a first output end and a second output end of the charge sampling conversion unit according to the excitation voltage signal and the first voltage;

13. The signal processing method according to claim 12, wherein controlling the first terminal and the third terminal of the first switching unit and the second terminal and the fourth terminal to be conductive includes:

the second control switch and the third control switch of the first switch unit are controlled to be both on, and the first control switch and the fourth control switch of the first switch unit are controlled to be both off;

the controlling the first end and the fourth end of the first switch unit and the second end and the third end to be conducted includes:

the second control switch and the third control switch of the first switch unit are controlled to be turned off, and the first control switch and the fourth control switch of the first switch unit are controlled to be turned on.

14. The signal processing method according to claim 13, further comprising:

outputting a third group of differential signals or a fourth group of differential signals from a first output end and a second output end of the operational amplifier correspondingly based on the common mode level feedback signals; the average value of the differential signals of the third group of differential signals is a preset common mode voltage; the average value of the differential signals of the fourth set of differential signals is a predetermined common mode voltage.