CN114356812B

CN114356812B - Interrupt processing method and device, electronic equipment and computer readable storage medium

Info

Publication number: CN114356812B
Application number: CN202111670637.8A
Authority: CN
Inventors: 沈一聪; 邹仕洪; 姜哲; 张广伟; 张炯明
Original assignee: Yuanxin Information Technology Group Co ltd
Current assignee: Yuanxin Information Technology Group Co ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-08-26
Anticipated expiration: 2041-12-31
Also published as: CN114356812A

Abstract

The application provides an interrupt processing method, an interrupt processing device, electronic equipment and a computer readable storage medium, and relates to the technical field of virtualization. The method comprises the following steps: the method receives the target interrupt through the target core according to the independent right related content; determining a physical address of a processor interface GICC of the target interrupt controller in a memory according to a preset equipment tree; accessing the target GICC according to the physical address to process the target interrupt; the target interrupt is determined and configured from the intercepted at least one interrupt by the distributor GICD of the pre-built virtual interrupt controller. According to the method and the device, partial interrupts in the interrupt controller are reserved and directly communicated, so that the partial interrupts can be directly transmitted to the specific virtual machine without being intercepted and virtualized by the virtual machine monitor and processed by the specific virtual machine, and the delay generated when the specific virtual machine processes the interrupts is reduced.

Description

Interrupt processing method and device, electronic equipment and computer readable storage medium

Technical Field

The present application relates to the field of virtualization technologies, and in particular, to an interrupt processing method and apparatus, an electronic device, and a computer-readable storage medium.

Background

Virtualization has become a popular technique in the computer field. Virtualization technology allows multiple user operating systems to run on the same physical host. By integrating multiple virtual machines onto a single hardware platform, virtualization techniques may reduce cost and improve manageability.

To efficiently implement interrupt virtualization, some commercial processors, such as the ARMv8 processor, have virtualization extensions such as virtual interrupts and general purpose interrupt controllers (GICs).

After the introduction of the virtualization technology, the virtual machine monitor needs to intercept all external interrupts and route the interrupts to the target virtual machine through the virtual interrupt controller. Even though virtualization is assisted by hardware to reduce the overhead of interrupting virtualization, this process still incurs some delay.

Disclosure of Invention

The embodiment of the application provides an interrupt processing method and device, electronic equipment and a computer readable storage medium. The technical scheme is as follows:

according to an aspect of the embodiments of the present application, there is provided a method for processing interrupt, applied to a processor, the method including:

receiving, by a target core, a target interrupt;

determining a physical address of a processor interface GICC of the target interrupt controller in a memory according to a preset equipment tree;

accessing the target GICC according to the physical address to process the target interrupt;

wherein the target interrupt is determined and configured from the intercepted at least one interrupt by a distributor GICD of a pre-built virtual interrupt controller.

In one possible implementation, the accessing the target GICC according to the physical address to process the target interrupt includes:

indicating that a first register in the target GICC approves the target interrupt;

instructing a second register in the target GICC to reset the priority of the target interrupt and invalidate the target interrupt.

In another possible implementation manner, the determining, according to a preset device tree, a physical address of the target GICC in the memory includes:

determining the equipment node of the target GICC from the equipment tree, and determining the physical address of the target GICC in the memory according to the pre-established address mapping information of the target GICC;

wherein the address mapping information includes a mapping relationship between an intermediate physical address and a physical address of an MMIO address space where the target GICC is located.

According to another aspect of the embodiments of the present application, there is provided an interrupt processing method applied to a virtual machine monitor, the method including:

intercepting at least one interrupt sent to the target core by a preset hardware device through a pre-constructed virtual GICD;

determining a target interrupt meeting a preset condition from the at least one interrupt, and configuring the target interrupt;

and sending the configured target interrupt to a GICC (graphics primitive center), and indicating the GICC to send the configured target interrupt to a target core corresponding to a target virtual machine.

In one possible implementation, the pre-constructed virtual GICD previously includes:

determining a target register in a target core corresponding to the target virtual machine;

modifying a target parameter in the target register to allow all interrupts to not be intercepted to a preset privilege level.

In another possible implementation manner, the determining, from the at least one interrupt, a target interrupt meeting a preset condition includes:

acquiring preconfiguration information of target interruption corresponding to the target virtual machine;

and if the configuration information of at least one interrupt is determined to meet the preconfigured information, determining the interrupt as a target interrupt meeting preset conditions.

In yet another possible implementation manner, the pre-constructed virtual GICD further includes:

if the fact that the bottom-layer firmware supports software to delegate the abnormal interface SDEI is determined, configuring corresponding SDEI events for the target core;

enabling the SDEI events and unmasking the target core for the respective SDEI events;

and if the bottom-layer firmware is determined not to support the SDEI, indicating the target core to process the asynchronous event in a user-mode program polling mode.

According to another aspect of an embodiment of the present application, there is provided an apparatus for interrupt processing, the apparatus including:

a receiving module for receiving a target interrupt through a target core;

the determining module is used for determining the physical address of a processor interface GICC of the target interrupt controller in the memory according to a preset device tree;

a processing module for accessing the target GICC according to the physical address to process the target interrupt;

the intercepting module is used for intercepting at least one interrupt sent to the target core by a preset hardware device through a pre-constructed virtual GICD;

the configuration module is used for determining a target interrupt meeting a preset condition from the at least one interrupt and configuring the target interrupt;

and the sending module is used for sending the configured target interrupt to the GICC and indicating the GICC to send the configured target interrupt to a target core corresponding to the target virtual machine.

According to another aspect of an embodiment of the present application, there is provided an electronic apparatus including:

comprising a memory, a processor and a computer program stored on the memory, the processor executing the computer program to implement the steps of any of the interrupt handling methods.

According to still another aspect of embodiments of the present application, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the interrupt processing methods.

According to an aspect of an embodiment of the present application, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the interrupt processing methods.

The technical scheme provided by the embodiment of the application has the following beneficial effects: and reserving and directly communicating part of the interrupt in the interrupt controller, so that the part of the interrupt can be directly transmitted to the specific virtual machine without being intercepted and virtualized by a virtual machine monitor and processed by the specific virtual machine, and the delay generated when the specific virtual machine processes the interrupt is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below.

Fig. 1 is a schematic flowchart of an interrupt processing method according to an embodiment of the present application;

fig. 2 is a schematic flowchart of another interrupt processing method according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another interrupt processing apparatus according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device for processing interrupt according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the embodiments set forth below in connection with the drawings are exemplary descriptions for explaining technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms "comprises" and/or "comprising," when used in this specification in connection with embodiments of the present application, specify the presence of stated features, information, data, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, information, data, steps, operations, elements, components, and/or groups thereof, as embodied in the art. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein indicates at least one of the items defined by the term, e.g., "a and/or B" may be implemented as "a", or as "B", or as "a and B".

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The terms referred to in this application will first be introduced and explained:

a Virtual Machine (VM) refers to a complete computer system that has complete hardware system functions and runs in a completely isolated environment, which is simulated by software, and the work that can be completed in a physical computer can be generally implemented in a Virtual Machine. When creating a virtual machine in an electronic device such as a computer, it is necessary to use a part of the hard disk and the memory capacity of a physical machine as the hard disk and the memory capacity of the virtual machine, and each virtual machine can be regarded as having independent hardware and an operating system, and can operate the virtual machine as if the physical machine is used.

A virtual machine monitor (Hypervisor), also known as vmm (virtual machine monitor), is an intermediate software layer that runs between the physical hardware and the operating system and allows multiple operating systems or applications to share the hardware. Hypervisors can be regarded as a 'meta' operating system in a virtual environment, and can access all physical hardware including a disk and a memory, and not only can the Hypervisors coordinate the access of the hardware resources, but also can exert protection among virtual machines.

Interrupt Controllers (GICs), including distributors (GICDs) and processor interfaces (CPUs interfaces, GICCs), are typically used to manage interrupt sources, interrupt behavior, and interrupt routing for one or more processors by specific registers and allow specific Virtual Machines (VMs) to efficiently handle interrupts according to the source and state of the exception. In the technical scheme of the application, no virtual word is arranged in front of the GICD and the GICC to represent physical hardware; if the virtual two words exist, the virtual hardware constructed by the virtual machine monitor is represented.

An interrupt is a signal sent to the processor from either hardware or software to indicate an event that needs to be immediately processed.

The application provides an interrupt processing method, an interrupt processing device, an electronic device and a computer readable storage medium, and aims to solve the technical problems in the prior art.

The technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application are explained below by describing several exemplary embodiments. It should be noted that the following embodiments may be referred to, referred to or combined with each other, and the description of the same terms, similar features, similar implementation steps and the like in different embodiments is not repeated.

As shown in fig. 1, the present application provides an interrupt processing method, which may be based on a processor (CPU) of an electronic product such as a terminal, and the method may include:

s101, receiving a target interrupt through a target core, wherein the target interrupt is determined and configured from at least one intercepted interrupt through a distributor GICD of a pre-constructed virtual interrupt controller.

In the embodiment of the present application, a target core of a target virtual machine, that is, a CPU core corresponding to the target virtual machine, may receive a target interrupt transmitted through a pin (pin) from a GICC; and the target core needs to respond to the target interrupt after receiving the target interrupt, namely interrupt approval, and converts the interrupted state from the pending state to the active state. Wherein the target interrupt is determined and configured by the virtual machine monitor from all the intercepted interrupt sources through a distributor GICD of a virtual interrupt controller which is constructed in advance.

S102, determining the physical address of a processor interface GICC of the target interrupt controller in the memory according to the preset device tree.

In this embodiment, the target core may determine an actual physical address of the GICC, that is, an actual address of the GICC in the memory, according to the device node of the GICC in the preset device tree.

S103, accessing the target GICC according to the physical address to process the target interrupt;

in the implementation of the present application, the physical address includes an address of the GICC-related register, and further, the related register may be directly accessed according to the actual physical address of the GICC-related register, so as to process the target interrupt.

Specifically, the accessing the target GICC according to the physical address to process the target interrupt may include:

indicating that a first register in the target GICC approves the target interrupt.

In an embodiment of the present application, a physical address of a first register of the GICC may be determined in the physical address, and the first register may be directly accessed according to the physical address, for example, addresses of the GICC _ TAR and the GICC _ air may be directly accessed, so that the target core may acknowledge the target interrupt in response to the target interrupt, for example, by directly accessing the first register of the GICC to determine a source of the interrupt, and then execute the interrupt. The specific flow of the interrupt is specifically executed, which is not specifically limited in this application as long as the target virtual machine can directly access the relevant register of the GICC according to the actual physical address of the relevant register of the GICC.

In this embodiment of the application, some parameters in the gich.ctrl register may be set, so that the whole "interrupt completion" may be performed in stages, that is, in one stage, the priority of the target terminal and the target interrupt are reset, for example, the GICC _ CLTR _ EN _ BIT and the GICC _ CTLR _ EOImodeNS _ BIT in the gich.ctrl register may be set, so that the "interrupt completion" is completed in one stage, that is, the priority of the target interrupt and the target interrupt are reset and the target interrupt is invalidated by reading and writing the second register of one GICC, and the processing flow of the target interrupt is ended.

Specifically, the determining the physical address of the target GICC in the memory according to the preset device tree may include:

determining a device node of the target GICC from the device tree, and determining a Physical Address of the target GICC in a memory according to pre-established Address mapping information of the target GICC, wherein the Address mapping information comprises a mapping relation between an Intermediate Physical Address (IPA) and a Physical Address (PA) of an MMIO (memory Mapped IO) Address space where the target GICC is located.

In this embodiment of the present application, two-stage device address mapping of an MMIO address space where the GICC is located may be established in advance for the target virtual machine, that is, mapping between an intermediate physical address of the GICC and an actual physical address is established, and meanwhile, a device node of the GICC is configured in a preset device tree corresponding to the target virtual machine, so that the target virtual machine may directly access the GICC.

As shown in fig. 2, the present application further provides an interrupt processing method, which may be based on a virtual machine monitor of an electronic product such as a terminal, and the method may include:

s201, intercepting at least one interrupt sent to the target core by a preset hardware device through a pre-constructed virtual GICD.

In the embodiment of the application, a virtual machine monitor can pre-construct a virtual GICD device, the virtual GICD device can correspond to a target virtual machine, and meanwhile, in a preset device tree, a corresponding virtual GICD device node is provided to configure corresponding hardware resources for the virtual GICD device node; the virtual GICD device can acquire the interrupt configuration information of the target virtual machine, namely, can determine which interrupt can be processed by the target core. Meanwhile, the virtual GICD device can collect all interrupt sources, set interrupt priority, interrupt grouping, target cores corresponding to interrupts and the like for each interrupt source, and send the current interrupt with the highest priority to the corresponding processor interface if the interrupt is generated.

S202, determining target interrupts meeting preset conditions from the at least one interrupt, and configuring the target interrupts.

In this embodiment, the virtual GICD may determine, among the intercepted interrupt sources, interrupt sources that may be received by the target core, and when these interrupt sources generate interrupts, may configure the interrupts generated by the interrupt sources, for example, configure information such as priority and interrupt grouping of the interrupts.

S203, sending the configured target interrupt to the GICC, and indicating the GICC to send the configured target interrupt to a target core corresponding to the target virtual machine.

In this embodiment of the present application, the virtual GICD may update the configuration information of the interrupt meeting the preset condition to the register of the physical hardware GICD, so that the GICC may read the interrupt configuration information in the register of the GICD, and send the configured target interrupt to the target core corresponding to the target virtual machine through pins (pins) such as IRQ by means of the GICC.

On the basis of the above embodiments, as an optional embodiment, the present application provides a partial cut-through technology (cpc), which is referred to as GPPT), for an interrupt controller, and the present application solves the technical problem of frequent virtual machine Exit (VM Exit) caused by interrupt delay and interrupt virtualization through the GPPT technology.

Further, the pre-constructed virtual GICD may previously include:

and determining a target register of a target core corresponding to the target virtual machine, and modifying target parameters in the target register to allow all interrupts not to be intercepted to a preset privilege level.

In this embodiment, a core of a target processor corresponding to a target virtual machine, that is, a target core, may be determined, and a target register of the target core, for example, the HCR _ EL2 register, may be determined, and the IMO and AMO bits in the register are modified, so that an interrupt sent to the target core is not intercepted to a preset privilege level, for example, the EL2, but is directly injected to the EL1 privilege level, and thus the target interrupt sent to the target virtual machine is directly sent to the target core corresponding to the target virtual machine without being processed by the virtual machine monitor.

Further, the determining, from the at least one interrupt, a target interrupt meeting a preset condition includes:

and acquiring preconfigured information of target interrupt corresponding to the target virtual machine, and if the configuration information of at least one interrupt is determined to meet the preconfigured information, determining that the interrupt is the target interrupt meeting preset conditions.

In the embodiment of the application, MMIO access of a target virtual machine to a GICD can be intercepted, pre-configuration information which can be sent to a target core interrupt is determined according to MMIO context and the like, corresponding configuration information is determined for each interrupt source in interrupt sources intercepted by the virtual GICD, and if the configuration information is consistent with the pre-configuration information, the interrupt generated by the interrupt source can be transmitted to the target virtual machine after configuration.

Specifically, before the pre-constructed virtual GICD, the method may further include:

if the fact that the bottom-layer firmware supports software to delegate the abnormal interface SDEI is determined, configuring corresponding SDEI events for the target core; enable (Enable) the SDEI events and unmask the target core from the corresponding SDEI events.

In the embodiment of the present application, since the target core configured with the GPPT may not be able to intercept any interrupt actively through the hypervisor and also cannot inject a virtual interrupt through the virtual GIC, the hypervisor directly loses the function of notifying the target virtual machine of the asynchronous event. To ensure the coexistence of GPPT and VM management/communications, it may be determined whether the terminal-like electronic product contains an ATF or firmware similar to its functionality, e.g., when the terminal-like electronic product contains an ATF, the virtual machine monitor may be caused to regain control of the target core through the SDEI asynchronous event notification mechanism provided by the ATF.

Software Delegated Exception Interface (SDEI) is an asynchronous event mechanism integrated into ARM Trusted Firmware (ATF) that allows a user to define various asynchronous events in Firmware through a specific programming Interface (i.e., SDEI call Interface) based on smc (secure Monitor call) privileged instructions and initiate the asynchronous events to various cores in the system through a specified call flow. After the asynchronous event is initiated, the target core is trapped in a pre-configured privilege level only by the non-maskable exception and jumps to the corresponding exception entry. When the target core finishes processing the SDEI event, the position of the previous execution is returned through the SDEI calling interface, and the corresponding context is restored.

On the basis of the above embodiments, as an optional embodiment, in an initial process of the virtual machine monitor, it may be detected whether the current underlying firmware provides complete SDEI support through SDEI _ VERSION; if the bottom firmware of the electronic product such as the current terminal supports complete SDEI, each core can be configured with SDEI _ HANDLER of the corresponding EVENT and an exception ENTRY SDEI _ ENTRY through an SDEI _ EVENT _ REGISTER programming interface of the SDEI, that is, the SDEI asynchronous EVENT which needs to be processed by the core is configured for the target core, the SDEI EVENT is enabled through the SDEI _ EVENT _ ENABLE, and the shielding of any SDEI EVENT by the target core is released through the SDEI _ PE _ UNMASK.

On the basis of the above embodiments, as an alternative embodiment, the user may initiate an SDEI EVENT to the target core through the SDEI _ EVENT _ SIGNAL, so that the target core falls into the privilege level of EL2, and jumps to a previously set exception entry, saves the context of the current target core execution environment, etc., and then jumps to the SDEI _ handle to process the corresponding SDEI EVENT, where how to process the SDEI EVENT is specific, which is not specifically limited in this application. After the target core has processed the SDEI EVENT, it returns to the original execution environment via SDEI _ EVENT _ COMPLETE to continue executing the previously executed EVENT. Through an asynchronous event mechanism in the ATF, communication among a plurality of virtual machines configured with a GPPT mode in electronic products such as terminals is realized, so that an asynchronous event notification mechanism based on soft interrupt in the prior art is replaced.

In the embodiment of the present application, if the electronic devices such as the terminal do not support the ATF or the hardware platform or firmware similar to the ATF, the asynchronous event may be processed in a user mode program polling manner. Specifically, how to process the asynchronous event is not specifically limited in the present application, as long as the target core configured with the GPPT can process the asynchronous event through a program polling mechanism.

An embodiment of the present application provides an interrupt processing apparatus, as shown in fig. 3, the interrupt processing apparatus 30 may include: a receiving module 301, a determining module 302, and a processing module 303, wherein,

a receiving module 301, configured to receive a target interrupt through a target core;

a determining module 302, configured to determine, according to a preset device tree, a physical address of a processor interface GICC of a target interrupt controller in a memory;

a processing module 303, configured to access the target GICC according to the physical address to process the target interrupt;

An embodiment of the present application further provides an interrupt processing apparatus, as shown in fig. 4, the interrupt processing apparatus 40 may include: an interception module 401, a configuration module 402, and a sending module 403, wherein,

an interception module 401, configured to intercept, through a pre-established virtual GICD, at least one interrupt sent to the target core by a preset hardware device;

a configuration module 402, configured to determine a target interrupt meeting a preset condition from the at least one interrupt, and configure the target interrupt;

a sending module 403, configured to send the configured target interrupt to the GICC, and instruct the GICC to send the configured target interrupt to a target core corresponding to the target virtual machine.

Compared with the related art, the method can realize that: and reserving and directly communicating part of the interrupt in the interrupt controller, so that the part of the interrupt can be directly transmitted to the specific virtual machine without being intercepted and virtualized by a virtual machine monitor and processed by the specific virtual machine, and the delay generated when the specific virtual machine processes the interrupt is reduced.

The apparatus of the embodiment of the present application may execute the method provided by the embodiment of the present application, and the implementation principle is similar, the actions executed by the modules in the apparatus of the embodiments of the present application correspond to the steps in the method of the embodiments of the present application, and for the detailed functional description of the modules of the apparatus, reference may be specifically made to the description in the corresponding method shown in the foregoing, and details are not repeated here.

An embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory, where the processor executes the computer program to implement steps of an interrupt processing method, and compared with the related art, the method can implement: partial interrupts in the interrupt controller are reserved and directly communicated, so that the partial interrupts do not pass through the interception and virtualization of the virtual machine monitor, can be directly transmitted to the specific virtual machine and are processed by the specific virtual machine, and the delay generated when the specific virtual machine processes the interrupts is reduced.

In an alternative embodiment, an electronic device is provided, as shown in fig. 5, the electronic device 5000 shown in fig. 5 includes: a processor 5001 and a memory 5003. The processor 5001 and the memory 5003 are coupled, such as via a bus 5002. Optionally, the electronic device 5000 may further include a transceiver 5004, and the transceiver 5004 may be used for data interaction between the electronic device and other electronic devices, such as transmission of data and/or reception of data. It should be noted that the transceiver 5004 is not limited to one in practical application, and the structure of the electronic device 5000 does not limit the embodiments of the present application.

The Processor 5001 may be a CPU (Central Processing Unit), a general-purpose Processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor 5001 may also be a combination of processors implementing computing functionality, e.g., a combination comprising one or more microprocessors, a combination of DSPs and microprocessors, or the like.

Bus 5002 can include a path that conveys information between the aforementioned components. The bus 5002 may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus 5002 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 5, but this is not intended to represent only one bus or type of bus.

The Memory 5003 may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), a magnetic disk storage medium, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and that can be Read by a computer, without limitation.

The memory 5003 is used for storing computer programs for executing the embodiments of the present application, and is controlled by the processor 5001 for execution. The processor 5001 is configured to execute computer programs stored in the memory 5003 to implement the steps shown in the foregoing method embodiments.

Embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program may implement the steps and corresponding contents of the foregoing method embodiments.

Embodiments of the present application further provide a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps and corresponding contents of the foregoing method embodiments can be implemented.

The terms "first," "second," "third," "fourth," "1," "2," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than illustrated or otherwise described herein.

It should be understood that, although each operation step is indicated by an arrow in the flowchart of the embodiment of the present application, the implementation order of the steps is not limited to the order indicated by the arrow. In some implementation scenarios of the embodiments of the present application, the implementation steps in the flowcharts may be performed in other sequences as desired, unless explicitly stated otherwise herein. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on an actual implementation scenario. Some or all of these sub-steps or stages may be performed at the same time, or each of these sub-steps or stages may be performed at different times, respectively. In a scenario where execution times are different, an execution sequence of the sub-steps or the phases may be flexibly configured according to requirements, which is not limited in the embodiment of the present application.

The foregoing is only an optional implementation manner of a part of implementation scenarios in this application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical idea of this application are also within the protection scope of the embodiments of this application without departing from the technical idea of this application.

Claims

1. An interrupt handling method, the method comprising:

intercepting at least one interrupt sent to a target core by a preset hardware device through a pre-constructed virtual GICD;

sending the configured target interrupt to a GICC (graphics primitive controller), and indicating the GICC to send the configured target interrupt to a target core corresponding to a target virtual machine;

wherein the pre-constructed GICD further comprises:

if the fact that the bottom layer firmware supports software to delegate the abnormal interface SDEI is determined, configuring corresponding SDEI events for the target core;

2. The method of claim 1, wherein the pre-constructed virtual GICD, previously comprises:

modifying a target parameter in the target register to allow all interrupts not to be intercepted to a preset privilege level.

3. The method according to claim 1, wherein said determining a target interrupt meeting a preset condition from said at least one interrupt comprises:

and if the configuration information of at least one interrupt is determined to accord with the pre-configuration information, determining the interrupt as a target interrupt meeting a preset condition.

4. An interrupt processing apparatus, comprising:

the system comprises an interception module, a target core and a hardware device, wherein the interception module is used for intercepting at least one interrupt sent to the target core by a preset hardware device through a pre-constructed virtual GICD;

the sending module is used for sending the configured target interrupt to the GICC and indicating the GICC to send the configured target interrupt to a target core corresponding to a target virtual machine;

wherein the interrupt processing apparatus further includes:

the event configuration module is used for configuring corresponding SDEI events for the target core if the fact that the bottom-layer firmware supports software to delegate the abnormal interface SDEI is determined;

a masking module to enable the SDEI events and unmask corresponding SDEI events from the target core;

and the processing module is used for indicating the target core to process the asynchronous event in a user mode program polling mode if the bottom-layer firmware is determined not to support the SDEI.

5. An electronic device comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to perform the steps of the method of any of claims 1-3.

6. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 3.