CN114355685B - Array substrate, preparation method of array substrate and display panel - Google Patents
Array substrate, preparation method of array substrate and display panel Download PDFInfo
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- CN114355685B CN114355685B CN202111657307.5A CN202111657307A CN114355685B CN 114355685 B CN114355685 B CN 114355685B CN 202111657307 A CN202111657307 A CN 202111657307A CN 114355685 B CN114355685 B CN 114355685B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The application discloses an array substrate, a preparation method of the array substrate and a display panel, wherein the array substrate comprises a substrate, a plurality of scanning lines, a plurality of data lines, a color filter layer and a display electrode; the color filter layer is provided with a plurality of color resistance layers with different colors corresponding to the pixels, each color resistance layer comprises a first color resistance layer, each first color resistance layer comprises an edge part close to the data line and a middle part far away from the data line, and the thickness of the edge part is larger than that of the middle part along the arrangement direction of the scanning lines; the display electrode comprises a first display electrode, the first display electrode is arranged on the first color resistance layer, and the first display electrode comprises a plurality of first display electrode branches; the width of the first display electrode branch corresponding to the edge part is smaller than that of the first display electrode branch corresponding to the middle part. According to the display device, the width of the display electrode branches is adjusted in the above mode, the phenomenon of uneven transmittance of the array substrate is improved, and the image quality performance effect is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
Liquid crystal displays, which occupy more and more important places in people's lives and works, have advantages of thin body, power saving, low price, etc., and thus have been widely used, such as: computers, cell phones, televisions, etc. The lcd generally comprises an lcd panel and a backlight module, wherein the lcd panel comprises a counter substrate, an array substrate for controlling electrical signals, and a liquid crystal sandwiched between the two substrates.
However, the color filter layer is generally made of photoresist made by coating, but because of the leveling problem of the photoresist itself, the color resist layer formed may be concave, resulting in a thin thickness at the middle position and a thick thickness at the edge position, resulting in different transmittances at the middle position and the edge position of the pixel corresponding to the color resist layer, and further resulting in a difference in chromaticity and brightness, resulting in a poor image quality of the product. Therefore, it is necessary to provide a new design to improve the problem of poor image quality due to the difference in transmittance.
Disclosure of Invention
The present application provides an array substrate, a method for manufacturing the array substrate, and a display panel, in which the width of a display electrode branch is adjusted to improve the phenomenon of uneven transmittance of the array substrate and improve the image quality performance.
The application discloses an array substrate, which is applied to a display panel and comprises a substrate, a plurality of scanning lines, a plurality of data lines, a color filter layer and a display electrode; the scanning lines and the data lines are arranged on the substrate and are staggered to form a plurality of pixels, each pixel comprises a display electrode, and each display electrode comprises a plurality of display electrode branches; the color filter layer is provided with a plurality of color resistance layers with different colors corresponding to the pixels, each color resistance layer comprises a first color resistance layer, each first color resistance layer comprises an edge part close to the data line and a middle part far away from the data line, and the thickness of the edge part is larger than that of the middle part along the arrangement direction of the scanning lines; the display electrode comprises a first display electrode, the first display electrode is arranged on the first color resistance layer, and the first display electrode comprises a plurality of first display electrode branches; wherein the width of the first display electrode branch corresponding to the edge portion is smaller than the width of the first display electrode branch corresponding to the middle portion.
Optionally, the display panel is a planar conversion display panel, the first display electrode includes a pixel electrode and a common electrode, and the pixel electrode includes a plurality of pixel electrode branches; the common electrode comprises a plurality of common electrode branches, the common electrode branches and the pixel electrode branches are alternately arranged at intervals and extend along the arrangement direction of the data lines to form a horizontal electric field; among the plurality of pixel electrode branches, the width of the pixel electrode branch corresponding to the edge portion is smaller than the width of the pixel electrode branch corresponding to the middle portion; and/or in the plurality of common electrode branches, the width of the common electrode branch corresponding to the edge part is smaller than that of the common electrode branch corresponding to the middle part.
Optionally, the display panel is a vertical alignment display panel, the first display electrode includes a pixel electrode, the pixel electrode includes a cross-shaped keel and a plurality of pixel electrode branches, and the plurality of pixel electrode branches are connected to the cross-shaped keel; the part of the pixel electrode branch corresponding to the edge part is an end part, the part of the pixel electrode branch corresponding to the middle part is a middle part, and the width of the end part of the pixel electrode branch is smaller than that of the middle part of the pixel electrode branch.
Optionally, the display panel is a fringe field switching technology display panel, the first display electrode includes a pixel electrode, and the pixel electrode includes a plurality of pixel electrode branches; the display electrodes comprise second display electrodes, the second display electrodes are arranged between the color filter layers, the second display electrodes are integral electrodes, and the second display electrodes and the pixel electrodes form fringe electric fields; in the plurality of pixel electrode branches, the width of the pixel electrode branch corresponding to the edge portion is smaller than the width of the pixel electrode branch corresponding to the middle portion.
Optionally, the width range of the first display electrode branch arranged corresponding to the middle part is 1.5um to 3.0um; the width range of the first display electrode branch corresponding to the edge part is 1.0 um-2.0 um.
Optionally, the array substrate further includes a planarization layer, the planarization layer is disposed above the color filter layer, and the display electrode is disposed on the planarization layer; and the thickness of the flat layer corresponding to the edge part is smaller than that of the flat layer corresponding to the middle part, so that the surface of the flat layer far away from the color filter layer is flush.
Optionally, the color filter layer further includes at least one second color resist layer, and the second color resist layer has a uniform thickness along the arrangement direction of the scanning lines; the display electrodes comprise third display electrodes, the third display electrodes are arranged on the second color resistance layer, and the third display electrodes comprise a plurality of third display electrode branches; wherein a width of the third display electrode branch is equal to a width of the first display electrode branch disposed corresponding to the middle portion.
Optionally, the first display electrode branches corresponding to the edge portions are arranged, and the widths of the first display electrode branches gradually increase from a position close to the scan line to a position far away from the scan line along the arrangement direction of the data lines.
The application also discloses a preparation method of the array substrate, which is used for manufacturing any one of the array substrates disclosed by the application, and the preparation method of the array substrate comprises the following steps:
providing a substrate, sequentially preparing a plurality of scanning lines and a plurality of data lines on the substrate, and forming a plurality of pixel regions in a staggered manner;
forming at least one second color resistance layer corresponding to the pixel region, and finally forming a first color resistance layer to form a color filter layer;
forming a planarization layer on the color filter layer;
preparing a plurality of third display electrodes on the flat layer corresponding to the upper part of the second color resistance layer, and preparing a plurality of first display electrodes on the flat layer corresponding to the upper part of the first color resistance layer to form a conductive layer so as to form pixels in the pixel area;
the width of the display electrode branch of the first display electrode arranged corresponding to the edge part of the first color resistor is larger than the width of the display electrode branch of the first display electrode arranged corresponding to the middle part of the first color resistor.
The application also discloses a display panel, including opposition base plate and this application disclose arbitrary the array substrate, the opposition base plate with the array substrate sets up the box.
In the scheme that the color resistance layer, especially the color resistance layer formed last, is prone to have a concave problem, so that pixel transmittance of the color resistance layer is different, and image quality is poor, the width of the first display electrode branch corresponding to different positions of the first color resistance layer is adjusted, specifically, the width of the first display electrode branch corresponding to the edge portion of the color resistance layer with larger thickness is smaller than that of the first display electrode branch corresponding to the middle portion of the color resistance layer, and when the color resistance layer is the same in thickness, the smaller the width of the first display electrode branch is, the higher the transmittance is; when the widths of the first display electrode branches are the same, the thicker the color resistance layer is, the lower the transmittance is; therefore, the transmittance of the edge part position is compensated by the first display electrode branches with smaller width at the edge part position, so that the transmittances of the edge part and the middle part tend to be consistent, the phenomenon of uneven transmittance of the array substrate is improved, the difference of chromaticity and brightness caused by inconsistent transmittance is avoided, the image quality display effect is improved, the product quality is improved, and the product structure is optimized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic view of a display panel of the present application;
FIG. 2 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic top view of a first display electrode according to an embodiment of the present application;
FIG. 4 isbase:Sub>A schematic cross-sectional view taken along A-A' of FIG. 2;
FIG. 5 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;
FIG. 6 is a schematic cross-sectional view of a second array substrate according to an embodiment of the present application;
FIG. 7 is a schematic top view of a three-array substrate according to an embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a three-array substrate according to an embodiment of the present application;
FIG. 9 is a process diagram of the array substrate of the present application;
FIG. 9a is a schematic structural diagram of a first stage of fabricating an array substrate according to the present application;
FIG. 9b is a structural diagram of a second stage of fabricating an array substrate according to the present application;
FIG. 9c is a schematic structural diagram of a third stage of fabricating an array substrate according to the present application;
fig. 9d is a schematic structural diagram of a fourth stage of preparing an array substrate according to the present application.
10, a display panel; 20. an array substrate; 210. a substrate; 220. scanning a line; 221. a pixel region; 230. a data line; 240. a color filter layer; 241. a first color resist layer; 242. an edge portion; 243. an intermediate portion; 244. a second resist layer; 250. a planarization layer; 260. a display electrode; 261. a first display electrode; 263. a second display electrode; 262. a third display electrode; 264. a display electrode branch; 270. a pixel electrode; 271. a pixel electrode branch; 278. a cross keel; 280. a common electrode; 281. a common electrode branch; 30. an opposing substrate; 40. and a liquid crystal layer.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless stated otherwise, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly and encompass, for example, both fixed and removable coupling as well as integral coupling; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
Fig. 1 is a schematic view of a display panel of the present application, and as shown in fig. 1, the present application discloses a display panel 10 including a counter substrate 30 and an array substrate 20, where the counter substrate 30 and the array substrate 20 are arranged in a pair of cells.
The display panel 10 of the present application may be a liquid crystal display panel 10, which may be a portable computer, a tablet computer, a mobile phone, a television, etc., the display panel 10 is composed of a counter substrate 30 and an array substrate 20, a liquid crystal layer 40 is further provided between the counter substrate 30 and the array substrate 20, liquid crystal deflection is realized by electric signal driving between the two substrates, a display screen, and the transmittance of the display panel 10 is uniform, the chromaticity and brightness presented at each angle are uniform, the image quality effect is good, the user experience is good, the display panel 10 may be a vertical alignment type (VA), an in-plane switching type (IPS), etc., the application is wide, and further the competitiveness of the product is strong.
The present application mainly aims at the improvement of the array substrate 20 in the display panel 10, which is as follows:
the first embodiment is as follows:
fig. 2 isbase:Sub>A schematic top view of an array substrate according to an embodiment of the present invention, fig. 3 isbase:Sub>A schematic top view ofbase:Sub>A first display electrode according to an embodiment of the present invention, fig. 4 isbase:Sub>A schematic cross-sectional view alongbase:Sub>A directionbase:Sub>A-base:Sub>A' of fig. 2, referring to fig. 2-4, the present invention discloses an array substrate 20 applied tobase:Sub>A display panel 10, the array substrate 20 includesbase:Sub>A substrate 210,base:Sub>A plurality of scan lines 220,base:Sub>A plurality of data lines 230,base:Sub>A color filter layer 240 andbase:Sub>A display electrode 260; the plurality of scan lines 220 and the plurality of data lines 230 are disposed on the substrate 210 and are arranged in a staggered manner to form a plurality of pixels, each pixel includes a display electrode 260, and the display electrode 260 includes a plurality of display electrode branches 264; the color filter layer 240 is provided with a plurality of color resist layers of different colors corresponding to pixels, the color resist layers include a first color resist layer 241, the first color resist layer 241 includes an edge portion 242 close to the data line 230 and a middle portion 243 far away from the data line 230, and the thickness of the edge portion 242 is greater than that of the middle portion 243 along the arrangement direction of the scanning lines 220; the display electrode 260 includes a first display electrode 261, the first display electrode 261 is disposed on the first color resist layer 241, and the first display electrode 261 includes a plurality of first display electrode branches; the width of the first display electrode branches corresponding to the edge portion 242 is smaller than the width of the first display electrode branches corresponding to the middle portion 243.
In terms of the scheme that the color resistance layer, especially the last color resistance layer formed, is prone to have a concave problem, so that the pixel transmittance of the color resistance layer is different, and the image quality is poor, the width of the first display electrode branch corresponding to different positions of the first color resistance layer 241 is adjusted, specifically, the width of the first display electrode branch is smaller than the width of the first display electrode branch corresponding to the middle portion 243 of the color resistance layer when the thickness of the color resistance layer is larger than the edge portion 242 of the first display electrode branch corresponding to the middle portion 243 of the color resistance layer, and when the thicknesses of the color resistance layers are the same, the smaller the width of the first display electrode branch is, the higher the transmittance is; when the width of the first display electrode branches is the same, the thicker the color resistance layer thickness is, the lower the transmittance is; therefore, at the position of the edge portion 242, the first display electrode branches with smaller width compensate for the transmittance at the position of the edge portion 242, so that the transmittances of the edge portion 242 and the middle portion 243 tend to be consistent, the phenomenon of uneven transmittance of the array substrate 20 is improved, the difference between chromaticity and brightness caused by the inconsistent transmittance is avoided, the image quality display effect is improved, the product quality is improved, and the structure of the product is optimized.
Moreover, the first display electrode branches disposed corresponding to the edge portion 242 gradually increase in width from a position close to the scan line 220 to a position away from the scan line 220 along the arrangement direction of the data lines 230.
Generally, not only along the arrangement direction of the scan lines 220, the first color resist layer 241 is concave, but also along the arrangement direction of the data lines 230, the first color resist layer 241 is concave, and therefore, the first display electrode branches corresponding to the edge portions 242 gradually increase from the width of the position close to the scan lines 220 to the width of the position far from the scan lines 220 along the arrangement direction of the data lines 230, so that the first display electrode branches are wide in the middle and gradually narrow towards two sides, thereby counteracting the problem that the transmittance of the first color resist layer 241 is low due to the fact that the thickness of the position close to the scan lines 220 is too large, and enabling the transmittances of the array substrate 20 to be consistent.
Specifically, the array substrate 20 further includes a planarization layer 250, the planarization layer 250 is disposed above the color filter layer 240, and the display electrode 260 is disposed on the planarization layer 250; and the thickness of the planarization layer 250 corresponding to the edge portion 242 is smaller than the thickness corresponding to the middle portion 243, so that the surface of the planarization layer 250 away from the color filter layer 240 is flush.
In this embodiment, the planarization layer 250 is formed above the color filter layer 240 to planarize the array substrate 20, and the thickness of the planarization layer 250 corresponding to the edge portion 242 of the first color resist layer 241 is smaller than the thickness of the middle portion 243, so that the upper surface of the planarization layer 250 (i.e., the surface of the planarization layer 250 away from the color filter layer 240) is flush, which is not only beneficial to forming the display electrode 260, making the thickness of the display electrode 260 uniform and enhancing the stability of the electric field, but also enables the thickness of the liquid crystal layer 40 to be uniform when the array substrate 20 forms the display panel 10 with respect to a box, thereby further improving the uniformity of image quality.
Fig. 4a is a graph showing the variation of transmittance and the width of the display electrode branch 264, fig. 4b is a graph showing the variation of transmittance and the thickness of the color-resist layer, and referring to fig. 4, the width of the first display electrode branch corresponding to the middle portion 243 is 1.5um to 3.0um; the width range of the first display electrode branch corresponding to the edge portion 242 is 1.0 um-2.0 um 。
In the present embodiment, the inventors of the present application have conducted experimental simulation with respect to the transmittance and the width of the display electrode branch 264, and the transmittance and the thickness of the color resist layer, and conducted many times verification during actual manufacturing, and normally the width of the display electrode branch 264 ranges from 1.0um to 3.0um in order to ensure normal liquid crystal driving, and as shown in fig. 4a, the wider the width of the display electrode branch 264, the lower the transmittance, and the normally the thickness of the color resist layer ranges from 1.4 μm to 4 μm, and as shown in fig. 4b (the abscissa is the decrease value of the film thickness of the middle portion of the color resist layer with respect to the film thickness of the edge portion, and the ordinate is the transmittance change value), the thicker the thickness of the color resist layer is, and the transmittance is lower because of the thickness at the position of the first color resist layer 241 is 0.2um to 0.5 μm greater than the thickness of the middle portion 243 due to the flatness of the color resist layer.
Preferably, the width of the first display electrode branches may be set to 1.5um to 3.0um corresponding to the position of the middle portion 243, and the width of the first display electrode branches may be reduced, specifically, set to 1.0um to 2.0um corresponding to the position of the edge portion 242 with low transmittance, so that the transmittances of the middle portion 243 and the edge portion 242 of the first color resist layer 241 tend to be consistent, thereby improving the image quality; it should be noted that the electrode width at the corresponding position plus the width of the adjacent empty area are kept consistent to ensure that the aperture ratio of the display panel is not changed.
Further, fig. 5 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure, and as shown in fig. 5, the color filter layer 240 further includes at least one second color resist layer 244, and the second color resist layer 244 has a uniform thickness along the arrangement direction of the scan lines 220; the display electrode 260 includes a third display electrode 262, the third display electrode 262 is disposed on the second color resist layer 244, and the third display electrode 262 includes a plurality of third display electrode branches; wherein the width of the third viewing electrode branch is equal to the width of the first viewing electrode branch disposed corresponding to the intermediate portion 243.
The color filter layer 240 is formed by color resist layers of three colors of red (R), green (G) and blue (B), the first color resist layer 241 is usually the last color resist layer formed, and is usually the B color resist layer, the color filter layer 240 further includes at least one second color resist layer 244, the second color resist layer 244 is a color resist layer formed before the first color resist layer 241, and may be an R and/or B color resist layer, and the second color resist layer 244 is usually uniform in thickness, does not have a significant degree of concavity or concavity, has a negligible effect on transmittance, and is perceived by human eyes as an indistinguishable image quality, so the transmittance of the array substrate 20 is determined based on the width of the third display electrode branches provided on the second color resist layer 244, so that the transmittance of the entire array substrate 20 is made uniform, or the width of the first display electrode branches of the edge portions 242 is set based on the width of the third display electrode branches provided on the second color resist layer 244, so that the transmittance of the first display electrode branches at the edge portions 242 is adjusted to be more uniform, and the transmittance of the second display electrode branches is further reduced by adjusting the width of the second color resist layer 242, and the second color resist layer 242 is further reduced by the second color resist layer 242.
Specifically, the display panel 10 is an in-plane switching (IPS) display panel 10, and the first display electrode 261 includes a pixel electrode 270 and a common electrode 280, including a plurality of pixel electrode branches 271; the common electrode 280 includes a plurality of common electrode branches 281, and the plurality of common electrode branches 281 and the plurality of pixel electrode branches 271 are alternately disposed at intervals and extend along the arrangement direction of the data lines 230 to form a horizontal electric field; among the plurality of pixel electrode branches 271, the width of the pixel electrode branch 271 disposed corresponding to the edge portion 242 is smaller than the width of the pixel electrode branch 271 disposed corresponding to the middle portion 243; and/or the common electrode branches 281 of the plurality of common electrode branches corresponding to the edge portions 242 have a width smaller than that of the common electrode branches corresponding to the middle portions 243.
In this embodiment, when the array substrate 20 is applied to the IPS display panel 10, the pixel electrode 270 and the common electrode 280 are both located on the color filter layer 240, and the pixel electrode branches 271 and the common electrode branches 281 are alternately arranged at intervals and extend along the arrangement direction of the data lines 230 to form a horizontal electric field to drive liquid crystal to deflect, at this time, the width of the pixel electrode branches 271 arranged at the edge portion 242 may be set to be smaller than the width of the pixel electrode branches 271 arranged at the middle portion 243 corresponding to the first color resist layer 241, and the width of the common electrode branches arranged at the edge portion 242 may be set to be smaller than the width of the common electrode branches arranged at the middle portion 243, so that the transmittances of the edge portion 242 and the middle portion 243 are consistent.
The second embodiment:
fig. 6 is a schematic cross-sectional view of a second array substrate according to an embodiment of the present invention, referring to fig. 6, in which the display panel 10 is a Fringe Field Switching (FFS) display panel 10, the first display electrode 261 includes a pixel electrode 270, and the pixel electrode 270 includes a plurality of pixel electrode branches 271; the display electrode 260 includes a second display electrode 263, the second display electrode 263 is disposed between the substrate 210 and the plurality of scan lines 220 and the plurality of data lines 230, the second display electrode 263 is a full-surface electrode, and forms a fringe field with the pixel electrode 270; of the plurality of pixel electrode branches 271, the width of the pixel electrode branch 271 disposed corresponding to the edge portion 242 is smaller than the width of the pixel electrode branch 271 disposed corresponding to the middle portion 243.
In this embodiment, the array substrate 20 is also applied to the FFS display panel 10, and different from the first embodiment, the first display electrode 261 includes a pixel electrode 270, the pixel electrode 270 includes a plurality of pixel electrode branches 271, the pixel electrode 270 is located on the color filter layer 240, the display electrode 260 further includes a second display electrode 263, the second display electrode 263 is located between the substrate 210 and the color filter layer 240, that is, located below the pixel electrode 270, the second display electrode 263 is a planar electrode and forms a fringe field with the pixel electrode 270, the second display electrode 263 can be a common electrode 280, and at this time, the common electrode 280 and the pixel electrode 270 are arranged in different layers, so that only the width of the pixel electrode branches 271 arranged corresponding to the edge portion 242 is set to be smaller than the width of the pixel electrode branches 271 arranged corresponding to the middle portion 243 to ensure that the transmittances are consistent.
Example three:
fig. 7 is a schematic top view of a three-array substrate according to an embodiment of the present invention, fig. 8 is a schematic cross-sectional view of the three-array substrate according to the embodiment of the present invention, and as can be seen from fig. 7 and 8, the display panel 10 is a Vertical Alignment (VA) display panel 10, the first display electrode 261 includes a pixel electrode 270, the pixel electrode 270 includes a cross-shaped keel 278 and a plurality of pixel electrode branches 271, and the plurality of pixel electrode branches 271 are all connected to the cross-shaped keel 278; the portion of the pixel electrode branch 271 corresponding to the edge portion 242 is an end portion, the portion of the pixel electrode branch 271 corresponding to the middle portion 243 is a middle portion, and the width of the end portion of the pixel electrode branch 271 is smaller than the width of the middle portion of the pixel electrode branch 271.
In this embodiment, the array substrate 20 is applied to the VA display panel 10, the first display electrode 261 includes a pixel electrode 270, the pixel electrode 270 may be in a "m" shape, and includes a cross-shaped keel 278 and a plurality of pixel electrode branches 271, the plurality of pixel electrode branches 271 are all connected to the cross-shaped keel 278, wherein the portion of the branch corresponding to the edge portion 242 is an end portion, the portion of the branch corresponding to the middle portion 243 is a middle portion, and the width of the end portion of the branch is smaller than the width of the middle portion of the branch, so that the width of the branch near the data line 230 or the scan line 220 is smaller than the width of the branch at the middle portion, thereby ensuring the transmittance to be consistent, and improving the image quality.
Generally, the pixel electrode 270 further includes a closed frame disposed outside the cross-shaped keel 278 and the plurality of pixel electrode branches 271, and the closed frame is in a shape of a Chinese character 'hui', so that the width of the closed frame at the position corresponding to the edge portion 242 can be changed, the width of the closed frame at the position close to the scan line 220 or the data line 230 is smaller than the width of the closed frame at the middle position, and the closed frame has a structure with a wide middle and two narrow sides, so as to ensure that the transmittance regions of the entire array substrate 20 are consistent.
Fig. 9 is a step diagram of a method for manufacturing an array substrate, and as can be seen from fig. 9, the present application further discloses a method for manufacturing an array substrate, which is used for manufacturing any one of the array substrates disclosed in the present application, and the method for manufacturing an array substrate includes the steps of:
s1, providing a substrate, sequentially preparing a plurality of scanning lines and a plurality of data lines on the substrate, and forming a plurality of pixel regions in a staggered mode;
s2, forming at least one second color resistance layer corresponding to the pixel region, and finally forming a first color resistance layer to form a color filter layer;
s3, forming a flat layer on the color filter layer;
s4, preparing a plurality of third display electrodes on the flat layer corresponding to the upper part of the second color resistance layer, preparing a plurality of first display electrodes corresponding to the upper part of the first color resistance layer, and forming a conductive layer so as to form pixels in the pixel area;
the width of the display electrode branch of the first display electrode arranged corresponding to the edge part of the first color resistor is smaller than the width of the display electrode branch of the first display electrode arranged corresponding to the middle part of the first color resistor.
Fig. 9a is a schematic structural diagram of a first stage of preparing the array substrate according to the present application, and referring to fig. 9a, a plurality of scan lines and a plurality of data lines are sequentially formed on a substrate on a pad by a series of processes such as film formation, photolithography, etching, and the like, and the plurality of scan lines and the plurality of data lines are staggered to form a plurality of pixel regions.
Fig. 9B is a schematic structural diagram of a second stage of the array substrate of the present application, and referring to fig. 9B, after the fabrication of the plurality of scan lines and the plurality of data lines is completed, a photoresist coating method is adopted to form a plurality of second color resist layers, and finally a first color resist layer is formed to form a color filter layer, when the color resist layers are fabricated in the color filter layer, a general fabrication sequence is to fabricate R, then G, and finally B, that is, the first color resist layer is a B color resist layer, and the second color resist layer is an R and/or G color resist layer, and due to leveling property of the color resist layers, a thickness of a middle portion of the first color resist layer is smaller than a thickness of an edge portion, and a thickness difference is usually 0.2um to 0.5um.
Fig. 9c is a schematic structural diagram of a third stage of the array substrate of the present application, and referring to fig. 9c, it can be seen that a flat layer is formed on the color filter layer by using a masking technique, and a halftone masking process is performed at a position corresponding to the first color resist layer, so that the thickness of the flat layer at the edge portion is smaller than that of the flat layer at the middle portion, and the upper surface of the flat layer is ensured to be flush.
Fig. 9d is a schematic structural diagram of a fourth stage of the array substrate of the present application, and referring to fig. 9d, a plurality of third display electrodes are prepared on the planarization layer by using processes such as film formation, yellow light, etching, and the like, corresponding to the second color resist layer, and a plurality of first display electrodes are prepared corresponding to the first color resist layer, so as to form a conductive layer, and a pixel electrode and/or a common electrode pattern is formed by using patterning processing, so as to form pixels in the pixel region, and widths of display electrode branches of the first display electrodes formed by using different patterning processing, specifically, a width of the display electrode branch of the first display electrode disposed corresponding to an edge portion of the first color resist is smaller than a width of the display electrode branch of the first display electrode disposed corresponding to a middle portion of the first color resist.
The width range of the first display electrode branch arranged corresponding to the middle part is 1.5 um-3.0 um; the width range of the first display electrode branch arranged corresponding to the edge part is 1.0 um-2.0 um, and the specific width can be adjusted in a pertinence manner according to the thicknesses of the middle part and the edge part in the first color resistance layer so as to ensure that the transmittance is consistent.
Specifically, in step S4, the third display electrode is formed to include a third pixel electrode and a third common electrode, and a plurality of third sub-pixel electrodes in the third pixel electrode and a plurality of third common sub-electrodes in the third common electrode are alternately arranged at intervals; the first display electrode comprises a first pixel electrode and a first common electrode, and a plurality of first sub-pixel electrodes in the first pixel electrode and a plurality of first common sub-electrodes in the first common electrode are alternately arranged at intervals.
As shown in fig. 9d, the third display electrode is formed to include a third pixel electrode and a third common electrode, the first display electrode includes a first pixel electrode and a first common electrode, and the third pixel electrode, the third common electrode, the first pixel electrode and the first common electrode are all in a comb-shaped structure to form a horizontal electric field, so that the array substrate can be applied to an IPS type display panel, and the plurality of pixel electrode branches and the plurality of common electrode branches are all parallel to the data lines, of course, the plurality of pixel electrode branches and the plurality of common electrode branches may also be in a V-shape.
In addition, when the first display electrode is only a pixel electrode and is applied to a VA display panel, the first display electrode may also be in a shape of a Chinese character 'mi', or in other shapes, and may be optimally designed according to scenes for different types of display panels, so as to improve transmittance and display quality.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
It should be noted that the inventive concept of the present application can form a great variety of embodiments, but the application documents are limited in space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after each embodiment or technical feature is combined, the original technical effect will be enhanced.
The technical scheme of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel, and all of them can be applied to the above scheme.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be considered as belonging to the protection scope of the present application.
Claims (6)
1. The array substrate is applied to a display panel and is characterized by comprising a substrate, a plurality of scanning lines, a plurality of data lines, a color filter layer and a display electrode;
the scanning lines and the data lines are arranged on the substrate and are staggered to form a plurality of pixels, each pixel comprises a display electrode, and each display electrode comprises a plurality of display electrode branches;
the color filter layer is provided with a plurality of color resistance layers with different colors corresponding to the pixels, each color resistance layer comprises a first color resistance layer, each first color resistance layer comprises an edge part close to the data line and a middle part far away from the data line, and the thickness of the edge part is larger than that of the middle part along the arrangement direction of the scanning lines;
the display electrode comprises a first display electrode, the first display electrode is arranged on the first color resistance layer, and the first display electrode comprises a plurality of first display electrode branches;
wherein the width of the first display electrode branch corresponding to the edge portion is smaller than the width of the first display electrode branch corresponding to the middle portion;
wherein the first display electrode branches compensate for the transmittance at the edge portion position so that the transmittances of the edge portion and the middle portion are the same;
the display panel is a planar conversion display panel, and the first display electrode includes:
a pixel electrode including a plurality of pixel electrode branches; and
the public electrode comprises a plurality of public electrode branches, the public electrode branches and the pixel electrode branches are alternately arranged at intervals and extend along the arrangement direction of the data lines to form a horizontal electric field;
among the plurality of pixel electrode branches, the width of the pixel electrode branch corresponding to the edge portion is smaller than the width of the pixel electrode branch corresponding to the middle portion;
and/or in the plurality of common electrode branches, the width of the common electrode branch corresponding to the edge part is smaller than that of the common electrode branch corresponding to the middle part.
2. The array substrate of claim 1, further comprising a planarization layer disposed over the color filter layer, the display electrode being disposed on the planarization layer;
and the thickness of the flat layer corresponding to the edge part is smaller than that of the flat layer corresponding to the middle part, so that the surface of the flat layer far away from the color filter layer is flush.
3. The array substrate of claim 1, wherein the color filter layer further comprises at least one second color resist layer, and the second color resist layer has a uniform thickness along the arrangement direction of the scan lines;
the display electrodes comprise third display electrodes, the third display electrodes are arranged on the second color resistance layer, and the third display electrodes comprise a plurality of third display electrode branches;
wherein a width of the third display electrode branch is equal to a width of the first display electrode branch disposed corresponding to the middle portion.
4. The array substrate of claim 1, wherein the first display electrode branches disposed corresponding to the edge portion gradually increase in width from a position close to the scan line to a position away from the scan line along the arrangement direction of the data lines.
5. A method for manufacturing an array substrate according to claims 1 to 4, the method comprising:
providing a substrate, sequentially preparing a plurality of scanning lines and a plurality of data lines on the substrate, and forming a plurality of pixel regions in a staggered manner;
forming at least one second color resistance layer corresponding to the pixel region, and finally forming a first color resistance layer to form a color filter layer;
forming a planarization layer on the color filter layer;
preparing a plurality of third display electrodes on the flat layer corresponding to the upper part of the second color resistance layer, and preparing a plurality of first display electrodes on the flat layer corresponding to the upper part of the first color resistance layer to form a conductive layer so as to form pixels in the pixel area;
the width of the display electrode branch of the first display electrode, which is arranged corresponding to the edge part of the first color resistor, is larger than the width of the display electrode branch of the first display electrode, which is arranged corresponding to the middle part of the first color resistor.
6. A display panel comprising an opposed substrate and the array substrate according to any one of claims 1 to 4, the opposed substrate and the array substrate being provided to a cell.
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