CN114338540B - Signal shunting method and device, electronic equipment and storage medium - Google Patents
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Abstract
The embodiment of the specification provides a signal shunting method, a signal shunting device, electronic equipment and a storage medium, which are applied to the technical field of segmentation verification of chip design, wherein the signal shunting method comprises the following steps: acquiring a network traffic map; determining a plurality of target signals to be shunted in a network flux map, wherein the target signals to be shunted are signals on a network with the weight smaller than a first threshold value; and shunting partial signals in the target signals to be shunted to other redundant networks, wherein the redundant networks are networks with the weight larger than a second threshold value, and the second threshold value is not smaller than the first threshold value. By dynamically configuring transfer paths for interconnection resources at an RTL level and carrying out signal shunting processing such as transferring and dredging on signals possibly in a congested network in a segmentation result, the communication flow of each area can be uniformly improved, so that the overall working frequency of the verification system is improved, the shunting processing is faster and more efficient, and the segmentation and verification efficiency in chip verification design is greatly improved.
Description
Technical Field
The invention relates to the technical field of chip design segmentation verification, in particular to a signal shunting method and device, electronic equipment and a storage medium.
Background
When verifying the segmentation result of the design of the super-large scale chip, a plurality of (for example, dozens or even hundreds of) verification chips are often required to form a verification system, and IO pins are used between the verification chips as interconnection resources between segmentation signals, so that the interconnection resources are scarce resources in the segmentation verification of the design of the large scale chip.
In an actual verification system, IO resources between verification chips need to be interconnected by using physical wires, as shown in fig. 1, signals a to d between the verification chip FPGA1 and the verification chip FPGA2 may be interconnected by a physical Cable _1, where a time division multiplexing ratio of the Cable _1 (i.e., TDMRatio is 4) and a time division multiplexing ratio of an interconnection line Cable _ n is m (m is a positive integer).
Therefore, when the communication pressure of a certain Cable is too high, the verification chip will operate at a lower operating frequency, that is, the operating frequency of the whole verification system may be affected by the communication pressure of the Cable and cannot meet the preset minimum operating frequency.
For example, in the implementation of interconnection by using TDM (time division multiplexing), too large TDM Ratio (time division multiplexing Ratio) will result in too long delay time, and the verification system cannot reach the minimum required operating frequency.
For example, in the networking of the verification chip, the segmentation result formed by the segmentation algorithm may not be reasonable and may be limited by the physical resource limit of the verification system, and even if the networking scheme corresponding to the segmentation result is continuously adjusted, the requirement of the verification system on working at the lowest working frequency may not be met.
In order to meet the minimum working frequency, chip design is required to be re-partitioned, re-laid out, networked and the like, and the partitioning and verification of large-scale chip design are greatly restricted, so that the partitioning and verification cannot be effectively carried out, and the marketing release of chips is influenced.
Therefore, a technical solution for effectively performing the segmentation verification on the chip design is needed.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a signal shunting method and apparatus, an electronic device, and a storage medium, which implement RTL-level signal shunting adjustment by processing a network traffic map, and improve the segmentation and verification efficiency of chip design.
The embodiment of the specification provides the following technical scheme:
the embodiment of the present specification provides a signal splitting method, which is applied to segmentation verification of chip design, and the signal splitting method includes:
acquiring a network traffic graph, wherein the network traffic graph is a graph formed by n nodes and m networks, the nodes correspond to grouping logics in the segmentation verification, the networks are physical interconnection networks in which the logical connection relation between the grouping logics is distributed in a verification system, and each network is marked with a corresponding weight which is used for representing the communication capacity of the network;
determining a plurality of target signals to be shunted in the network flux map, wherein the target signals to be shunted are signals on the network with the weight smaller than a first preset threshold value;
and shunting part of the target signals to be shunted to other redundant networks, wherein the redundant networks are networks with weights larger than a second preset threshold, and the second preset threshold is not smaller than the first preset threshold.
The embodiment of this specification further provides a signal shunting device, which is applied to the segmentation verification of chip design, and the signal shunting device includes:
the network traffic graph module is used for acquiring a network traffic graph, the network traffic graph is a graph formed by n nodes and m networks, the nodes correspond to grouping logics in the segmentation verification, the networks are physical interconnection networks in the verification system, the logical connection relations among the grouping logics are distributed in the verification system, each network is marked with a corresponding weight, and the weight is used for representing the communication capacity of the network;
the determining module is used for determining a plurality of target signals to be shunted in the network flux map, wherein the target signals to be shunted are signals on the network, and the weight of the signals is smaller than a first preset threshold value;
the distribution module is used for distributing partial signals in the target signals to be distributed to other redundant networks, wherein the redundant networks are networks with weights larger than a second preset threshold value, and the second preset threshold value is not smaller than the first preset threshold value.
An embodiment of the present specification further provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to: a signal splitting method as in any one of the embodiments of the present description.
Embodiments of the present specification also provide a computer storage medium storing computer-executable instructions configured to: a signal splitting method as in any one of the embodiments of the present description.
Compared with the prior art, the beneficial effects that can be achieved by the at least one technical scheme adopted by the embodiment of the specification at least comprise:
by dynamically configuring transfer paths for interconnection resources at an RTL level, and performing signal shunting processing such as transfer and dredging on signals possibly in a congestion network in a segmentation result, the communication flow of each area can be uniformly improved, and the overall working frequency of the verification system is improved; meanwhile, by carrying out signal shunting operation on an RTL level, the processing is quicker and more efficient, and the segmentation verification efficiency in the chip verification design is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of signal interconnections between verification chips in a verification system;
fig. 2 is a schematic structural diagram of a signal splitting scheme provided in an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a network traffic map in a signal splitting scheme provided in an embodiment of the present specification;
fig. 4 is a flowchart of a signal splitting method provided in an embodiment of the present specification;
fig. 5 is a schematic diagram of an RTL level code before splitting in a signal splitting method provided in an embodiment of the present specification;
fig. 6 is a schematic diagram of a local network traffic map before splitting in a signal splitting method according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of split RTL level code in a signal splitting method provided in an embodiment of the present specification;
fig. 8 is a schematic diagram of a local network traffic map after splitting in a signal splitting method according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a signal splitting device according to an embodiment of the present disclosure.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. The application is capable of other and different embodiments and its several details are capable of modifications and various changes in detail without departing from the spirit of the application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number and aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features described as being defined as "first," "second," etc., may explicitly or implicitly include one or more of the features. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
At present, in verifying a segmentation result of a chip design by using a verification system, in order to solve a bottleneck problem of an interconnection resource, there are several common methods:
firstly, the following scheme can be adopted without changing the transmission line of the split signal: (1) in the TDM implementation of interconnection multiplexing, the working frequency of a verification system is reduced, and the TDM Ratio of a congested network is increased, the scheme uses a simple form to increase the communication capacity of the congested network by sacrificing the working performance of the verification system, but causes great performance loss of the verification system; (2) the method comprises the following steps of changing physical networking of the verification system, rearranging and modifying a physical connection relation between verification chips (such as an FPGA (field programmable gate array), re-dividing a chip design and the like, wherein the scheme not only needs to consume a large amount of time to carry out networking adjustment and re-division, but also can cause new congestion of the verification system at other transmission path positions due to new networking, division results and the like, and cannot be fundamentally solved;
secondly, the current technical support situation of changing the transmission line of the split signal is as follows: when an interconnection relation required by a partition result which cannot be supported by a physical connection line occurs, for example, there is no physical connection line between the verification chip FPGA _ a and the verification chip FPGA _ B, but there is a logical connection line in the user design distributed to the FPGA _ a and the FPGA _ B, and at this time, a signal required to be transmitted by the logical connection line can be realized by a transit signal in the shortest path (the number of transit FPGAs passing through is minimum) between the FPGA _ a and the FPGA _ B, where there is a physical connection. However, the problems with this solution are: (1) the signal transmission line is changed only when the physical connection line does not support the segmentation result, but not for verifying the optimal system performance; (2) the fixed line is determined in the shortest path to change the transmission route, but the fixed line is often changed into a new congestion path, namely, a new congestion is caused in order to solve a congestion; (3) at present, only the circuit transfer at the netlist level is supported (i.e. the transfer route is changed), and no circuit transfer scheme at the RTL level is supported, but the RTL language of the large chip design is often converted into the netlist through a logic synthesis process for tens of hours, and the scale of the netlist expands sharply compared with the RTL design, so that the fast iteration and the efficiency need to be improved.
In view of this, after deep research and improved exploration are performed on the segmentation process and the verification process, a new technical scheme for splitting the segmentation signal in the verification system is provided: as shown in fig. 2, when a user design (i.e. a segmentation result corresponding to a chip design) is allocated to multiple verification chips (e.g. four FPGAs), each verification chip will be allocated to a part of the total design, so that the part of the user design allocated to each verification chip FPGA can be packaged as a grouping logic at RTL level, so that there are several signals that need to be logically interconnected between the grouping logics, and these interconnection signals can be allocated to a physical connection medium (e.g. a physical interconnection line Cable) existing between the verification chips in the verification system, thereby implementing signal interconnection transfer in segmentation verification. Therefore, when the signal of the logical interconnection between the grouped logics is distributed to a certain interconnection line Cable, which causes that the Cable communication pressure of the physical connection is too large, such as the TDM Ratio value is too large, or the logical interconnection between the grouped logics is a signal, and the logical connection relationship fails to have the physical connection (which can be understood as infinite communication pressure) supporting the logical connection relationship in the physical networking of the verification system, the interconnection signal of the type can be partially or completely shunted and transferred through other paths to realize the physical interconnection capable of meeting the requirement of the segmentation verification.
For example, if the communication pressure borne by the physical connection Cable _ n between the interconnection port pA of the verification chip FPGA1 and the interconnection port pB of the verification chip FPGA4 in fig. 2 is too large, that is, the Cable _ n becomes a congested network (also referred to as a congested path), at this time, part of signals (such as the original logical connection identified by the dotted line in the figure) that need to be transmitted through the Cable _ n may be "bypassed" through other networks with communication redundancy capability, so as to implement transfer and shunt of interconnection signals in grouping logic in the split verification, for example, corresponding ports and connections are created in the verification chips FPGA2 and FPGA3, for a certain logical interconnection connection between the ports pA and pB in the figure, transfer interconnection may be implemented through the newly added ports p1, p2, p3, p4 and the newly added logical connections a, b, c, d, and e, that is the newly added logical connections may be interconnected after transfer through the physical connection between the verification chips, the interconnection signals between the verification chip FPGA1 and the verification chip FPGA4 can work at a higher working frequency, so that after partial or all signals of a congestion network are transferred and shunted, the chip design does not need to be re-divided, the verification system can meet the requirement of the higher preset working frequency, the division and verification efficiency of the chip design is improved, and the chips can be released on the market after being verified in time.
It should be noted that, when a chip design (i.e., a division result corresponding to the chip design) is distributed to a plurality of verification chips in division verification, each verification chip is distributed to a part of the whole chip design, i.e., the whole chip design is verified after being divided, and logical connection relationships generally exist among the part of the designs, and these logical connection relationships need to be interconnected through a physical interconnection Cable in the verification system. Therefore, the part allocated to each verification chip can be designed and packaged as grouping logic at RTL level to form corresponding division results, and the logic connection relationship (or signals to be interconnected) exists between the division results. Therefore, the grouping logic (i.e. the verification chip corresponding to the verification system) can be used as the node (also called vertex) of the network traffic graph, the logic connection relation between the grouping logic required by the interconnection signal can be obtained, and the connection relationship of physical connection relationship between chips is verified in the verification system by the interconnection signal, which is used as the interconnection edge (also called as path, network, interconnection line Cable, etc.) between nodes in the network traffic map, wherein each edge can contain several interconnection signals, that is, several interconnection signals can be distributed to be transmitted in the same interconnection edge, and the communication capability (or communication pressure) of the interconnection edge is characterized by using the weight, that is, the network traffic graph may be a graph structure composed of nodes, paths and weights, so that the network traffic graph may be used to characterize the segmentation result of the whole chip design when the whole chip design is distributed to the verification system for segmentation verification.
For example, as shown in fig. 3, a certain chip design to be verified is assigned to the division results corresponding to the verification chips a to E in the verification system, so that these verification chips can be used as nodes of the network traffic map, the interconnection paths (for example, a plurality of signals are logically connected and/or physically connected to form an interconnection multiplexing path) existing between the verification chips are used as interconnection edges between the nodes, and the communication pressure of the interconnection paths is characterized by the weight of the edges, so that the entire network traffic map can be used to reflect the interconnection relationship after the division results are assigned to each verification chip, for example, the weight of the path between the verification chip a and the verification chip B is 2, the weight of the path between the verification chip a and the verification chip C is-3, and so on.
It should be noted that, the weight in the network traffic map is used to represent the communication capability of the network, so that the communication pressure of the network can be reflected by the size of the weight, wherein the value of the weight may be a positive value, a zero value, a negative value, and the like. Therefore, the weight can be compared with the threshold value, which paths have congestion and which paths do not have congestion can be quickly determined, and then the congested paths can be dynamically adjusted to be non-congested, so that the communication pressure of each path is in a bearable range, and the verification system can be ensured to work at a higher frequency.
In implementation, whether the network belongs to the congested network can be determined according to the following: when the RTL level obtains the segmentation result and distributes the segmentation result to the verification system for segmentation verification, whether the communication capability of the network in the segmentation result meets the preset requirement or not can be judged.
For example, in a verification system using TDM, it may be determined whether the TDM Ratio exceeds a preset Ratio threshold, for example, whether a corresponding physical interconnection network does not exist in a logical connection relationship.
Wherein, the Ratio threshold value can be solved reversely by the working frequency set by the system through the following formula: t istdm=(20+TDM Ratio/4 )/312.5。
Note that, T istdmThe unit of (1) is ns, which represents the time consumed for completing the signal transmission of one time of TDM Ratio number, and each signal transmits 1bit at one time; the unit of 312.5 in the formula is MHz, which is the fixed working frequency of the TDM module, and the TDM module can process 4bit data at a time with the frequency of 312.5 MHz; for TDM modules, a transceiving time of 20 clock cycles is required for processing data once: the transmitting end and the receiving end respectively need 3 TDM clock cycles, and the transmission needs to consume 14 TDM clock cycles at most. Therefore, when the TDM modules are used for multiplexing and interconnecting, if the operating parameters (such as operating frequency, required clock number, etc.) of the TDM modules are different from the foregoing description, the TMDRatio can be solved inversely according to the actual operating parameters, which is not limited herein.
Therefore, when the lowest operating frequency of the verification system is set to FminThen the maximum duty cycle of the system is Tmax = 1/FminThus, T can be convertedtdmCorresponding to the maximum duty cycle TmaxThen, the set system operating frequency is substituted into the above formula, so as to obtain the TDM Ratio maximum value corresponding to the verification system, that is, the maximum number of different signals that the physical interconnection line Cable can transmit in TDM, and further, the obtained maximum value can be used as a preset Ratio threshold value, and then the Ratio threshold value can be used for judging the communication pressure of each Cable, that is, the actual TDM Ratio of the Cable is compared with the Ratio threshold value, so as to obtain the actual CaThe communication pressure of the Cable, for example, if the actual TDMRatio of the Cable exceeds the preset Ratio threshold, it may be determined that the Cable belongs to the congested network.
It should be noted that a congested network (also referred to as a congested path, that is, a network may be a path, and will not be distinguished below) may refer to an interconnection network whose communication pressure exceeds a preset communication capability, for example, a physical interconnection Cable whose preset TDMRatio is 10, but whose current TDMRatio is 20, whose TDM Ratio is too high, that is, the communication capability exceeds the preset capability, so that the communication pressure is too high, and thus it may be determined as a congested network, for example, a congested network whose logical connection relationship is not supported by the physical interconnection network (that is, the communication capability of the network is abnormally small, or the communication pressure is abnormally large). Accordingly, an interconnection network with communication margin may be referred to as a non-congested network (also referred to as a redundant network, a redundant path), for example, a physical interconnection line Cable, where TDMRatio is preset to be 10, but if TDMRatio is currently 2, TDM Ratio of the Cable is not high, and there is more communication margin, communication pressure is small, and a redundant path may be provided for other signal communication (for example, communication redundancy of TDMRatio is 8).
The technical solutions provided by the embodiments in the present specification are described below with reference to the accompanying drawings.
The embodiment in the specification provides a signal shunting method applied to chip design segmentation verification, which is characterized in that signal shunting is performed on a segmentation result of a chip design on an RTL level, so that all paths in a network traffic diagram of the segmentation result are adjusted to be non-congestion paths, the signal transmission delay of a verification system is kept at a low level, the verification system can work at a high working frequency, the performance of the verification system is improved, and the efficiency of segmentation verification in the chip design is improved.
As shown in fig. 4, the signal splitting method includes:
step S202, obtaining a network traffic map, wherein the network traffic map is a map formed by n nodes and m networks, the nodes correspond to grouping logics in the segmentation verification, the networks are physical interconnection networks in the verification system, the logical connection relations among the grouping logics are distributed in the verification system, each network is marked with a corresponding weight, and the weights are used for representing the communication capacity of the network.
In implementation, the corresponding segmentation result of the chip design in the segmentation verification may be converted into a graph formed by vertices (which may also be referred to as nodes) and edges, that is, the network path graph is denoted as G = (V, E), where the set V represents a top set of vertices, the set E represents an edge set of interconnected edges, each edge is labeled with a corresponding weight Wi, i ∈ {1, 2, 3 … m }, m and n are positive integers, and Wi may be a positive value, a zero value, or a negative value, where the value of Wi is not limited.
The division result may be obtained by performing division processing on the chip design by using a preset division algorithm at an RTL level, that is, the division result is a part of the design allocated to each verification chip of the verification system after the chip design is allocated to the verification system in the division verification, and the RTL level code allocated to each verification chip may be divided into block code blocks, that is, grouping logic.
It should be noted that, the RTL level code logic allocated to the verification chip may be used as grouping logic, and the nodes and the network of the network traffic graph may characterize the relationship between these grouping logics, and the division of the RTL level code is not limited herein, and reference may be made to the related prior art.
After the segmentation result is obtained, the grouping logic can be turned into a graph. As shown in fig. 5, the top-level grouping logic in split verification, which may correspond to the entire network traffic graph, corresponds to the FPGA1, the FPGA2, the FPGA3, and the like, and the interconnection lines between the verification chips, such as cable1 and cable2, may correspond to the network in the network traffic graph (as illustrated by the partial network in fig. 6). It should be noted that, the process of converting the grouping logic into the network traffic map is not limited here.
By dividing the RTL level code of the chip design into the grouping logics corresponding to the verification system and representing the grouping logics by adopting the network traffic diagram, the dynamic equalization adjustment processing of the communication capacity of the interconnection line between the verification chips can be conveniently carried out through the network traffic diagram.
Step S204, determining a plurality of target signals to be shunted in the network flux map, wherein the target signals to be shunted are signals on the network with the weight smaller than a first preset threshold value.
As in the foregoing example, the weight reflects the magnitude of the communication capability (or the communication pressure) of the network, so that several signals to be distributed may be determined from the network traffic map, for example, signals in the network with high communication pressure, for example, the logical connection relationship of the signals does not have a corresponding physical connection network in the verification system, and so on, i.e., after the logical connection relationship of the target signal is distributed to the verification system, the corresponding physical connection network may not meet the preset performance requirement, and thus the signals in these networks may need to be partially or completely distributed to other networks.
The communication pressure condition of the network can be quickly judged through the weight, namely whether the network is congested or not is determined. In the method, part or all of the signals in the network with the weight less than the first preset threshold may be determined as target signals, while the signals in the network with the weight not less than the second preset threshold may be determined as non-target signals, or the network with the weight not less than the second preset threshold may be determined as a non-congested network (also referred to as a redundant path, a redundant network, etc.), so as to facilitate shunting and adjusting part of the signals in the congested network to the non-congested network.
Step S206, shunting a part of the target signals to be shunted to other redundant networks, where the redundant networks are networks whose weights are greater than a second preset threshold, and the second preset threshold is not less than the first preset threshold.
In the implementation, part of signals (namely target signals) on the congested network can be partially shunted to the uncongested network, and after shunting, the communication pressure of each network in the network traffic diagram is dynamically adjusted to a bearable range, so that the verification system can work at a higher working frequency.
It should be noted that, part of the signals in the congested network may be distributed to the same non-congested network, or may be distributed to different non-congested networks, which is not limited herein.
It should be noted that the value of the first preset threshold and/or the second preset threshold may be preset and adjusted according to the actual application requirement. For example, in the foregoing embodiment, when the difference between TDMRatio and the predetermined Ratio is used as the weight, both the first predetermined threshold and the second predetermined threshold may be set to be zero, that is, a network with a weight smaller than zero is a congested network, signals on the congested network may need to be shunted, a path with a weight larger than zero is a non-congested network, and the non-congested network can bear signal shunting of other congested networks.
Through the steps S202 to S206, after the segmentation result corresponding to the RTL level code is obtained, the segmentation result is converted into the network traffic map, the segmentation scheme and the networking scheme do not need to be adjusted repeatedly, and only the transit path for signal shunting is dynamically selected from the network traffic map according to the network congestion degree corresponding to the segmentation result, and the signal of the congested network is shunted to the non-congested network for shunting and dredging, so that the communication smoothness degree of each area is improved in a balanced manner, and the overall working frequency of the verification system is improved; meanwhile, signal shunting is based on RTL level shunting, the operation is quicker and more efficient, and the segmentation and verification efficiency of chip design is greatly improved.
In some embodiments, the communication pressure of each network can be dynamically equalized by determining a plurality of transit paths in the network traffic map, and then shunting the signals to be shunted to each transit path according to the shunting scheme.
In implementation, splitting part of the signals to be split into the other redundant paths may include: firstly, determining a source node corresponding to an input port of the partial signal and a target node corresponding to an output port of the partial signal; then, determining transit links (also called transit paths) in the network traffic graph, wherein the transit links comprise transit nodes and transit networks for communication between the source node and the target node, and the transit networks are redundant networks; and finally, shunting part of the target signals to be shunted through the transit link.
It should be noted that, after a plurality of transit paths are determined in the network traffic diagram, the signal to be split may be split to the transit paths according to a preset splitting policy, where the splitting policy may be a shortest path, a maximum network flux, and the like, and may be specifically preset according to the actual application needs, and this is not limited herein.
In some embodiments, the transit path may be determined from the network traffic map using a breadth-first search algorithm and a depth-first search algorithm. Preferably, a breadth first search algorithm may be employed such that the path of each split may be the shortest path.
It should be noted that, the breadth-first search algorithm and the depth-first search algorithm applied in the graph processing may be implemented by using corresponding search algorithms, which is not limited herein.
In some embodiments, the determination of the transit path can be realized by adopting a data structure of the queue, so that the determination process is simplified, and the processing efficiency is improved.
In one embodiment, queue processing may proceed as follows: firstly, a first access queue is established and initialized; then, sequentially adding the source node, a plurality of neighbor nodes and the target node into the first access queue, recording precursor nodes corresponding to the neighbor nodes in the first access queue, and marking access states corresponding to the nodes in the first access queue as accessed, wherein the neighbor nodes are nodes with at least one redundant network corresponding to the precursor nodes, and the precursor nodes are nodes which cause the neighbor nodes to be added into the first access queue; and finally, determining a transit link in the first access queue in a reverse direction, wherein a precursor link is determined from the target node to the source node in the reverse direction so as to serve the precursor link as the transit link.
For example, in the aforementioned example shown in fig. 3, the source node is a, the destination node is C, the network AC is a congested network, the communication pressure to be shunted is 3, wherein the communication margin of the network from node a to node B is 2, the communication margin of the network from node a to node D is 5, and so on. At this time, node a is enqueued, then node B, D with a redundant network is enqueued, then node C with node B redundant network is enqueued, node E with node D redundant network is enqueued, and finally node C with node E redundant network is enqueued (node C has already been enqueued, but this time an effective distinction can be achieved by recording the predecessor node to which this C is enqueued). Thus, two transit links can be found, where the first transit link is: node A to node B, and node B to node C, which may be denoted as transit link ABC; the second transit link: node a to node D, node D to node E, and node E to node C may be denoted as transit link ADEC.
The precursor nodes corresponding to the nodes entering the queue are recorded, the precursor nodes of the nodes entering the queue are effectively distinguished, when a transfer path is determined, precursor node chains between a target node and a source node can be obtained by reversely needing the precursor nodes from the target node, and the found precursor node chain reverse chains are used as transfer links.
In one embodiment, queue processing may proceed as follows: firstly, creating and initializing a second access queue, wherein the second access queue is a first-in first-out queue, initializing the source node as a queue head element, and marking the access state of the source node as accessed; then, adding neighbor nodes with at least one redundant network existing in the node of the queue head element into the access queue, marking the access state corresponding to each neighbor node in the second access queue as accessed, and recording precursor nodes corresponding to each neighbor node in the second access queue; then, after each neighbor node is added to the second access queue, whether a target node exists in the queue is judged, and queue operation is performed according to the judgment result, that is, if the target node exists in the second access queue, precursor nodes are sequentially enumerated from the target node to the source node, a precursor node chain is formed, and then the precursor node chain is determined to be a transit link; and if the target node does not exist in the second access queue, popping up an original queue head element in the second access queue, and taking an original second element of the second access queue as a new queue head element.
For example, in the example shown in FIG. 3, node A is queued as the head element, and then node B, D, which has a redundant network with A, is queued, where the target node C is not present in the queue. Therefore, it is necessary to continue the next round of queue operation, that is, pop the node a out of the queue, and since the queue is first in first out, after the node a pops up, the node B is used as a queue head element (assuming that the node B is queued before the node D), and continue to queue the node C having a redundant network with the node B, and thus there is a target node C in the queue, and therefore, the node C starts to trace back the predecessor nodes of the respective nodes, so as to find the predecessor node chain: node C, node B, node a, so the forward node chain can be reversed to obtain a transit link: node a to node B, node B to node C, may be denoted as transit link ABC.
In some embodiments, in the queue operation, when the transit path is not found but the queue is empty, it indicates that there is no physically reachable path with communication capability redundancy between the source node and the target node in the verification system, i.e. there is no redundant network capable of undertaking signal splitting. And at the moment, stopping the shunting processing, and outputting prompt information, wherein the prompt information is used for representing that a transit link does not exist, so that the user who performs segmentation verification can conveniently perform subsequent processing according to the prompt information.
For example, when the original queue head element in the second access queue is popped up, the second access queue is empty, which indicates that the transit link cannot be found, and then the prompt message is output.
In some embodiments, the network weights may be dynamically adjusted as the semicolons are shunted to the redundant networks.
In practice, for other redundant networks that are under the burden of offloading, the network weights may be adjusted as follows: firstly, determining a weight adjustment value of the other redundant networks, wherein the weight adjustment value is used for representing the influence degree of the partial signals on the communication capacity of the other redundant networks when the partial signals are shunted to the other redundant networks; then, the weights of the other redundant networks are updated according to the weight adjustment value.
For example, the relay link ABC in the foregoing embodiment may shunt the signal shunt with the communication capability of 2, and then may determine the weight adjustment value of the network AB to be 2, and then may adjust the weight of the network AB to be zero (i.e., the network AB no longer has communication margin) after the communication capability of the network AB to shunt is 2.
In implementation, the weights may be dynamically adjusted for the congested network being shunted. For example, after the transit link ABC assumes a split communication capability of 2, the weight of the congested network AC may be adjusted to-1.
In some embodiments, assuming that the network traffic graph G = (V, E), which includes n nodes, m edges, where the edge has a corresponding weight Wi, i ∈ {1, 2, 3 … m }, and m and n are positive integers, the signal splitting process may be implemented by using the following queue operation:
and (1) taking the edge ei with the minimum weight Wi, wherein two end points of the edge ei are Node _ A and Node _ B respectively. Wi is the minimum, that is, the number of signals to be shunted is the maximum, that is, the number of signals to be shunted is correspondingly marked as Num _ bypass. In practice, Wi requires shunting for negative number characterization.
And (2) establishing and initializing an access queue (queue) to be empty, adding Node _ A into the queue as a queue head element Nodetop, and marking the Node as accessed. In implementation, the queues use a first-in first-out data structure.
And (3) pressing the neighboring nodes which have a connection relation with the queue head element Nodetop and have the weight larger than zero and are not accessed into the queue according to a preset numbering sequence, and marking all the pressed neighboring nodes as accessed. In the implementation, a predecessor Node of each adjacent Node in the current push queue is recorded, the predecessor Node is a Node leading the predecessor Node to enter the queue, for example, Node _ a is connected with Node _ n, and at this time, Node _ a is used as a queue head element Node top and is also used as a predecessor Node of Node _ n. It should be noted that the preset numbering sequence of the nodes may be preset in the network traffic map modeling, and is not limited herein.
And (4) if the Node _ B appears in the queue, sequentially listing the precursor nodes from the Node _ B to form a precursor Node chain till the Node _ A, wherein if the Node chain exists, the chain is a transfer path. In addition, in the transit path searching, the minimum value Wmin of the edge weight passing through the edge is the maximum semaphore which can be shunted through the transit path; after determining the transit path, the edge weight Wi of the edge ei with the minimum Wi in the step (1) can be modified to be Wi + Wmin, and the edge weight of each edge on the transit path is subtracted by Wmin; finally, according to the transit path, a port and a connection are newly built in the user RTL level code design, corresponding Wmin signals are transited, wherein the operation of shunting the transit signals in the RTL level code is described in the relevant description in the specification. This means that the transit path helps the congested network ei to shunt Wmin signals. And (4) returning to the step (1) to continue executing until all the edge weights in the network traffic graph G are not less than 0, namely all the congested networks are shunted, or the shunted signals cannot find a corresponding redundant network for shunting, and ending the algorithm.
And (5) if the Node _ B does not exist in the queue, popping up the head element of the queue, taking a Node behind the original head element as a new head element Node top, and executing the step (3). If no neighbor Node introducing queue meeting the condition is found after popping the head element of the queue, and the queue is empty at the moment, the signal of the congested network cannot exist in a redundant network for shunting, the shunting processing can be terminated, and no physical reachable path or any path capable of shunting does not exist between the Node _ A and the Node _ B is reported.
In some embodiments, when the target signal to be shunted is shunted to the transit path, the signal shunting operation may be implemented on the RTL level code by modifying the grouping logic (i.e., the RTL level code) corresponding to each verification chip.
With the foregoing examples as illustrated in fig. 5 and 6, a bypass operation may be performed on RTL level code.
As shown in FIG. 7, the code modification operation may be completed on RTL level code in the following steps:
step (1), acquiring a source FPGAN _ instance _ source and a target FPGAN _ instance _ target, wherein the instances are fpga1_ instance and fpga3_ instance; acquiring a signal name to be transferred, wherein the signal name is assumed as cable1 in an illustration; the transfer path obtained in the shunting algorithm is obtained, in the illustration, the transfer path is FPGA1- > FPGA2- > FPGA3, and the FPGA2 is a transfer FPGA. It should be noted that, in this embodiment, there is one FPGA2, and the number of relay FPGAs in other embodiments may be greater than 1.
And (2) for each transfer FPGA, newly building transfer input and output ports, such as bridge _ in and bridge _ out in an illustration diagram, in the grouping design of the transfer FPGA, and connecting the two ports in the FPGA by using an assign statement in the module of the transfer FPGA.
Step (3), a transfer connecting line is newly established in the top module, such as cable _ bridge; and inputting an original output signal such as cable1 into a newly-built input port of an instance corresponding to the transit FPGA, and outputting an output port of the transit instance through a newly-built transit connecting line in the top module. It should be noted that, if a next transfer FPGA exists on the transfer path, the step (3) is repeated; if the target FPGAN _ instance _ target does not exist, the connection line is output to the input port of the target FPGAN _ instance _ target, and the transfer is completed.
As shown in fig. 8, cable1 realizes communication connection after signal shunting after passing through relay FPGA 2. It should be noted that only the signal splitting path is shown in the figure, and other networks are not shown in the figure.
Based on the same inventive concept, the embodiments of the present specification further provide a signal shunting device, which corresponds to the signal shunting method and can be applied to the segmentation verification of chip design, that is, in a segmentation verification system.
As shown in fig. 9, the signal splitting device 100 includes: a network traffic graph module 101, configured to obtain a network traffic graph, where the network traffic graph is a graph formed by n nodes and m networks, the nodes correspond to grouping logics in a segmentation verification, the networks are physical interconnection networks in which logical connection relationships between the grouping logics are distributed in a verification system, and each network is marked with a corresponding weight, where the weight is used to characterize communication capability of the network; a determining module 103, configured to determine a plurality of target signals to be split in the network traffic map, where the target signals to be split are signals on a network whose weight is smaller than a first preset threshold; the shunting module 105 is configured to shunt part of the signals in the target signals to be shunted to other redundant networks, where the redundant networks are networks whose weights are greater than a second preset threshold, and the second preset threshold is not less than the first preset threshold.
Optionally, in the signal splitting device 100, splitting a part of the signals of the target signals to be split into other redundant paths includes:
determining a source node corresponding to an input port of the partial signal and a target node corresponding to an output port of the partial signal;
determining transit links in the network traffic map, wherein the transit links comprise transit nodes and transit networks for communicating between the source node and the target node, and the transit networks are redundant networks;
and shunting part of the target signals to be shunted through the transit link.
Optionally, in the signal splitting apparatus 100, determining a transit link in the network traffic map includes: and determining a transit link in the network traffic map by adopting a breadth-first search algorithm.
Optionally, in the signal splitting device 100, splitting a part of the signals in the target signals to be split through the relay link, including:
determining grouping logics corresponding to the source node, the target node and the transit node respectively;
creating a transit connection line corresponding to the transit network in a top-level logic, sequentially creating a transit input port and a transit output port corresponding to the transit network in the transit node in a grouping logic corresponding to the transit node, and internally interconnecting the transit input port and the transit output port of the transit node in the grouping logic corresponding to the transit node, wherein the top-level logic is a previous-level grouping logic corresponding to the grouping logics corresponding to the source node, the target node and the transit node;
in the top logic, the output port of the partial signal is connected to the transit input port of the first transit node on the transit link, the transit output port of the previous transit node on the transit link is connected to the transit input port of the next transit node, and the transit output port of the last transit node is connected to the input port of the destination node.
Optionally, in the signal splitting device 100, determining a transit link in the network traffic map includes:
creating and initializing a first access queue;
sequentially adding the source node, a plurality of neighbor nodes and the target node into the first access queue, recording precursor nodes corresponding to all the neighbor nodes in the first access queue, and marking access states corresponding to all the nodes in the first access queue as accessed, wherein the neighbor nodes are nodes with at least one redundant network corresponding to the precursor nodes, and the precursor nodes are nodes which cause the neighbor nodes to be added into the first access queue;
and determining a transit link in the first access queue in a reverse direction, wherein a precursor link is determined in the reverse direction from the target node to the source node, and the precursor link is used as the transit link.
Optionally, in the signal splitting device 100, determining a transit link in the network traffic map includes:
creating and initializing a second access queue, wherein the second access queue is a first-in first-out queue, initializing the source node as a queue head element, and marking the access state of the source node as accessed;
adding neighbor nodes with at least one redundant network existing in the node of the queue head element into the access queue, marking the access state corresponding to each neighbor node in the second access queue as accessed, and recording precursor nodes corresponding to each neighbor node in the second access queue;
after each neighbor node is added to the second access queue, if the target node exists in the second access queue, sequentially enumerating predecessor nodes from the target node to the source node, forming a predecessor node chain, and then determining the predecessor node chain as a transit link; if the target node does not exist in the second access queue, popping up an original queue head element in the second access queue, and taking an original second element of the second access queue as a new queue head element.
Optionally, the signal splitting device 100 further includes: and a prompt module (not shown in the figure), wherein the prompt module is configured to output prompt information when the second access queue is empty after popping up the original queue head element in the second access queue, and the prompt information is used to indicate that the transit link does not exist.
Optionally, the signal splitting device 100 further includes: an adjusting module (not shown in the figure), wherein the adjusting module is configured to determine a weight adjustment value of the other redundant network, the weight adjustment value being used to characterize a degree of influence of the partial signal on communication capability of the other redundant network when being shunted to the other redundant network, and update the weight of the other redundant network according to the weight adjustment value.
Based on the same inventive concept, embodiments of the present specification further provide an electronic device for signal splitting in segmentation verification, so as to implement a signal splitting scheme corresponding to any one of the foregoing embodiments.
The electronic device may include: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions that are executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the signal splitting method according to any one of the foregoing embodiments, which may specifically refer to the foregoing description of the embodiments of the electronic device, and a description thereof is not repeated here.
Based on the same inventive concept, embodiments of the present specification further provide a computer storage medium for signal splitting in segmentation verification, where the computer storage medium stores computer-executable instructions configured to: and instructions for implementing the signal splitting method corresponding to any of the foregoing embodiments.
Note that, the description of the computer storage medium may specifically refer to the description of the foregoing embodiments, and will not be further described here.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments described later, since they correspond to the previous embodiments, the description is simple, and the relevant points can be referred to the partial description of the previous embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A signal shunting method is applied to segmentation verification of chip design, and comprises the following steps:
acquiring a network traffic graph, wherein the network traffic graph is a graph formed by n nodes and m networks, the nodes correspond to grouping logics in the segmentation verification, the networks are physical interconnection networks in which the logical connection relation between the grouping logics is distributed in a verification system, and each network is marked with a corresponding weight which is used for representing the communication capacity of the network;
determining a plurality of target signals to be shunted in the network flux map, wherein the target signals to be shunted are signals on the network with the weight smaller than a first preset threshold value;
and shunting part of the target signals to be shunted to other redundant networks, wherein the redundant networks are networks with weights larger than a second preset threshold, and the second preset threshold is not smaller than the first preset threshold.
2. The signal splitting method according to claim 1, wherein splitting some of the target signals to be split into other redundant paths includes:
determining a source node corresponding to an input port of the partial signal and a target node corresponding to an output port of the partial signal;
determining transit links in the network traffic map, wherein the transit links comprise transit nodes and transit networks for communicating between the source node and the target node, and the transit networks are redundant networks;
and shunting part of the target signals to be shunted through the transit link.
3. The signal splitting method of claim 2, wherein determining a transit link in the network traffic map comprises: and determining a transit link in the network traffic map by adopting a breadth-first search algorithm.
4. The signal splitting method according to claim 2, wherein splitting a part of the target signals to be split through the transit link includes:
determining grouping logics corresponding to the source node, the target node and the transit node respectively;
creating a transit connection line corresponding to the transit network in a top-level logic, sequentially creating a transit input port and a transit output port corresponding to the transit network in a grouping logic corresponding to the transit node, and internally interconnecting the transit input port and the transit output port of the transit node in the grouping logic corresponding to the transit node, wherein the top-level logic is a previous-layer grouping logic corresponding to the grouping logics corresponding to the source node, the target node and the transit node;
in the top logic, the output port of the partial signal is connected to the transit input port of the first transit node on the transit link, the transit output port of the previous transit node on the transit link is connected to the transit input port of the next transit node, and the transit output port of the last transit node is connected to the input port of the destination node.
5. The signal splitting method of claim 2, wherein determining a transit link in the network traffic map comprises:
creating and initializing a first access queue;
sequentially adding the source node, a plurality of neighbor nodes and the target node into the first access queue, recording precursor nodes corresponding to all the neighbor nodes in the first access queue, and marking access states corresponding to all the nodes in the first access queue as accessed, wherein the neighbor nodes are nodes with at least one redundant network corresponding to the precursor nodes, and the precursor nodes corresponding to the neighbor nodes are nodes which cause the neighbor nodes to be added into the first access queue;
and determining a transit link in the first access queue in a reverse direction, wherein a precursor link is determined in the reverse direction from the target node to the source node so as to be used as the transit link.
6. The signal splitting method of claim 2, wherein determining a transit link in the network traffic map comprises:
creating and initializing a second access queue, wherein the second access queue is a first-in first-out queue, initializing the source node as a queue head element, and marking the access state of the source node as accessed;
adding neighbor nodes with at least one redundant network to the access queue, marking the access state corresponding to each neighbor node in the second access queue as accessed, and recording precursor nodes corresponding to each neighbor node in the second access queue, wherein the neighbor nodes are nodes with at least one redundant network corresponding to the precursor nodes, and the precursor nodes corresponding to the neighbor nodes are nodes causing the neighbor nodes to be added to the second access queue;
after each neighbor node is added to the second access queue, if the target node exists in the second access queue, sequentially enumerating precursor nodes from the target node to the source node, forming a precursor node chain, and determining the precursor node chain as a transit link; and if the target node does not exist in the second access queue, popping up an original queue head element in the second access queue, and taking an original second element of the second access queue as a new queue head element.
7. The signal splitting method according to claim 6, further comprising:
and when the original queue head element in the second access queue is popped up and the second access queue is empty, outputting prompt information, wherein the prompt information is used for representing that a transfer link does not exist.
8. The signal splitting method according to claim 1, wherein the signal splitting method further comprises:
determining a weight adjustment value of the other redundant network, wherein the weight adjustment value is used for representing the influence degree of the partial signal on the communication capacity of the other redundant network when the partial signal is shunted to the other redundant network;
and updating the weights of the other redundant networks according to the weight adjustment value.
9. A signal shunting device is applied to the segmentation verification of chip design, and comprises:
the network traffic graph module is used for acquiring a network traffic graph, the network traffic graph is a graph formed by n nodes and m networks, the nodes correspond to grouping logics in the segmentation verification, the networks are physical interconnection networks in the verification system, the logical connection relations among the grouping logics are distributed in the verification system, each network is marked with a corresponding weight, and the weight is used for representing the communication capacity of the network;
the determining module is used for determining a plurality of target signals to be shunted in the network flux map, wherein the target signals to be shunted are signals on the network, and the weight of the signals is smaller than a first preset threshold value;
the distribution module is used for distributing part of the signals in the target signals to be distributed to other redundant networks, wherein the redundant networks are networks with weights larger than a second preset threshold, and the second preset threshold is not smaller than the first preset threshold.
10. An electronic device, comprising:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to: a method of signal splitting as claimed in any one of claims 1 to 8.
11. A computer storage medium having computer-executable instructions stored thereon, the computer-executable instructions configured to: a method of signal splitting as claimed in any one of claims 1 to 8.
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