CN114338318B - Signal receiving and decoding method and device - Google Patents
Signal receiving and decoding method and device Download PDFInfo
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- CN114338318B CN114338318B CN202111371825.0A CN202111371825A CN114338318B CN 114338318 B CN114338318 B CN 114338318B CN 202111371825 A CN202111371825 A CN 202111371825A CN 114338318 B CN114338318 B CN 114338318B
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Abstract
The application provides a signal receiving and decoding method and a device, wherein the method comprises the following steps: a comparator array is adopted to respectively compare Pulse Amplitude Modulation (PAM) voltage signals with a plurality of reference voltages with a first preset number, and a plurality of paths of time sequence signals with the first preset number are obtained, wherein the plurality of paths of time sequence signals are used for representing comparison results of the comparison; and decoding the multi-channel time sequence signals to obtain multi-channel NRZ signals with the number of second preset numbers. According to the application, the PAM voltage signal is compared with a plurality of reference voltages in an analog domain to obtain a plurality of paths of time sequence signals, so that the introduction of an analog-to-digital converter and a tapping device module with complicated structures and high power consumption is avoided, the circuit system architecture is simplified, the power consumption of the circuit system is reduced, and the PAM signal receiving and decoding method is suitable for receiving and decoding PAM4 and PAM signals with higher orders.
Description
Technical Field
The present application relates to the field of optical communications technologies, and in particular, to a method and an apparatus for receiving and decoding signals.
Background
With the continuous popularization and maturity of cloud computing, internet of things, photoelectric information processing technology, artificial intelligence technology and 5G mobile communication technology (5 th Generation Mobile Communication Technology), data centers will face the situation of explosive growth of traffic, which further increases the requirements on transmission rate. If a conventional Non-Return-to-Zero (NRZ) signal is used, the time margin requirements for the transceiver chip and the transmission link are very stringent, and the loss of the channel to the high bandwidth signal is significantly increased.
In response to the above difficulties and challenges, the introduction of multi-level modulation schemes is a potential and efficient method, such as eight-order pulse amplitude modulation (PAM 8) transmission signals. The existing receiving end circuit for realizing the pulse amplitude modulation signal adopts an analog-to-digital converter and a tapping device module with complex structure and high power consumption, and has the challenges of complexity, power consumption and the like of a circuit system when the PAM4 signal demodulation is realized, so that the circuit is not suitable for realizing the PAM signal demodulation with higher order number.
Disclosure of Invention
The application provides a signal receiving and decoding method and device, which are used for solving the defects of complex circuit structure and high power consumption of a PAM signal receiving end in the prior art and realizing the receiving and decoding of PAM4 and higher-order PAM signals.
In a first aspect, the present application provides a signal reception decoding method, including:
a comparator array is adopted to respectively compare Pulse Amplitude Modulation (PAM) voltage signals with a plurality of reference voltages with a first preset number, and a plurality of paths of time sequence signals with the first preset number are obtained, wherein the plurality of paths of time sequence signals are used for representing comparison results of the comparison;
decoding the multi-channel time sequence signals to obtain multi-channel non-return-to-zero NRZ signals with the number of second preset numbers;
wherein the first preset number and the second preset number are determined based on the number of levels of PAM.
Optionally, according to the signal receiving and decoding method provided by the present application, the comparing the PAM voltage signal with a plurality of reference voltages with a first preset number to obtain a plurality of paths of timing signals with the first preset number includes:
sequentially adopting one of comparison operators in the comparator array to compare the PAM voltage signal with target reference voltages which are in one-to-one correspondence with the comparison operators in the plurality of reference voltages, and acquiring one of the plurality of paths of time sequence signals until the first preset number of paths of time sequence signals are acquired;
the comparator array comprises a biaser and a plurality of comparison operators with the first preset number, wherein the biaser is used for generating a bias voltage and the plurality of reference voltages.
Optionally, according to the signal receiving and decoding method provided by the present application, the comparing the PAM voltage signal with a target reference voltage corresponding to the comparison operator one by one in the plurality of reference voltages, to obtain one of the plurality of timing signals includes:
amplifying the PAM voltage signal and the target reference voltage based on the bias voltage to obtain an amplified PAM voltage signal and an amplified target reference voltage;
comparing the amplified PAM voltage signal with the amplified target reference voltage to obtain a first signal, wherein the first signal is used for representing a comparison result of the size;
amplifying the first signal to obtain the one-path time sequence signal.
Optionally, according to the signal receiving and decoding method provided by the present application, the decoding the multiple paths of time sequence signals to obtain multiple paths of non-return-to-zero NRZ signals with a number being a second preset number includes:
eliminating time delay of the multi-path time sequence signals and obtaining synchronous multi-path time sequence signals;
and carrying out logic judgment on the synchronous multipath time sequence signals to obtain multipath NRZ signals.
Optionally, the signal receiving and decoding method provided by the application further includes:
converting a PAM current signal into the PAM voltage signal.
In a second aspect, the present application also provides a signal receiving and decoding apparatus, including: a comparator array and a decoder, wherein:
the comparator array is used for respectively comparing the Pulse Amplitude Modulation (PAM) voltage signals with a plurality of reference voltages with a first preset number to obtain a plurality of paths of time sequence signals with the first preset number, wherein the plurality of paths of time sequence signals are used for representing comparison results of the comparison;
the decoder is used for decoding the multi-path time sequence signals to obtain multi-path non-return-to-zero NRZ signals with the number being a second preset number;
wherein the first preset number and the second preset number are determined based on the number of levels of PAM.
Optionally, according to the signal receiving and decoding device provided by the present application, the comparator array includes a biaser and a plurality of comparison operators with the first preset number, wherein:
the biaser is used for generating a bias voltage and the plurality of reference voltages;
the comparison arithmetic unit is used for comparing the PAM voltage signal with target reference voltages which are in one-to-one correspondence with the comparison arithmetic unit in the plurality of reference voltages, and acquiring one of the plurality of paths of time sequence signals.
Optionally, according to the signal receiving and decoding device provided by the application, one of the comparison operators includes a pre-amplifying module, a decision module and an output buffer module, wherein:
the pre-amplification module is used for amplifying the PAM voltage signal and the target reference voltage based on the bias voltage to obtain an amplified PAM voltage signal and an amplified target reference voltage;
the decision module is used for comparing the amplified PAM voltage signal with the amplified target reference voltage to obtain a first signal, and the first signal is used for representing a size comparison result;
the output buffer module is used for amplifying the first signal and obtaining the one-path time sequence signal.
Optionally, according to the present application, there is provided a signal receiving and decoding device, the decoder includes a retiming array and a sequential logic arbiter, wherein:
the re-timing array is used for eliminating the time delay of the multi-path time sequence signals and obtaining synchronous multi-path time sequence signals;
the sequential logic discriminator is used for carrying out logic judgment on the synchronous multipath sequential signals to acquire multipath NRZ signals.
Optionally, the signal receiving and decoding device provided by the application further includes: and the transimpedance amplifier is used for converting a PAM current signal into the PAM voltage signal.
The signal receiving and decoding method and the signal receiving and decoding device provided by the application can obtain a plurality of paths of time sequence signals by comparing the PAM voltage signals with a plurality of reference voltages, and finally decode the plurality of paths of time sequence signals to obtain a plurality of paths of NRZ signals.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a signal receiving and decoding method provided by the application;
fig. 2 is a schematic diagram of a signal receiving and decoding device according to the present application;
FIG. 3 is a circuit diagram of a comparator array provided by the present application;
FIG. 4 is a schematic diagram of a comparison operator according to the present application;
FIG. 5 is a circuit diagram of a comparison operator provided by the present application;
FIG. 6 is a schematic diagram of a decoder according to the present application;
FIG. 7 is a schematic diagram of a retimer provided by the present application;
FIG. 8 is a circuit diagram of a retimer provided by the present application;
FIG. 9 is a circuit diagram of a sequential logic arbiter provided by the present application;
fig. 10 is one of the NRZ signal eye diagrams output by the signal receiving and decoding apparatus provided by the present application;
FIG. 11 is a diagram showing the second eye pattern of the NRZ signal outputted from the signal receiving and decoding apparatus according to the present application;
fig. 12 is a third diagram of an NRZ signal eye outputted from the signal receiving and decoding apparatus according to the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order to facilitate a clearer understanding of various embodiments of the present application, some relevant background knowledge is first presented as follows.
The PAM8 signal uses 8 consecutive binary coded (000, 001, 010, 011, 100, 101, 110, 111) represented level magnitudes for information transmission. Each amplitude of the PAM8 signal contains three bits of information compared to a Non-Return-to-Zero (NRZ) signal, and the width of the power spectrum of PAM8 is only one third of NRZ, so that the data transmission rate of PAM8 signal is increased by two times at the same bandwidth, that is, the bandwidth efficiency of PAM8 is three times that of NRZ. Due to the improvement of bandwidth efficiency, the channel loss of PAM8 signals is also reduced. However, PAM8 signal modulation, which increases the data bit rate by increasing the number of pulse amplitude modulation levels, comes at the expense of noise sensitivity. Under the condition of the same swing, the eye diagram of the PAM8 signal is only one seventh of the NRZ signal, so that under the condition of the same error rate, the signal to noise ratio required by transmitting the PAM8 signal is seven times of that of the NRZ signal, and the design of a circuit of a receiving end is higher.
Since the PAM8 signal has eight levels, it needs to be reduced to three parallel NRZ codes in the circuit design, so the PAM8 receiving and decoding circuit design is very different from the conventional light receiving end circuit. At present, research on pulse amplitude modulation signal decoding circuits is mainly focused on an analog front-end circuit part of an optical receiver, a whole circuit of a receiving end is still in a module level design, and the existing receiving end circuit has the problems of high circuit design complexity and high power consumption.
In order to overcome the defects, the application provides a signal receiving and decoding method, which can realize demodulation of PAM voltage signals in an analog domain, acquire multi-path time sequence signals, avoid introducing an analog-to-digital converter and a tapping device module with complicated structures and high power consumption, simplify a circuit system architecture and reduce the power consumption of the circuit system.
The application is explained below in connection with fig. 1-12.
Fig. 1 is a schematic flow chart of a signal receiving and decoding method provided by the present application, and as shown in fig. 1, an execution subject of the method may be an electronic device, where the method includes:
step 101, respectively comparing a Pulse Amplitude Modulation (PAM) voltage signal with a plurality of reference voltages with a first preset number by adopting a comparator array to obtain a plurality of paths of time sequence signals with the first preset number, wherein the plurality of paths of time sequence signals are used for representing comparison results of the comparison;
specifically, the PAM voltage signal is compared with a plurality of reference voltages, and a plurality of paths of timing signals can be obtained, wherein the plurality of paths of timing signals can be a plurality of paths of binary serial timing signals, and the plurality of paths of timing signals are used for representing comparison results of the comparison.
Alternatively, the PAM signal may be a PAM4 signal, a PAM8 signal, or a PAM16 signal, and the specific PAM signal is not limited herein.
Optionally, the PAM voltage signal is compared with one of the plurality of reference voltages in one symbol period, if the level of the PAM voltage signal is higher than the reference level, the corresponding output one-way timing signal may be at a high level, and if the level of the PAM voltage signal is lower than the reference level, the corresponding output one-way timing signal may be at a low level.
Optionally, the first preset number is determined based on the number of levels of PAM.
Alternatively, the reference voltage may be selected as an intermediate value of adjacent levels of the PAM signal.
For example, in the case of a PAM4 signal, the number of levels of PAM is 4, and further, the 4 levels can determine 3 intermediate values, and the first preset number is 3.
For example, in the case of a PAM8 signal, the number of levels of PAM is 8, and further, the 8 levels can determine 7 intermediate values, and the first preset number is 7.
For example, in the case of a PAM8 signal in particular, the 7 reference levels from low to high may be the following levels, respectively: (1) An intermediate value between the level corresponding to logical bit 000 and the level corresponding to logical bit 001; (2) An intermediate value between the level corresponding to logical bit 001 and the level corresponding to logical bit 010; (3) An intermediate value between the level corresponding to logical bit 010 and the level corresponding to logical bit 011; (4) A median between the level corresponding to logical bit 011 and the level corresponding to logical bit 100; (5) An intermediate value between the level corresponding to logical bit 100 and the level corresponding to logical bit 101; (6) An intermediate value between the level corresponding to logical bit 101 and the level corresponding to logical bit 110; (7) Logical bit 110 corresponds to a value intermediate between the level and logical bit 111 corresponds to the level.
Therefore, by comparing the PAM voltage signal with a plurality of reference voltages, a plurality of paths of time sequence signals can be obtained, the PAM signal is demodulated in an analog domain, and the introduction of an analog-to-digital converter and a tapping device module with complicated structures and high power consumption is avoided, so that the architecture of a circuit system is simplified, and the power consumption of the circuit system is reduced.
Step 102, decoding the multi-path time sequence signals to obtain multi-path non-return-to-zero NRZ signals with the number being a second preset number;
specifically, after the multi-path timing signal is acquired, the multi-path timing signal may be decoded to acquire a corresponding multi-path non-return-to-zero NRZ signal.
Optionally, the second preset number is determined based on the number of levels of PAM.
For example, in the case of a PAM4 signal in particular, the second preset number is 2.
For example, in the case of a PAM8 signal in particular, the second preset number is 3.
The signal receiving and decoding method provided by the application can obtain multiple paths of time sequence signals by comparing the PAM voltage signals with multiple reference voltages, and finally decodes the multiple paths of time sequence signals to obtain multiple paths of NRZ signals.
Optionally, the comparing the PAM voltage signal with a plurality of reference voltages with a first preset number to obtain a plurality of paths of timing signals with the first preset number, includes:
sequentially adopting one of comparison operators in the comparator array to compare the PAM voltage signal with target reference voltages which are in one-to-one correspondence with the comparison operators in the plurality of reference voltages, and acquiring one of the plurality of paths of time sequence signals until the first preset number of paths of time sequence signals are acquired;
the comparator array comprises a biaser and a plurality of comparison operators with the first preset number, wherein the biaser is used for generating a bias voltage and the plurality of reference voltages.
Specifically, the comparator array includes a plurality of comparison operators, wherein any one comparison operator can compare the PAM voltage signal with the target reference voltage, and further obtain a path of timing signal, and since the number of comparison operators corresponds to the number of reference voltages, a plurality of paths of timing signals can be obtained through the plurality of comparison operators.
For example, in the case of a PAM4 signal in particular, the number of comparison operators is 3. The 3-path timing signal can be obtained by a plurality of comparison operators.
For example, in the case of a PAM8 signal, the number of comparison operators is 7, and 7 timing signals can be obtained by a plurality of comparison operators.
Therefore, by comparing the PAM voltage signal with a plurality of reference voltages, respectively, a plurality of paths of timing signals can be obtained, and demodulation of the PAM signal in the analog domain is realized.
Optionally, the comparing the PAM voltage signal with a target reference voltage corresponding to the comparison operator one by one in the plurality of reference voltages, to obtain one of the plurality of timing signals, includes:
amplifying the PAM voltage signal and the target reference voltage based on the bias voltage to obtain an amplified PAM voltage signal and an amplified target reference voltage;
comparing the amplified PAM voltage signal with the amplified target reference voltage to obtain a first signal, wherein the first signal is used for representing a comparison result of the size;
amplifying the first signal to obtain the one-path time sequence signal.
Specifically, before comparing the PAM voltage signal with the target reference voltage, the PAM voltage signal and the target reference voltage may be amplified to obtain an amplified PAM voltage signal and an amplified target reference voltage, the voltage is compared to obtain a first signal, and then the first signal is amplified to obtain a time sequence signal.
Alternatively, a differential amplification circuit may be employed to amplify the PAM voltage signal and the target reference voltage.
Alternatively, one of the timing signals may be one of the binary serial timings.
Therefore, one path of time sequence signal can be obtained by comparing the PAM voltage signal with the target reference voltage, and multiple paths of time sequence signals can be obtained by comparing the PAM voltage signal with a plurality of reference voltages respectively, so that the PAM signal is demodulated in an analog domain.
Optionally, the decoding the multiple paths of timing signals to obtain multiple paths of non-return-to-zero NRZ signals with a number of second preset numbers includes:
eliminating time delay of the multi-path time sequence signals and obtaining synchronous multi-path time sequence signals;
and carrying out logic judgment on the synchronous multipath time sequence signals to obtain multipath NRZ signals.
Specifically, since the multi-path timing signal may have an asynchronous problem, in order to solve the problem, the time delay of the multi-path timing signal may be eliminated first, the synchronized multi-path timing signal may be obtained, and then the logic judgment may be performed to obtain the multi-path NRZ signal.
Optionally, a retiming array may be used to eliminate the time delay of the multiple paths of timing signals, and obtain the synchronized multiple paths of timing signals, where the number of retimers in the retiming array may be a first preset number.
For example, in the case of a PAM4 signal in particular, the number of retimers is 3, and 3 synchronized timing signals can be obtained by the retiming array.
For example, in the case of a PAM8 signal in particular, the number of retimers is 7, and 7 synchronized timing signals can be obtained by the retiming array.
Therefore, the time delay of the multipath time sequence signals can be eliminated by adopting the retiming array, and the error rate of time sequence logic discrimination is reduced.
Optionally, the method further comprises:
converting a PAM current signal into the PAM voltage signal.
Alternatively, the PAM current signal may be obtained by receiving a PAM optical signal through a photodetector and converting the PAM optical signal into a current signal.
Alternatively, a transimpedance amplifier may be employed to effect conversion of the PAM current signal to a PAM voltage signal.
Therefore, the application can convert the PAM current signal into the PAM voltage signal, and then process the PAM voltage signal to obtain the multipath non-return-to-zero NRZ signal.
The signal receiving and decoding method provided by the application can obtain multiple paths of time sequence signals by comparing the PAM voltage signals with multiple reference voltages, and finally decodes the multiple paths of time sequence signals to obtain multiple paths of NRZ signals.
Fig. 2 is a schematic structural diagram of a signal receiving and decoding device according to the present application, as shown in fig. 2, the device includes: a comparator array 201 and a decoder 202, wherein:
the comparator array 201 is configured to compare the pulse amplitude modulation PAM voltage signal with a plurality of reference voltages with a first preset number, respectively, to obtain a plurality of paths of timing signals with the first preset number, where the plurality of paths of timing signals are used to characterize a comparison result of the comparison;
the decoder 202 is configured to decode the multiple paths of timing signals to obtain multiple paths of non-return-to-zero NRZ signals with a number equal to a second preset number;
wherein the first preset number and the second preset number are determined based on the number of levels of PAM.
Specifically, the comparator array may respectively compare the PAM voltage signal with a plurality of reference voltages to obtain a plurality of paths of timing signals, and the decoder decodes the plurality of paths of timing signals to obtain a plurality of paths of NRZ signals.
Alternatively, the PAM signal may be a PAM4 signal, a PAM8 signal, or a PAM16 signal, and the specific PAM signal is not limited herein.
Optionally, in one symbol period, the comparator array compares the PAM voltage signal with one of the plurality of reference voltages, if the level of the PAM voltage signal is higher than the reference level, the corresponding output one-way timing signal may be at a high level, and if the level of the PAM voltage signal is lower than the reference level, the corresponding output one-way timing signal may be at a low level.
It can be understood that the application realizes the circuit design of PAM signal receiving demodulation in the analog domain, and compared with the traditional optical receiver and the existing multi-level amplitude modulation receiver, the signal receiving and decoding device provided by the application has the advantages of simple structure, low power consumption, easy design and realization, and the like, and provides a new solution for high-speed optical interconnection.
The signal receiving and decoding device provided by the application can obtain multiple paths of time sequence signals by comparing the PAM voltage signals with multiple reference voltages, and finally decodes the multiple paths of time sequence signals to obtain multiple paths of NRZ signals.
Optionally, the comparator array includes a biaser and a plurality of comparison operators of the first preset number, wherein:
the biaser is used for generating a bias voltage and the plurality of reference voltages;
the comparison arithmetic unit is used for comparing the PAM voltage signal with target reference voltages which are in one-to-one correspondence with the comparison arithmetic unit in the plurality of reference voltages, and acquiring one of the plurality of paths of time sequence signals.
Specifically, the comparator array includes a plurality of comparison operators, wherein any one comparison operator can compare the PAM voltage signal with the target reference voltage, and further obtain a path of timing signal, and since the number of comparison operators corresponds to the number of reference voltages, a plurality of paths of timing signals can be obtained through the plurality of comparison operators.
For example, in the case of a PAM4 signal in particular, the number of comparison operators is 3. The 3-path timing signal can be obtained by a plurality of comparison operators.
For example, in the case of a PAM8 signal, the number of comparison operators is 7, and 7 timing signals can be obtained by a plurality of comparison operators.
Fig. 3 is a circuit diagram of a comparator array provided in the present application, as shown in fig. 3, a bias device may provide a bias voltage and a plurality of reference voltages, and multiple paths of timing signals may be obtained by a plurality of comparison operators.
Alternatively, as shown in fig. 3, in the case of a PAM8 signal in particular, the biaser may provide a bias voltage V bias1 And V bias2 The bias may also provide 7 reference voltages including V ref1 、V ref2 、V ref3 、V ref4 、V ref5 、V ref6 And V ref7 。
Alternatively, as shown in fig. 3, in the case of a PAM8 signal, the plurality of comparison operators may be 7 comparison operators, and the 7 comparison operators may respectively compare the PAM8 voltage signal with V ref1 、V ref2 、V ref3 、V ref4 、V ref5 、V ref6 And V ref7 Comparing the PAM8 voltage signal with V ref1 A path of time sequence signal V can be obtained by comparison out1 PAM8 voltage signal is combined with V ref2 A path of time sequence signal V can be obtained by comparison out2 And so on, the PAM8 voltage signal is compared with V ref7 A path of time sequence signal V can be obtained by comparison out7 。
Therefore, the PAM voltage signal and a plurality of reference voltages are respectively compared by adopting the comparator array to obtain a plurality of paths of time sequence signals, so that the PAM signal is demodulated in an analog domain.
Fig. 4 is a schematic structural diagram of a comparison operator provided in the present application, as shown in fig. 4, one of the comparison operators includes a pre-amplifying module 401, a decision module 402, and an output buffer module 403, where:
the pre-amplification module 401 is configured to amplify the PAM voltage signal and the target reference voltage based on the bias voltage, to obtain an amplified PAM voltage signal and an amplified target reference voltage;
the decision module 402 is configured to compare the amplified PAM voltage signal with the amplified target reference voltage to obtain a first signal, where the first signal is used to characterize a comparison result of the magnitudes;
the output buffer module 403 is configured to amplify the first signal to obtain the one-path timing signal.
Specifically, before comparing the PAM voltage signal with the target reference voltage, the PAM voltage signal and the target reference voltage may be amplified by the pre-amplifying module to obtain an amplified PAM voltage signal and an amplified target reference voltage, then the voltage is compared by the decision module to obtain a first signal, and finally the first signal is amplified by the output buffer module to obtain a time sequence signal.
Optionally, the pre-amplifying module may amplify the PAM voltage signal and the target reference voltage so as to facilitate the decision made by the decision making module, thereby improving the sensitivity of the whole circuit.
Optionally, the pre-amplifying module may be designed in a parallel connection manner of two differential amplifiers, which may include a PMOS differential amplifier and an NMOS differential amplifier, where the PMOS differential amplifier is configured to amplify a signal with a smaller input common mode level, and the NMOS differential amplifier is configured to amplify a signal with a larger input common mode level.
Alternatively, the decision block may be designed in a positive feedback form to increase the gain of the circuit.
Alternatively, the output buffer module may amplify the decision output information (first information) and output a digital signal, that is, a one-way timing signal.
FIG. 5 is a circuit diagram of a comparison operator according to the present application, wherein the input end of the comparison operator is V as shown in FIG. 5 bias1 、V bias2 、V n And V p The output end is V out The comparison arithmetic unit consists of 23 MOS tubes, 2 inductors and 2 resistors.
Optionally, as shown in fig. 5, the comparison operator includes a pre-amplification module, a decision module, and an output buffer module.
Optionally, as shown in fig. 5, the source of the PMOS transistor M0 is connected to the power supply voltage VDD; grid electrode of PMOS tube M0 and input end V bias1 Are connected; the drain electrode of the PMOS tube M0 is in common point with the source electrode of the PMOS tube M1 and the source electrode of the PMOS tube M2; grid electrode and input end V of PMOS tube M1 n Are connected; grid electrode and input end V of PMOS tube M2 p Are connected; the drain electrode of the PMOS tube M1, the drain electrode and the grid electrode of the NMOS tube M3, the grid electrode of the NMOS tube M4,The grid electrode of the PMOS tube M10 is at the same point; the drain electrode of the PMOS tube M2 is in common point with the drain electrode of the NMOS tube M4 and the grid electrode of the PMOS tube M11; the source electrode of the NMOS tube M3 is connected with the ground GND; the source electrode of the NMOS tube M4 is connected with the ground GND; the source electrode of the NMOS tube M5 is connected with the ground GND; grid electrode and input end V of NMOS tube M5 bias2 Are connected; the drain electrode of the NMOS tube M5 is in common with the source electrode of the NMOS tube M6 and the source electrode of the NMOS tube M7; gate and input terminal V of NMOS transistor M6 n Are connected; gate and input terminal V of NMOS transistor M7 p Are connected; the source electrode of the PMOS tube M8 is connected with the power supply voltage VDD; the source electrode of the PMOS tube M9 is connected with the power supply voltage VDD; the source electrode of the PMOS tube M12 is connected with the power supply voltage VDD; the source electrode of the PMOS tube M13 is connected with the power supply voltage VDD; the grid electrode of the PMOS tube M12 is in common point with the grid electrode and the drain electrode of the PMOS tube M8; the grid electrode of the PMOS tube M13 is in common point with the grid electrode and the drain electrode of the PMOS tube M9; the drain electrode of the PMOS tube M12 is in common with the drain electrode of the PMOS tube M10, the drain electrode and the grid electrode of the NMOS tube M14, the drain electrode of the NMOS tube M15, the grid electrode of the NMOS tube M16 and the grid electrode of the NMOS tube M20; the drain electrode of the PMOS tube M13 is in common with the drain electrode of the PMOS tube M11, the drain electrode and the grid electrode of the NMOS tube M17, the drain electrode of the NMOS tube M16, the grid electrode of the NMOS tube M15 and the grid electrode of the NMOS tube M19; the source electrode of the NMOS tube M14 is connected with the ground GND; the source electrode of the NMOS tube M15 is connected with the ground GND; the source electrode of the NMOS tube M16 is connected with the ground GND; the source electrode of the NMOS tube M17 is connected with the ground GND; the source electrode of the NMOS tube M18 is connected with the ground GND; gate and input terminal V of NMOS transistor M18 bias2 Are connected; the drain electrode of the NMOS tube M18 is in common with the source electrode of the NMOS tube M19 and the source electrode of the NMOS tube M20; the drain electrode of the NMOS tube M19 is connected with one end of a resistor R1; one end of the resistor R1 is connected with one end of the inductor L1; one end of the inductor L1 is connected with a power supply voltage VDD; the drain electrode of the NMOS tube M20 is in common with one end of the resistor R2, the grid electrode of the NMOS tube M21 and the grid electrode of the PMOS tube M22; one end of the resistor R2 is connected with one end of the inductor L2; one end of the inductor L2 is connected with a power supply voltage VDD; the source electrode of the PMOS tube M22 is connected with the power supply voltage VDD; drain of PMOS tube M22 and drain of NMOS tube M21, output end V out Are connected; the source of the NMOS transistor M21 is connected to ground GND.
It will be appreciated that the use of a differential configuration with an inductor in series with a resistor as the load, as shown in fig. 5, allows for a significant increase in the bandwidth of the overall circuit.
Fig. 6 is a schematic structural diagram of a decoder provided in the present application, as shown in fig. 6, the decoder includes a retiming array 601 and a sequential logic arbiter 602, wherein:
the retiming array 601 is configured to eliminate time delay of the multiple paths of timing signals, and obtain multiple paths of synchronous timing signals;
the sequential logic discriminator 602 is configured to perform logic determination on the synchronized multiple paths of sequential signals, and obtain multiple paths of NRZ signals.
Specifically, the structures of the comparison operators are different, and multiple paths of signal wires in an actual layout are difficult to be completely matched, so that time differences exist among multiple paths of time sequence signals output by the comparison operators.
Alternatively, the number of retimers in the retiming array may be a first preset number.
For example, in the case of a PAM4 signal in particular, the number of retimers is 3, and 3 synchronized timing signals can be obtained by the retiming array.
For example, in the case of a PAM8 signal in particular, the number of retimers is 7, and 7 synchronized timing signals can be obtained by the retiming array.
FIG. 7 is a schematic diagram of a retimer according to the present application, wherein the retimer input may be a timing signal V as shown in FIG. 7 out And the clock signal CLK outputs a timing signal Q which is synchronous with other timing signals.
Fig. 8 is a circuit diagram of the retimer provided by the present application, as shown in fig. 8, the retimer is composed of two stages of latches, the circuit samples the input signal D when the clock signal CLK is at a high level, the latch output follows, and the latch output remains unchanged when the clock signal CLK is at a low level.
FIG. 9 is a circuit diagram of a sequential logic arbiter according to the present application, as shown in FIG. 9, the sequential logic arbiter includes a plurality of exclusive OR gates, and a plurality of OR gates.
Optionally, in the specific case of PAM8 signals, the sequential logic discriminator includes 7 exclusive or gates and 3 or gates, where 7 synchronous sequential signals (Q1, Q2, Q3, Q4, Q5, Q6 and Q7 in fig. 9) are connected to six exclusive or gate logic in pairs to perform exclusive or operation, and one sequential signal Q1 is connected to one exclusive or gate logic together with the ground GND signal to perform exclusive or operation, so as to determine which of eight levels the input PAM8 signal is located. All signals are output through exclusive or logic so as to ensure that the signal delays are consistent, and no bit difference exists. And then the three four-input OR logic gates realize decoding operation on the PAM8 signal and output three NRZ signals with different bit levels.
Optionally, the apparatus further comprises: and the transimpedance amplifier is used for converting a PAM current signal into the PAM voltage signal.
Specifically, the transimpedance amplifier may receive a PAM current signal and convert the PAM current signal into a PAM voltage signal that can be converted by the comparator array, the comparator array may respectively compare the PAM voltage signal with a plurality of reference voltages to obtain a plurality of paths of timing signals, and the decoder decodes the plurality of paths of timing signals to obtain a plurality of paths of NRZ signals.
Alternatively, the transimpedance amplifier may acquire the PAM current signal through the photodetector.
Therefore, the PAM current signal can be converted into the PAM voltage signal through the transimpedance amplifier, and the PAM voltage signal is further processed to obtain the multipath NRZ signal.
Fig. 10 is one of NRZ signal eye diagrams output by the signal receiving and decoding device provided by the present application, fig. 11 is the second NRZ signal eye diagram output by the signal receiving and decoding device provided by the present application, fig. 12 is the third NRZ signal eye diagram output by the signal receiving and decoding device provided by the present application, the abscissa in fig. 10 to 12 represents time, the ordinate represents voltage amplitude, fig. 10 to 12 are overall simulation results of the signal receiving and decoding device in the case where PAM signal is PAM8 signal, fig. 10 is the high NRZ signal eye diagram output by the signal receiving and decoding device, fig. 11 is the middle NRZ signal eye diagram output by the signal receiving and decoding device, and fig. 12 is the low NRZ signal eye diagram output by the signal receiving and decoding device. 10-12, one 10GBaud PAM8 signal can decode three 10Gb/s NRZ signals, the eye diagram quality is good, obvious jitter, overshoot and undershoot are avoided, and the output swing is larger.
The signal receiving and decoding device provided by the application can obtain multiple paths of time sequence signals by comparing the PAM voltage signals with multiple reference voltages, and finally decodes the multiple paths of time sequence signals to obtain multiple paths of NRZ signals.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A signal reception decoding method, comprising:
a comparator array is adopted to respectively compare Pulse Amplitude Modulation (PAM) voltage signals with a plurality of reference voltages with a first preset number, and a plurality of paths of time sequence signals with the first preset number are obtained, wherein the plurality of paths of time sequence signals are used for representing comparison results of the comparison;
decoding the multi-channel time sequence signals to obtain multi-channel non-return-to-zero NRZ signals with the number of second preset numbers;
wherein the first preset number and the second preset number are determined based on the number of levels of PAM.
2. The method of claim 1, wherein comparing the PAM voltage signal with a plurality of reference voltages of a first preset number to obtain a plurality of timing signals of the first preset number, respectively, comprises:
sequentially adopting one of comparison operators in the comparator array to compare the PAM voltage signal with target reference voltages which are in one-to-one correspondence with the comparison operators in the plurality of reference voltages, and acquiring one of the plurality of paths of time sequence signals until the first preset number of paths of time sequence signals are acquired;
the comparator array comprises a biaser and a plurality of comparison operators with the first preset number, wherein the biaser is used for generating a bias voltage and the plurality of reference voltages.
3. The signal receiving and decoding method according to claim 2, wherein comparing the PAM voltage signal with a target reference voltage of the plurality of reference voltages, which corresponds to the comparison operator one by one, to obtain one of the plurality of timing signals, includes:
amplifying the PAM voltage signal and the target reference voltage based on the bias voltage to obtain an amplified PAM voltage signal and an amplified target reference voltage;
comparing the amplified PAM voltage signal with the amplified target reference voltage to obtain a first signal, wherein the first signal is used for representing a comparison result of the size;
amplifying the first signal to obtain the one-path time sequence signal.
4. The signal receiving and decoding method according to claim 1, wherein decoding the multiple paths of timing signals to obtain a second preset number of multiple paths of non-return-to-zero NRZ signals includes:
eliminating time delay of the multi-path time sequence signals and obtaining synchronous multi-path time sequence signals;
and carrying out logic judgment on the synchronous multipath time sequence signals to obtain multipath NRZ signals.
5. The signal reception decoding method according to claim 1, characterized in that the method further comprises:
converting a PAM current signal into the PAM voltage signal.
6. A signal reception decoding apparatus, the apparatus comprising: a comparator array and a decoder, wherein:
the comparator array is used for respectively comparing the Pulse Amplitude Modulation (PAM) voltage signals with a plurality of reference voltages with a first preset number to obtain a plurality of paths of time sequence signals with the first preset number, wherein the plurality of paths of time sequence signals are used for representing comparison results of the comparison;
the decoder is used for decoding the multi-path time sequence signals to obtain multi-path non-return-to-zero NRZ signals with the number being a second preset number;
wherein the first preset number and the second preset number are determined based on the number of levels of PAM.
7. The signal receiving and decoding device of claim 6, wherein the comparator array includes a biaser and a plurality of comparison operators of the first predetermined number, wherein:
the biaser is used for generating a bias voltage and the plurality of reference voltages;
the comparison arithmetic unit is used for comparing the PAM voltage signal with target reference voltages which are in one-to-one correspondence with the comparison arithmetic unit in the plurality of reference voltages, and acquiring one of the plurality of paths of time sequence signals.
8. The signal receiving and decoding device of claim 7, wherein one of the comparison operators comprises a pre-amplification module, a decision module, and an output buffer module, wherein:
the pre-amplification module is used for amplifying the PAM voltage signal and the target reference voltage based on the bias voltage to obtain an amplified PAM voltage signal and an amplified target reference voltage;
the decision module is used for comparing the amplified PAM voltage signal with the amplified target reference voltage to obtain a first signal, and the first signal is used for representing a size comparison result;
the output buffer module is used for amplifying the first signal and obtaining the one-path time sequence signal.
9. The signal receiving and decoding device of claim 6, wherein the decoder comprises a retiming array and a sequential logic arbiter, wherein:
the re-timing array is used for eliminating the time delay of the multi-path time sequence signals and obtaining synchronous multi-path time sequence signals;
the sequential logic discriminator is used for carrying out logic judgment on the synchronous multipath sequential signals to acquire multipath NRZ signals.
10. The signal reception decoding apparatus according to claim 6, wherein the apparatus further comprises: and the transimpedance amplifier is used for converting a PAM current signal into the PAM voltage signal.
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