CN114335115A - Display panel and manufacturing method thereof - Google Patents
Display panel and manufacturing method thereof Download PDFInfo
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- CN114335115A CN114335115A CN202111646203.4A CN202111646203A CN114335115A CN 114335115 A CN114335115 A CN 114335115A CN 202111646203 A CN202111646203 A CN 202111646203A CN 114335115 A CN114335115 A CN 114335115A
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Abstract
The application provides a display panel and a manufacturing method thereof, the display panel is provided with a display area and a binding area, the display panel comprises a substrate base plate, a line layer, a flat layer, an anode, a pixel definition layer, a light-emitting layer and a cathode, the substrate base plate comprises a second insulating layer, the line layer is arranged on the second insulating layer, the line layer comprises a line pattern and a plurality of wirings, the wirings extend to the binding area from the line pattern, the pixel definition layer comprises a plurality of pixel retaining walls and a plurality of bonding retaining walls, the pixel retaining walls are arranged on the flat layer, one part of the bonding retaining walls are arranged on the edge of the wirings in a pressing mode, and the other part of the bonding retaining walls are arranged on the second insulating layer. The pixel definition layer is provided with the bonding retaining wall, so that the reliability of the circuit layer in the binding area is improved, and the problem that the circuit layer in the binding area falls off is greatly improved.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a display panel and a manufacturing method thereof.
Background
In the current production of large-sized OLED products, since the PAD layer (circuit layer, made of MoTi and other materials) and the PVS layer (insulating layer, made of organic materials) in the bonding region film layer design are in direct contact, one is an inorganic film layer and the other is an organic film layer, the adhesion between the two layers is poor. Because the PAD layer is located at the outermost surface and is in an exposed state, if the adhesion force of the PAD layer and the PVS layer is poor and the boundary position of the contact surface is not protected by other films, the PAD layer is easy to fall off. Particularly, when the OLED display panel is subjected to reworking operation, the PAD layer in the binding area is easy to drop obviously, and the problem can cause that newly-added line defects of products after reworking or line defects caused by corrosion of a metal film layer in a reliability test (continuous dot screen in a high-temperature and high-humidity environment) can occur directly.
Disclosure of Invention
The embodiment of the application provides a display panel and a manufacturing method thereof, and aims to solve the problem that a binding area circuit layer of the existing display panel falls off.
In a first aspect, an embodiment of the present application provides a display panel, which has a display area and a binding area, and includes:
a substrate including a base and a transistor array layer disposed on the base; the transistor array layer comprises a transistor device arranged on the substrate and a spacing layer wrapping the transistor device, wherein the spacing layer comprises a shading layer, a passivation layer, a first insulating layer and a second insulating layer which are sequentially arranged on the substrate;
the circuit layer is arranged on the second insulating layer and is electrically connected with the transistor device through a through hole, the circuit layer comprises a circuit pattern and a plurality of connecting wires, the circuit pattern is arranged in the display area, and the connecting wires extend from the circuit pattern to the binding area;
a planarization layer disposed on the substrate and the line pattern of the display region;
an anode disposed on the planarization layer;
the pixel definition layer comprises a plurality of pixel retaining walls arranged on the flat layer and a plurality of bonding retaining walls arranged in the binding region, one part of the bonding retaining walls is pressed on the edge of the wiring, and the other part of the bonding retaining walls is pressed on the second insulating layer;
the light-emitting layer is arranged on the pixel retaining wall and the anode; and the number of the first and second groups,
and the cathode is arranged on the light emitting layer.
Optionally, the middle of the wiring protrudes from the adhesive retaining wall.
Optionally, the width of the overlapping part of the bonding retaining wall and the wiring is 3-5 μm.
Optionally, a plurality of first grooves are formed in the surface of the second insulating layer corresponding to the wiring, and a plurality of first protrusions embedded with the first grooves are formed in the wiring.
Optionally, the width of the first groove is 2-4 μm.
Optionally, a plurality of second grooves are formed in the surface of the wiring close to the edge, and a plurality of second protrusions embedded with the second grooves are formed in the bonding retaining wall.
Optionally, an oblique inward lateral groove is formed on the side surface of the wiring, and a lateral protrusion embedded with the lateral groove is arranged on the bonding retaining wall.
In a second aspect, an embodiment of the present application further provides a manufacturing method of a display panel, where the display panel includes a display area and a binding area, and the manufacturing method of the display panel includes:
s10, preparing a substrate base plate, wherein the substrate base plate comprises a base plate and a transistor array layer arranged on the base plate; the transistor array layer comprises a transistor device arranged on the substrate and a spacing layer wrapping the transistor device, wherein the spacing layer comprises a shading layer, a passivation layer, a first insulating layer and a second insulating layer which are sequentially arranged on the substrate;
s20, forming a circuit layer on the second insulating layer, the circuit layer being electrically connected to the transistor device through the via hole, the circuit layer including a circuit pattern and a plurality of wires, the circuit pattern being disposed in the display area, the wires extending from the circuit pattern to the bonding area;
s30, preparing a flat layer, wherein the flat layer covers the substrate base plate and the circuit layer of the display area;
s40, preparing an anode on the flat layer;
s50, preparing a pixel definition layer, wherein the pixel definition layer comprises a plurality of pixel retaining walls arranged on the flat layer and an adhesive retaining wall arranged in the binding region, one part of the adhesive retaining wall is pressed on the edge of the wiring, and the other part of the adhesive retaining wall is pressed on the second insulating layer;
s60, preparing a light-emitting layer on the pixel retaining wall and the anode;
and S70, preparing a cathode on the light-emitting layer.
Optionally, in step S50, the pixel definition layer is formed by photolithography, and the bonding retaining wall is thinned by weak exposure using a halftone mask process, so that the middle of the wiring protrudes from the bonding retaining wall.
Optionally, in step S20, the wires are formed by etching with an etchant, and the etching time of the etchant is prolonged to form lateral grooves obliquely inward on the side surfaces of the wires.
According to the display panel provided by the embodiment of the application, the bonding retaining wall is formed in the binding area by carrying out pattern design on the pixel definition layer, the bonding retaining wall is used as a part of the pixel definition layer, a photoetching process is not required to be added during manufacturing, the production efficiency is not influenced, and the bonding retaining wall can be arranged under the conventional process. One part of the bonding retaining wall is arranged on the edge of the wiring in a pressing mode, and the other part of the bonding retaining wall is arranged on the second insulating layer in a pressing mode. The adhesive retaining wall and the second insulating layer are both made of organic materials, and the adhesive performance of the adhesive retaining wall and the second insulating layer is good. The border of wiring is compressed tightly to the bonding barricade, tightly be in the same place with the laminating of second insulating layer simultaneously, the border of wiring has been wrapped, and the position at wiring border has been injectd, make it can not remove, also can not direct and external contact, can effectively avoid the border atress of wiring and the pine that leads to takes off, the reliability of wiring has been improved greatly, the problem that the district circuit layer that binds of solving display panel drops, consequently also can avoid the wiring to take off and receive the condition of corruption in the high humid tropical environment, and then show improvement product yield.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be derived from these drawings by a person skilled in the art without inventive effort.
For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a film structure of a display region in the display panel shown in fig. 1.
Fig. 3 is a schematic diagram of a film structure of a bonding region in the display panel shown in fig. 1.
Fig. 4 is a schematic diagram of a film structure of a bonding region in a display panel according to another embodiment of the present application.
Fig. 5 is a schematic diagram of a film structure of a bonding region in a display panel according to yet another embodiment of the present application.
Fig. 6 is a schematic diagram of a film structure of a bonding region in a display panel according to yet another embodiment of the present application.
Fig. 7 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a display panel and a manufacturing method thereof, and aims to solve the problem that a binding area circuit layer of the existing display panel falls off. The following description will be made with reference to the accompanying drawings.
In order to more clearly explain the structure of the display panel, the display panel will be described below with reference to the accompanying drawings.
For example, please refer to fig. 1 to 3, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application. Fig. 2 is a schematic diagram of a film structure of a display region in the display panel shown in fig. 1. Fig. 3 is a schematic diagram of a film structure of a bonding region in the display panel shown in fig. 1.
The display panel has a display area 100 and a binding area 200, and includes a substrate base 300, a wiring layer 400, a planarization layer 500, an anode electrode 600, a pixel defining layer 700, a light emitting layer 800, and a cathode electrode 900.
Referring further to fig. 2, the substrate 300 includes a base plate and a transistor array layer 320 disposed on the base plate 310; the transistor array layer 320 includes a transistor device 321 disposed on the substrate 310 and a spacer layer 322 covering the transistor device 321, wherein the spacer layer 322 includes a light-shielding layer 3221, a passivation layer 3222, a first insulating layer 3223 and a second insulating layer 3224 sequentially disposed on the substrate 310. The transistor device 321 provided in the embodiment of the present application is not limited to the LTPS, Oxide TFT, or SPC transistor device. It should be noted that, in this embodiment, the structures of the light-shielding layer 3221, the passivation layer 3222, the first insulating layer 3223, the second insulating layer 3224 and the transistor device 321 are all conventional arrangements in OLED products, and are not described herein again.
Referring to fig. 1 to 3, a circuit layer 400 is disposed on the second insulating layer 3224, the circuit layer 400 is electrically connected to the transistor device 321 through a via, the circuit layer 400 includes a circuit pattern 410 and a plurality of wires 420, the circuit pattern 410 is disposed in the display area 100, and the wires 420 extend from the circuit pattern 410 to the bonding area 200. The circuit layer 400 is formed by patterning a metal film layer under the action of an etchant, the circuit pattern 410 is used for electrically connecting the transistor device 321, and the connection wire 420 is used for connecting an external circuit.
A planarization layer 500 is disposed on the substrate base 300 and the line pattern 410 of the display area 100. The planarization layer 500 is formed on the display area 100 to form a planarized layer for facilitating the subsequent film layer preparation.
The anode 600 is disposed on the planarization layer 500. The anode 600 is obtained by patterning a metal film layer of the anode 600 under the action of an etchant, and is used as the anode 600 of the OLED light emitting device. It should be noted that, in this embodiment, the arrangement manner of the anode 600 may be various arrangement manners existing in the existing OLED product, and is not limited herein.
The pixel definition layer 700 includes a plurality of pixel retaining walls 710 disposed on the planarization layer 500 and a plurality of bonding retaining walls 720 disposed in the bonding region 200, wherein a portion of the bonding retaining walls 720 is pressed on the edge of the wiring 420, and the other portion is pressed on the second insulating layer 3224. The pixel walls 710 are used to define each pixel of the display panel, and the adhesion walls 720 are used to improve the adhesion reliability of the wires 420 to the second insulating layer 3224. In actual operation, the bonding wall 720 may be formed in the bonding region 200 by patterning the pixel definition layer 700, and the bonding wall 720 is used as a part of the pixel definition layer 700, so that a photolithography process is not required to be separately added during manufacturing, the production efficiency is not affected, and the bonding wall 720 can be disposed in a conventional process. A portion of the adhesive dam 720 is pressed on the edge of the wire 420, and another portion is pressed on the second insulating layer 3224. The adhesion wall 720 and the second insulating layer 3224 are both made of organic materials, and the adhesion performance of the two materials is good. The bonding retaining wall 720 compresses the edge of the wiring 420, and is tightly attached to the second insulating layer 3224, so that the edge of the wiring 420 is covered, the position of the edge of the wiring 420 is limited, the wiring 420 cannot move, the wiring cannot be directly contacted with the outside, the loosening caused by the stress on the edge of the wiring 420 can be effectively avoided, and the reliability of the wiring 420 is greatly improved. In order to achieve a good adhesion effect without affecting the use properties of the wiring 420, the width of the overlapping portion of the adhesion stopper 720 and the wiring 420 may be set to 3-5 μm. At this time, the adhesive dam 720 is in sufficient contact with the wiring 420, and does not block the wiring 420, thereby ensuring the functionality and reliability of the wiring 420. It should be noted that, in order to avoid the effect of the Bonding wall 720 affecting the subsequent processes (such as COF Bonding), the Bonding wall 720 may be thinned by performing weak exposure on the Bonding wall 720, so that the middle portion of the wire 420 protrudes from the Bonding wall 720, and the wire 420 is used as the most prominent portion of the Bonding region 200, and thus has better connection performance.
The light emitting layer 800 is disposed on the pixel retaining wall 710 and the anode 600. The light emitting layer 800 is made of an electroluminescent material, and can emit light under the action of current to realize image display of the display panel.
The cathode 900 is disposed on the light emitting layer 800. The cathode 900 is made of a cathode 900 metal film layer, which is used as the cathode 900 of the OLED light emitting device. In this embodiment, the cathode 900 may be disposed in various manners existing in the OLED product, and is not limited herein.
In summary, in the display panel provided in the embodiment of the present application, the bonding wall 720 is formed in the bonding region 200 by performing the pattern design on the pixel definition layer 700, and the bonding wall 720 is used as a part of the pixel definition layer 700, so that the photo-etching process is not required to be separately added during the manufacturing process, the production efficiency is not affected, and the bonding wall 720 can be arranged in the conventional process. A portion of the adhesive dam 720 is pressed on the edge of the wire 420, and another portion is pressed on the second insulating layer 3224. The adhesion wall 720 and the second insulating layer 3224 are both made of organic materials, and the adhesion performance of the two materials is good. Bonding barricade 720 compresses tightly the border of wiring 420, tightly be in the same place with second insulating layer 3224 laminating simultaneously, the border of wiring 420 has been wrapped up, and the position at wiring 420 border has been injectd, make it can not remove, also can not direct and external contact, can effectively avoid the border atress of wiring 420 and the pine that leads to takes off, wiring 420's reliability has been improved greatly, the problem that bonding district 200 circuit layer 400 of solving display panel drops, consequently also can avoid wiring 420 to drop the back and receive the condition of corruption in the high humid ambience, and then show improvement product yield.
In order to improve the adhesion reliability of the second insulating layer 3224 and the wiring 420 and achieve a better anti-falling effect, some specific designs may be performed on the contact surfaces of the two. For example, fig. 4 is a schematic diagram of a film layer structure of a bonding region 200 in a display panel according to another embodiment of the present application. The surface of the second insulating layer 3224 is provided with a plurality of first grooves 3225 corresponding to the wiring 420, and the wiring 420 is provided with a plurality of first protrusions 421 engaged with the first grooves 3225. The contact area between the second insulating layer 3224 and the wiring 420 can be greatly increased by arranging the first groove 3225 and the first protrusion 421, so that the adhesion between the second insulating layer 3224 and the connection is improved, the reliability of the wiring 420 is further improved, and the problem that the wiring layer 400 falls off in the binding region 200 of the display panel is solved. The first groove 3225 may be formed during the preparation of the second insulating layer 3224 by a reticle design. Theoretically, the larger the number of the first grooves 3225, the better the bonding effect, so the smaller the size of the first grooves 3225, the better, considering the device accuracy, in the present embodiment, the width of the first grooves 3225 is 2-4 μm. Preferably, the width of the first groove 3225 is 3 μm.
In addition to the design of the contact surface between the second insulating layer 3224 and the wire 420, the contact surface between the wire 420 and the adhesive retaining wall 720 may be designed to improve the adhesion reliability between the wire 420 and the adhesive retaining wall 720 and optimize the anti-slip effect.
For example, referring to fig. 5, fig. 5 is a schematic diagram of a film structure of a bonding region 200 in a display panel according to another embodiment of the present application. The surface of the wiring 420 is provided with a plurality of second grooves 422 near the edge, and the adhesive retaining wall 720 is provided with a plurality of second protrusions 721 embedded with the second grooves 422. The contact area between the wiring 420 and the adhesive dam 720 can be greatly increased by providing the second recess 422 and the second protrusion 721, so that the adhesion between the wiring 420 and the adhesive dam 720 is improved, the reliability of the wiring 420 is further improved, and the problem that the wiring layer 400 falls off in the bonding region 200 of the display panel is improved.
Referring to fig. 6, fig. 6 is a schematic diagram of a film structure of a bonding region 200 in a display panel according to yet another embodiment of the present disclosure, and considering that a wire 420 is formed by etching with an etchant, the present disclosure also provides the embodiment shown in fig. 6, in which a side surface of the wire 420 is formed with a lateral groove 423 inclined inward, and the adhesive retaining wall 720 is provided with a lateral protrusion 722 engaged with the lateral groove 423. The lateral grooves 423 may be formed by etching the lower side portions of the wire 420 using the fluidity of the etchant by extending the etching time of the etchant. The contact area between the wiring 420 and the adhesive wall 720 can be greatly increased by the arrangement of the lateral grooves 423 and the lateral protrusions 722, so that the adhesion between the wiring 420 and the adhesive wall 720 is improved, the reliability of the wiring 420 is further improved, and the problem that the wiring layer 400 falls off from the bonding region 200 of the display panel is solved.
For better explaining the method for manufacturing the display panel according to the embodiment of the present application, please refer to fig. 7 and refer to fig. 1 to 3 for understanding, and fig. 7 is a flowchart for illustrating the method for manufacturing the display panel according to the embodiment of the present application. The manufacturing method of the display panel comprises the following steps:
s10, preparing a substrate 300, wherein the substrate 300 comprises a base plate 310 and a transistor array layer 320 arranged on the base plate 310; the transistor array layer 320 includes a transistor device 321 disposed on the substrate 310 and a spacer layer 322 covering the transistor device 321, wherein the spacer layer 322 includes a light-shielding layer 3221, a passivation layer 3222, a first insulating layer 3223 and a second insulating layer 3224 sequentially disposed on the substrate 310. The transistor device 321 fabricated in the embodiment of the present application is not limited to the transistor device 321 such as LTPS, Oxide TFT, or SPC. It should be noted that, in this embodiment, the light-shielding layer 3221, the passivation layer 3222, the first insulating layer 3223, the second insulating layer 3224, and the transistor device 321 are all manufactured by a conventional manufacturing method in an OLED product, and details are not repeated herein.
S20, preparing a circuit layer 400 on the second insulating layer 3224, the circuit layer 400 being electrically connected to the transistor device 321 through a via, the circuit layer 400 including a circuit pattern 410 and a plurality of wires 420, the circuit pattern 410 being disposed in the display area 100, the wires 420 extending from the circuit pattern 410 to the bonding area 200. The circuit layer 400 is formed by patterning a metal film layer under the action of an etchant, the circuit pattern 410 is used for electrically connecting the transistor device 321, and the connection wire 420 is used for connecting an external circuit. In some embodiments, to improve the selectivity, in the step S20, the connection line is formed by etching with an etchant, and the etching time of the etchant is prolonged to form a lateral groove 423 inclined inward at the lateral edge of the connection line 420. By forming the lateral grooves 423, the bonding barriers 720 can also form the lateral protrusions 722 correspondingly during subsequent preparation, and the contact area between the wiring 420 and the bonding barriers 720 can be greatly increased by the embedding of the lateral grooves 423 and the bonding barriers 720, so that the adhesion between the wiring 420 and the bonding barriers 720 is improved, the reliability of the wiring 420 is further improved, and the problem that the wiring layer 400 falls off from the bonding region 200 of the display panel is solved.
S30, preparing a flat layer 500, wherein the flat layer 500 covers the substrate 300 and the circuit layer 400 of the display area 100. The planarization layer 500 is formed on the display area 100 to form a planarized layer for facilitating the subsequent film layer preparation.
S40, preparing an anode 600 on the planarization layer 500. The anode 600 is obtained by patterning a metal film layer of the anode 600 under the action of an etchant, and is used as the anode 600 of the OLED light emitting device. It should be noted that, in this embodiment, a specific preparation manner of the anode 600 may be a preparation manner occurring in the production of an existing OLED product, and is not limited herein.
S50, preparing a pixel defining layer 700, where the pixel defining layer 700 includes a plurality of pixel retaining walls 710 disposed on the planarization layer 500 and an adhesive retaining wall 720 disposed in the bonding region 200, a portion of the adhesive retaining wall 720 is pressed on the edge of the wire 420, and another portion is pressed on the second insulating layer 3224. The pixel defining layer 700 is formed by a photolithography process, the pixel retaining walls 710 are used to define each pixel of the display panel, and the adhesion retaining walls 720 are used to improve the adhesion reliability of the wiring 420 to the second insulating layer 3224. In the preparation process, the bonding retaining wall 720 can be formed in the binding region 200 by performing pattern design on the mask of the pixel definition layer 700, the bonding retaining wall 720 is used as a part of the pixel definition layer 700, a photolithography process is not required to be added during the preparation process, the production efficiency is not affected, and the setting of the bonding retaining wall 720 can be realized under the conventional process. A portion of the adhesive dam 720 is pressed on the edge of the wire 420, and another portion is pressed on the second insulating layer 3224. The adhesion wall 720 and the second insulating layer 3224 are both made of organic materials, and the adhesion performance of the two materials is good. The bonding retaining wall 720 compresses the edge of the wiring 420, and is tightly attached to the second insulating layer 3224, so that the edge of the wiring 420 is covered, the position of the edge of the wiring 420 is limited, the wiring 420 cannot move, the wiring cannot be directly contacted with the outside, the loosening caused by the stress on the edge of the wiring 420 can be effectively avoided, and the reliability of the wiring 420 is greatly improved.
Optionally, in order to avoid the effect of the subsequent process (e.g., COF Bonding) caused by the excessive thickness of the Bonding wall 720, in step S50, the pixel defining layer 700 is formed by photolithography, and a half-tone mask process is correspondingly used at the Bonding wall 720 to thin the Bonding wall 720 by weak exposure, so that the middle of the wire 420 protrudes from the Bonding wall 720. The position of the mask plate used in the halftone photomask manufacturing process corresponding to the bonding retaining wall 720 has partial light transmittance, in the photoetching manufacturing process, weak exposure to the bonding retaining wall 720 can be realized, and the light transmittance of the mask plate corresponding to the position of the bonding retaining wall 720 can be adjusted according to needs, so that the exposure degree is adjusted, and the thickness of the bonding retaining wall 720 is controlled. The middle of the connection wire 420 is guaranteed to protrude from the adhesive retaining wall 720, and at this time, the connection wire 420 is used as the most protruding part of the binding region 200, so that the connection performance is better.
S60, preparing a light emitting layer 800 on the pixel retaining wall 710 and the anode 600; the light emitting layer 800 is made of an electroluminescent material, and can emit light under the action of current to realize image display of the display panel.
S70, preparing a cathode 900 on the light emitting layer 800. The cathode 900 is made of a cathode 900 metal film layer, which is used as the cathode 900 of the OLED light emitting device. In this embodiment, the cathode 900 may be prepared in various manners existing in the existing OLED product, and is not limited herein.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the embodiment of the present application are explained by applying specific examples herein, and the description of the embodiments above is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel having a display area and a binding area, the display panel comprising:
a substrate including a base and a transistor array layer disposed on the base; the transistor array layer comprises a transistor device arranged on the substrate and a spacing layer wrapping the transistor device, wherein the spacing layer comprises a shading layer, a passivation layer, a first insulating layer and a second insulating layer which are sequentially arranged on the substrate;
the circuit layer is arranged on the second insulating layer and is electrically connected with the transistor device through a through hole, the circuit layer comprises a circuit pattern and a plurality of connecting wires, the circuit pattern is arranged in the display area, and the connecting wires extend from the circuit pattern to the binding area;
a planarization layer disposed on the substrate and the line pattern of the display region;
an anode disposed on the planarization layer;
the pixel definition layer comprises a plurality of pixel retaining walls arranged on the flat layer and a plurality of bonding retaining walls arranged in the binding region, one part of the bonding retaining walls is pressed on the edge of the wiring, and the other part of the bonding retaining walls is pressed on the second insulating layer;
the light-emitting layer is arranged on the pixel retaining wall and the anode; and the number of the first and second groups,
and the cathode is arranged on the light emitting layer.
2. The display panel according to claim 1, wherein the middle of the wiring protrudes from the adhesive dam.
3. The display panel according to claim 1, wherein the width of the portion where the adhesive dam and the wiring overlap is 3 to 5 μm.
4. The display panel according to claim 1, wherein the second insulating layer has a plurality of first grooves corresponding to the wires, and the wires have a plurality of first protrusions engaged with the first grooves.
5. The display panel according to claim 4, wherein the width of the first groove is 2-4 μm.
6. The display panel according to claim 1, wherein a plurality of second grooves are formed on the surface of the wiring close to the edge, and a plurality of second protrusions are formed on the adhesive barrier wall and are embedded with the second grooves.
7. The display panel according to claim 1, wherein the side surfaces of the wirings are formed with lateral grooves inclined inward, and the adhesive dam is provided with lateral protrusions fitted into the lateral grooves.
8. A method of making a display panel having a display area and a bonding area, the method comprising:
s10, preparing a substrate base plate, wherein the substrate base plate comprises a base plate and a transistor array layer arranged on the base plate; the transistor array layer comprises a transistor device arranged on the substrate and a spacing layer wrapping the transistor device, wherein the spacing layer comprises a shading layer, a passivation layer, a first insulating layer and a second insulating layer which are sequentially arranged on the substrate;
s20, forming a circuit layer on the second insulating layer, the circuit layer being electrically connected to the transistor device through the via hole, the circuit layer including a circuit pattern and a plurality of wires, the circuit pattern being disposed in the display area, the wires extending from the circuit pattern to the bonding area;
s30, preparing a flat layer, wherein the flat layer covers the substrate base plate and the circuit layer of the display area;
s40, preparing an anode on the flat layer;
s50, preparing a pixel definition layer, wherein the pixel definition layer comprises a plurality of pixel retaining walls arranged on the flat layer and an adhesive retaining wall arranged in the binding region, one part of the adhesive retaining wall is pressed on the edge of the wiring, and the other part of the adhesive retaining wall is pressed on the second insulating layer;
s60, preparing a light-emitting layer on the pixel retaining wall and the anode;
and S70, preparing a cathode on the light-emitting layer.
9. The method as claimed in claim 8, wherein in step S50, the pixel defining layer is formed by photolithography, and the bonding wall is thinned by weak exposure using a half tone mask process, so that the middle portion of the wire protrudes from the bonding wall.
10. The method of claim 8, wherein in the step S20, the wires are formed by etching with an etchant, and the etching time of the etchant is prolonged to form lateral grooves on the sides of the wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111646203.4A CN114335115A (en) | 2021-12-30 | 2021-12-30 | Display panel and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111646203.4A CN114335115A (en) | 2021-12-30 | 2021-12-30 | Display panel and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN114335115A true CN114335115A (en) | 2022-04-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111646203.4A Pending CN114335115A (en) | 2021-12-30 | 2021-12-30 | Display panel and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114335115A (en) |
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2021
- 2021-12-30 CN CN202111646203.4A patent/CN114335115A/en active Pending
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