CN114335003A - Three-dimensional memory and preparation method thereof - Google Patents

Abstract

The application provides a three-dimensional memory and a preparation method thereof. The method for preparing the three-dimensional memory comprises the following steps: forming a first laminated structure, and forming a channel sacrificial structure and an initial support structure which penetrate through the first laminated structure; forming a second stacked structure on the first stacked structure and forming a second channel hole penetrating the second stacked structure, wherein the second channel hole is at least partially aligned with the corresponding channel sacrificial structure; and forming a gate line gap, wherein one part of the gate line gap penetrates through the first laminated structure and the second laminated structure, and the other part of the gate line gap penetrates through the second laminated structure and extends to the initial support structure.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory (3D NAND) and a method for fabricating the same.

Background

In recent years, with the rapid development of integrated circuit technology, the performance requirements of memories in integrated circuits are higher and higher, and 3D NAND memories are produced accordingly. In order to further improve the device performance of the 3D NAND, the number of stacked layers of memory cells in the 3D NAND is increasing.

In the 3D NAND manufacturing process, generally, a stacked structure including a dielectric layer and a sacrificial layer is formed on a substrate, and a plurality of gate line slits are formed in the stacked structure in a subsequent process. The gate line gap can separate the stacked structure into different parts, and the sacrificial layer can be removed through the gate line gap by adopting a process such as etching.

It should be understood that the statements in this background section merely provide an aid in understanding the technical solutions disclosed herein and are not necessarily prior art to the filing date of the present application.

Disclosure of Invention

One aspect of the present application provides a method of fabricating a three-dimensional memory. The method comprises the following steps: forming a first laminated structure, and forming a channel sacrificial structure and an initial support structure which penetrate through the first laminated structure; forming a second stacked structure on the first stacked structure and forming a second channel hole penetrating the second stacked structure, wherein the second channel hole is at least partially aligned with the corresponding channel sacrificial structure; and forming a gate line gap, wherein one part of the gate line gap penetrates through the first laminated structure and the second laminated structure, and the other part of the gate line gap penetrates through the second laminated structure and extends to the initial support structure.

In one embodiment, the forming of the gate line slit includes: forming a first etching mask layer including a gate line slit pattern on the second stacked structure; and etching the second stacked structure, the first stacked structure and the initial support structure via the gate line gap pattern to form the gate line gap.

In one embodiment, in the step of forming the gate line slit, an etching rate of the initial support structure is less than an etching rate of the first stack structure, so that at most a portion of the initial support structure corresponding to the gate line slit pattern is removed to form a support structure when the etching is completed.

In one embodiment, the gate line slit extends in a first direction, and the support structure extends in a second direction crossing the first direction, wherein the first direction and the second direction are perpendicular to a direction in which the first stacked structure and the second stacked structure are stacked.

In one embodiment, a projection shape of the support structure on a plane in which the first direction and the second direction are located includes a first end portion, a second end portion, and a connection portion connecting the first end portion and the second end portion, and the gate line slit crosses the connection portion.

In one embodiment, a plurality of the channel sacrifice structures are arranged in an array in a plane perpendicular to a stacking direction of the first stacked structure and the second stacked structure, the array includes a plurality of rows extending in a first direction and a plurality of columns extending in a second direction, and a plurality of the columns are spaced between two adjacent initial support structures along the first direction.

In one embodiment, the projected shape of the support structure on the plane comprises a first end portion, a second end portion and a connecting portion connecting the first end portion and the second end portion, the first end portion and the second end portion being located in two adjacent rows, respectively.

In one embodiment, the step of forming a channel sacrificial structure and an initial support structure through the first stack structure comprises: forming a second etching mask layer comprising a first channel hole pattern and a supporting channel hole pattern on the first laminated structure; etching the first laminated structure to form a first channel hole and a support channel hole which penetrate through the first laminated structure; and filling a sacrificial material in the first channel hole and the support channel hole to form the channel sacrificial structure and the initial support structure respectively.

In one embodiment, before forming the gate line slit, the method further includes: removing the channel sacrificial structure through the second channel hole to expose the first channel hole; and forming a channel structure in the second channel hole and the first channel hole.

In one embodiment, the method further comprises: the first stack structure is formed on a substrate, the initial support structure penetrates through the first stack structure and extends to the substrate, and the channel structure penetrates through the first stack structure and the second stack structure and extends to the substrate.

Another aspect of the present application provides a three-dimensional memory, including: a first stacking structure through which a support structure is disposed; a second stacked structure stacked on the first stacked structure; and a gate line slit structure, a part of which penetrates through the first and second stacked structures, and another part of which penetrates through the second stacked structure and extends to the support structure.

In one embodiment, the gate line slit structure extends in a first direction perpendicular to a stacking direction of the first and second stacked structures, and the support structure extends in a second direction perpendicular to the stacking direction and intersecting the first direction.

In one embodiment, a projection shape of the support structure on a plane in which the first direction and the second direction are located includes a first end portion, a second end portion, and a connection portion connecting the first end portion and the second end portion, and the gate line slit crosses the connection portion.

In one embodiment, the three-dimensional memory further comprises: and a channel structure extending through the first stacked structure and the second stacked structure, wherein a plurality of the channel structures are arranged in an array in a plane perpendicular to a stacking direction of the first stacked structure and the second stacked structure, the array includes a plurality of rows extending in a first direction and a plurality of columns extending in a second direction, and a plurality of the columns are spaced between two adjacent support structures along the first direction.

In one embodiment, the projected shape of the support structure on the plane comprises a first end portion, a second end portion and a connecting portion connecting the first end portion and the second end portion, the first end portion and the second end portion being located in two adjacent rows, respectively.

In one embodiment, the number of the gate line slit structures includes a plurality, and each of the gate line slit structures extends to at least one of the support structures along the first direction.

The preparation method of the three-dimensional memory provided by the application can have at least one of the following beneficial effects:

according to some embodiments of the present application, after the gate line slit is formed, at least a portion of the initial support structure located in the first stacked structure is maintained, so that stress of the first stacked structure can be improved, and skew of the first stacked structure due to the stress can be prevented.

According to some embodiments of the present application, the effect of increasing the memory processing process window and stability can be achieved.

Drawings

Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments when taken in conjunction with the accompanying drawings. In the drawings:

fig. 1 to 2 are process diagrams illustrating a method for manufacturing a three-dimensional memory according to the related art;

FIG. 3 is a flow chart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application;

fig. 4 to 16 are process diagrams of a method of manufacturing a three-dimensional memory according to an exemplary embodiment of the present application; and

fig. 17 is a schematic structural diagram of a three-dimensional memory according to an exemplary embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, without departing from the teachings of the present application, the second channel hole discussed in the present application may also be referred to as a first channel hole and the first channel structure may also be referred to as a second channel structure, and vice versa.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, the thickness of the first etch mask layer as drawn in the figures of the present application is not to scale in actual production. As used herein, "substantially", "about" and similar terms are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

The features, principles and other aspects of the present application are described in detail below.

Fig. 1 to 2 are schematic views illustrating a manufacturing process of a three-dimensional memory according to the related art. As shown in fig. 1, a plurality of insulating layers and sacrificial layers may be stacked in the z-direction on the substrate 110 to form a stacked structure 120. Illustratively, a plurality of gate line slits 130 may be formed in the three-dimensional memory partial structure 100 to extend through the stacked structure 120 and to the substrate 110. Illustratively, the gate line slit 130 may be formed using a combination of processes such as photolithography and etching.

The inventors of the present application have discovered that in some cases, the laminate structure 120 may have residual stress present during fabrication. The gate line slit 130 is formed to divide the stacked structure 120 into a plurality of portions, and each portion of the stacked structure 120 is subjected to stress. As shown in fig. 2, a portion of the stacked structure 120 between two gate line slits 130 forms a stacked structure first portion 121. Due to the stress, the first portion 121 of the stacked structure may be distorted to a certain extent, which may have a serious impact on the subsequent processing and performance of the memory device.

The present application provides a three-dimensional memory and a method for manufacturing the same, which can at least partially improve or solve the above problems, reduce device defects caused by the above stress, and significantly increase the window of the manufacturing process and the stability of the device.

Fig. 3 is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application. As shown in fig. 3, the present application provides a method 1000 for manufacturing a three-dimensional memory, including:

step S1100, forming a first laminated structure, and forming a channel sacrificial structure and an initial support structure which penetrate through the first laminated structure;

step S1200, forming a second stacked structure on the first stacked structure, and forming a second channel hole penetrating through the second stacked structure, wherein the second channel hole is at least partially aligned with the corresponding channel sacrificial structure; and

step S1300, a gate line gap is formed, in which a portion of the gate line gap penetrates through the first stacked structure and the second stacked structure, and another portion penetrates through the second stacked structure and penetrates through an upper portion of the initial support structure.

It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the illustrated steps may be performed concurrently or may be performed in an order different than that shown in FIG. 3.

Fig. 4 to 17 are process diagrams of a method 1000 for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. The above steps S1100 to S1300 are further described below with reference to fig. 3 to 17.

Step S1100, forming a first stacked structure, and forming a channel sacrificial structure and an initial structure penetrating the first stacked structure A support structure.

As shown in fig. 4, in step S1100, a first stacked structure 220 may be formed on a substrate 210. The first stacked structure 220 may be formed by alternately stacking dielectric layers 221 and sacrificial layers 222. In some embodiments, the material of the substrate 210 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. In some embodiments, the substrate 210 may include a base (not shown) and a composite layer on the base, wherein the base has a certain thickness and may serve as a structural support for a device structure (e.g., the first stacked structure 220) formed thereon, and optionally may be removed in some subsequent process steps.

In some embodiments, the first stacked structure 220 may include a plurality of dielectric layers 221 and a plurality of sacrificial layers 222 alternately stacked in a direction (z direction) perpendicular or substantially perpendicular to the substrate 210, and the sacrificial layers 222 and the dielectric layers 221 may have a high etching selectivity under the same etching conditions, so that the dielectric layers 221 are hardly removed when the sacrificial layers 222 are removed in a subsequent process. In some examples, the material for sacrificial layer 222 includes, for example, silicon nitride, and the material for dielectric layer 221 includes silicon oxide.

Illustratively, the first stack structure 220 may be formed by alternately forming a plurality of sacrificial layers 222 and dielectric layers 221 on the substrate 210 through a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

It should be understood that the number of layers of the first stacked structure 220 is not limited to the number of layers shown in the drawing, but the number of stacked layers and the stacking height of the stacked structure 220 may be designed according to actual requirements, which is not specifically limited in this application.

Fig. 5(a) is a schematic process diagram of forming a first channel hole 230 and a support channel hole 240 of a three-dimensional memory according to an embodiment of the present disclosure. FIG. 5(b) is a schematic cross-sectional view taken along plane A-A in FIG. 5 (a). As shown in conjunction with fig. 5(a) and 5(b), in some embodiments, a plurality of first channel holes 230 and support channel holes 240 may be formed on the first stack structure 220. Illustratively, the first channel hole 230 and the support channel hole 240 may both penetrate the first stack structure 220 and extend to the substrate 210. In some embodiments, the projected shape 230 'of the first channel hole 230 on the substrate 210 may be circular, and the projected shape 240' of the support channel hole 240 on the substrate 210 may be elongated. The projected shape 240' of the support channel hole 240 may include a first end portion, a second end portion, and a connection portion connecting the first end portion and the second end portion. An example of a support channel hole 240 having a dumbbell-shaped projected shape 240' is shown in fig. 6. The dumbbell shape may be composed of a first end portion, a second end portion, and a shank portion as a connecting portion, the first end portion, the shank portion, and the second end portion being arranged in order in the y-direction. It should be noted that the projected shapes 230 'and 240' of the first channel hole 230 and the support channel hole 240 on the substrate 210 are only exemplary, and are not limited to the projected shapes 230 'and 240', and those skilled in the art can design suitable shapes of the first channel hole 230 and the support channel hole 240 according to the specific structural requirements of different memory devices, and the present application does not limit the shapes.

With continued reference to fig. 4, in some embodiments, the step of forming the first channel hole 230 and the support channel hole 240 may include disposing a second etch mask layer 250 on an upper side (in the z-direction) of the first stacked structure 220, and patterning the second etch mask layer 250 using, for example, a photolithography and/or etching process, to form a first channel hole pattern and a support channel hole pattern on the second etch mask layer 250. Thereafter, the first stacked structure 220 may be etched through the pattern region of the second etch mask layer 250, so that the first stacked structure 220 forms the first channel hole 230 and the support channel hole 240 in a desired configuration. For example, the projection shape of the patterned second etch mask layer 250 along the z-direction can be as shown in fig. 6.

In some embodiments, the first stack structure 220 may be etched using, for example, a combination of photolithography and etching processes. In the context of the present invention, some steps, such as planarization, surface cleaning, scum removal, etc., are omitted from the method of fabricating the first channel hole 230 and the support channel hole 240. These are not the focus of the present invention and will not be described further herein. One skilled in the art can add or reduce steps in the manufacturing method of the present invention as needed.

As shown in fig. 7, in some embodiments, there is further included the step of forming a channel sacrifice structure 260 and an initial support structure 270 in the first channel hole 230 and the support channel hole 240, respectively. Illustratively, the channel sacrificial structure 260 and the initial support structure 270 may be formed within the liner first channel hole 230 and the support channel hole 240, respectively, by a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the channel sacrificial structure 260 and the initial support structure 270 penetrate the first stacked structure 220 and extend to the substrate 210.

In some embodiments, the material forming the channel sacrificial structure 260 and the initial support structure 270 may be the same, for example, including polysilicon, metal tungsten, alumina, carbon material, or any combination thereof.

In other embodiments, the material forming the sacrificial trench structure 260 and the initial support structure 270 may be different, for example, the material of the sacrificial trench structure 260 includes polysilicon, metal tungsten, aluminum oxide, carbon material, or any combination thereof. The material of the initial support structure 270 may include a different material than the material used for the channel sacrificial structure 260, of the example materials described above.

Referring to fig. 6, in some embodiments, the first channel holes 230 and the corresponding plurality of channel sacrificial structures 260 are arranged in an array in a plane perpendicular to the z-direction, the array including a plurality of rows extending in the x-direction and a plurality of columns extending in the y-direction. Adjacent two of the initial support structures 270 are spaced apart by a plurality of columns. The first and second ends of the initial support structure 270 are located in two adjacent rows, respectively.

Step S1200, forming a second laminated structure on the first laminated structure, and forming a second laminated structure penetrating through the second laminated structure Two channel holes, wherein the second channel holes are at least partially aligned with corresponding channel sacrificial structures.

As shown in fig. 8, a second stacked structure 310 may be formed on the upper side (in the z-direction) of the first stacked structure. The second stacked structure 310 may be formed by alternately stacking the dielectric layers 221 and the sacrificial layers 222. In some embodiments, the second stacked structure 310 may include a plurality of dielectric layers 221 and a plurality of sacrificial layers 222 alternately stacked in a direction (z direction) perpendicular or substantially perpendicular to the first stacked structure 220.

Illustratively, the plurality of sacrificial layers 222 and the dielectric layers 221 may be alternately formed on the upper surface of the first stacked structure 220 by a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, thereby forming the second stacked structure 310.

In some embodiments, the upper surface of the first stacked structure 220 may be planarized using a process such as Chemical Mechanical Polishing (CMP), so that the first stacked structure 220 may provide a substantially planar upper surface.

As shown in fig. 9, in some embodiments, forming a plurality of second channel holes 320 in the second stacked structure 310 is further included. Illustratively, the second channel hole 320 extends through the second stack structure 310 and is at least partially aligned with the channel sacrificial structure 260.

With continued reference to fig. 8, in some embodiments, the step of forming the second channel hole 320 may be similar to the step of forming the first channel hole 260, and may include disposing a third etch mask layer 330 on an upper side (in the z-direction) of the second stacked structure 310, and patterning the third etch mask layer 330 using, for example, a photolithography and/or etching process to form a second channel hole pattern on the third etch mask layer 330. Thereafter, the second stacked structure 310 may be etched through the pattern region of the third etching mask layer 330, so that the first stacked structure 310 forms the second channel hole 320 of a desired configuration. For example, the projected shape of the patterned third etch mask layer 330 may be as shown in fig. 10. As can be seen from a comparison of fig. 10 and 6, the first channel hole 230 and the second channel hole 320 are formed corresponding to each other, and no pattern is formed at a position of the third etch mask layer 330 corresponding to the support channel hole 240.

In some embodiments, the second stacked structure 310 may be etched using, for example, a combination of photolithography and etching processes to form a second channel hole 320 extending through the second stacked structure 310 and at least partially aligned with the channel sacrificial structure 260.

In some embodiments, the projected shape 320' of the second channel hole 320 on the substrate 210 may be circular (as shown in fig. 10). It should be noted that the projection shape 320' of the second channel hole 320 on the substrate 210 is only an exemplary illustration and is not a limitation, and those skilled in the art can design a suitable shape of the second channel hole 320 according to the specific structural requirements of different memory devices, which is not limited in this application.

Fig. 11 is a process diagram of removing a channel sacrificial structure 260 of a three-dimensional memory according to an embodiment of the present disclosure. As shown in fig. 11, the channel sacrificial structure 260 may be removed through the second channel hole 320, exposing the first channel hole 230. The exposed first channel hole 230 is at least partially aligned with the second channel hole 320. Illustratively, the channel sacrificial structure 260 may be etched using a combination of photolithography and etching processes.

It is understood that since there are no channels in the second stacked structure 310 aligned with the initial support structure 270, the initial support structure 270 is maintained during the process of removing the channel sacrificial structure 260.

As shown in fig. 12, in some embodiments, filling the exposed first channel hole 230 and the second channel hole 320 is further included to form a first channel structure 351 and a second channel structure 352, respectively. Illustratively, first channel structure 351 and second channel structure 352 are at least partially aligned and may form a continuous channel structure 350. For example, a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer may be formed sequentially from the outside to the inside (along the x direction) on the exposed sidewalls of the first and second channel holes 230 and 320. Illustratively, the blocking layer, the charge trapping layer, and the tunneling layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. In some examples, the channel layer can serve as a channel for transporting charges (electrons or holes). The material forming the channel layer is a conductive material, including, for example, polysilicon. The space defined by the channel layer can be filled with a channel filling layer, and the material of the channel filling layer is an insulating material and comprises silicon oxide or silicon oxynitride, for example. In some embodiments, the upper side (in the z-direction) of the channel structure 350 also includes a channel plug through which the channel structure 350 can be interconnected with external circuitry. Illustratively, the material of the channel plug may include, for example, polysilicon.

Illustratively, the blocking layer, the charge trapping layer, and the tunneling layer may be sequentially deposited in sequence using, for example, one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof), after which the channel layer may be deposited on a side of the tunneling layer away from the channel sidewalls.

Step S1300, forming a gate line gap, wherein a part of the gate line gap penetrates through the first laminated structure and the second laminated junction And another portion extending through the second stack and through an upper portion of the initial support structure.

Fig. 13 and 14 are schematic views of a process of forming a gate line slit 360 of a three-dimensional memory according to an embodiment of the present disclosure. As shown in fig. 13, a first etch mask layer 370 including a gate line slit pattern may be disposed on an upper side of the second stacked structure 310. Thereafter, the second stacked structure 310 and the first stacked structure 220 are etched through the pattern region of the first etch mask layer 370 to form a gate line slit 360. The projection of the pattern area of the first etch mask layer 370 onto the substrate 210 at least partially overlaps the projection of the initial support structure 270 onto the substrate 210. Illustratively, the projection of the pattern area may extend in a first direction (e.g., the x-direction) and intersect with a connecting portion (e.g., a dumbbell-shaped handle) of the initial support structure 270 extending in a second direction (e.g., the y-direction).

Fig. 15 is a view of fig. 14 in the x direction. Referring to fig. 14 and 15, in some embodiments, the gate line slit 360 may be formed using, for example, a photolithography and etching process. It should be noted that, under the same etching conditions, the sacrificial layer 222, the dielectric layer 221 and the initial support structure 270 may have a higher etching selectivity. The etching rate of the initial support structure 270 may be less than that of the first stack structure 220, so that when the sacrificial layer 222 and the dielectric layer 221 positioned at the lower side of the pattern region of the first etch mask layer 370 are completely removed during the formation of the gate line slit 360, only a portion of the initial support structure 270 is removed to form the support structure 270'. The dimension of the support structure 270' in the y-direction is larger than the dimension of the gate line slit 360 in the same direction (see fig. 14). The support structure 270' may include a support structure first portion at both sides of the gate line slit 360 and a support structure second portion at one side of the x-direction of the gate line slit 360. The support structure second portion connects the support structure first portions located at both sides of the gate line slit 360. The presence of the support structure 270' may provide an interaction force for the stacked structure (including the first stacked structure 220 and the second stacked structure 310) at both sides of the gate line slit 360 to reduce or even eliminate the tilt of the stacked structure 220.

When the etching of the gate line slit 360 is completed, a portion of the gate line slit 360 is formed to penetrate the first and second stacked structures 220 and 310, and another portion penetrates the second stacked structure 310 and passes through an upper portion of the initial support structure 270. Illustratively, an etching process (e.g., wet etching) etches from the upper sides of the first stacked structure 220 and the initial support structure 270 in the opposite direction z, the etching process has limited etching capability for the initial support structure 270 due to the high etching selectivity of the initial support structure 270 to the first stacked structure 220, and an etchant (e.g., a solution) removes the first stacked structure 220 to form a groove, and as the etching process proceeds, the etchant contacting the initial support structure 270 tends to flow into the groove, so that the etching of the initial support structure 270 is further inhibited, and an etching hole with a large top and a small bottom (like an inverted trapezoid) is formed in the x direction, and the width of the bottom of the etching hole in the y direction is smaller than the width of the gate line slit 360 in the y direction (shown in fig. 14).

In some embodiments, channel structures 350 are arranged in an array in a plane perpendicular to the z-direction, the array including a plurality of rows extending in the x-direction and a plurality of columns extending in the y-direction. Adjacent two support structures 270' are spaced apart by a plurality of columns. The support structure 270' may extend in the y-direction with first and second ends thereof located in two adjacent rows, respectively, and a connecting portion connecting the first and second ends in the y-direction.

The gate line slit 360 may be formed between the above-mentioned adjacent two rows and extend in the x-direction so as to cross the connection portion of the support structure 270'. The gate line slits 360 divide the first and second stacked structures 220 and 310 into a plurality of portions (parallel to the plane formed by zx), each of which is subject to stress. Since the support structure 270' spans two sides of the gate line gap 360, a pulling force can be provided for the first stacked structure 220 and the second stacked structure 310 located at two sides of the gate line gap 360, so as to balance the stress suffered by the first stacked structure 220 and the second stacked structure 310, and the purpose of improving the skew of the first stacked structure 220 and the second stacked structure 310 is achieved.

In some embodiments, further comprising forming a gate layer 380 within the first stacked structure 220 and the second stacked structure 310. Illustratively, the sacrificial layer 222 may be removed through the gate line slit 360, and the gap formed after removing the sacrificial layer 222 may be filled with the gate layer 380. The channel structure 350 may provide mechanical support during the formation of the gate layer 380.

Illustratively, the sacrificial layer 222 may be removed using, for example, a wet etch process, and the gate layer 380 may be formed using one or more thin film deposition processes (e.g., ALD, CVD, PVD, combinations thereof, and the like).

In some embodiments, a high dielectric constant layer may be formed in the voids formed after removal of sacrificial layer 222, for example, using a thin film deposition process, followed by formation of gate layer 380 inside the high dielectric constant layer.

In other embodiments, the high-k layer, the adhesion layer, and the gate layer 380 may be sequentially formed in the voids formed after removing the sacrificial layer 140, using, for example, a thin film deposition process.

Illustratively, the high dielectric constant layer may be, for example, a high dielectric constant material including hafnium oxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide compound, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate, zirconium silicate oxide compound, or the like. The high-k layer using the high-k material can effectively reduce the gate capacitance. The material of the adhesion layer may, for example, comprise titanium, titanium nitride, tantalum nitride, or any combination thereof. The gate layer may, for example, comprise a conductive material of tungsten, cobalt, copper, aluminum, or any combination thereof.

In some embodiments, filling an insulating material in the gate line gap 360 to form a gate line gap structure 390 is further included. In other embodiments, the gate line gap 360 is sequentially filled with a combination of an insulating material and a conductive material to form a gate line gap structure 390. Illustratively, the gate line gap structure 390 may be formed within the gate line gap 360 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

Another aspect of the present application also provides a three-dimensional memory. The three-dimensional memory can be manufactured by any one of the manufacturing methods described in the above embodiments.

Fig. 17 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present application. As shown in fig. 17, the three-dimensional memory includes a first stack structure 220 'and a second stack structure 310'. Illustratively, the first stacked structure 220 'is stacked on the upper side (in the z-direction) of the second stacked structure 310'. The first stacked structure 220 'has a support structure 270' formed therein.

In some embodiments, the three-dimensional memory further includes a substrate 210, the first stacked structure 220 ' is stacked on the substrate 210, and the support structure 270 ' extends through the first stacked structure 220 ' and to the substrate 210.

In some embodiments, the three-dimensional memory further includes a gate line slit structure 390 extending through the second stacked structure 310 'and through a portion of the first stacked structure 220'. A portion of the gate line slit structure 390 penetrates the first and second stack structures 220 'and 310', and another portion penetrates the second stack structure 310 'and penetrates an upper portion of the support structure 270'. The gate line slit structure 390 may extend in the x-direction and the support structure 270' may extend in the y-direction.

In some embodiments, the projected shape of the support structure 270' on a plane perpendicular to the z-direction includes a first end portion, a second end portion, and a connection portion connecting the first end portion and the second end portion, and the gate line slit structure 390 crosses the connection portion. The projection shape includes, for example, a dumbbell shape, which may be composed of a first end portion, a second end portion, and a shank portion, the first end portion, the shank portion, and the second end portion being arranged in this order in the y direction.

In some embodiments, a plurality of channel structures 350 extending through the second stacked structure 310 'and through the first stacked structure 220' and to the substrate 210 are also included. The channel structures 350 are arranged in a plane perpendicular to the z-direction as an array comprising a plurality of rows extending in the x-direction and a plurality of columns extending in the y-direction. Adjacent two support structures 270' are spaced apart by a plurality of columns. The support structure 270' may extend in the y-direction with first and second ends thereof located in two adjacent rows, respectively, and a connecting portion connecting the first and second ends in the y-direction.

In some embodiments, the first stacked structure 220' includes dielectric layers 221 and gate layers 380 alternately stacked in sequence. The first stacked structure 310' also includes dielectric layers 221 and gate layers 380 alternately stacked in sequence.

In some embodiments, the number of gate line slit structures 390 includes a plurality, and each gate line slit structure 390 may penetrate the second stacked structure 310 'in the opposite direction z and extend to at least one support structure 270' in the direction x. The support structure 270' may be located at both sides of the gate line slit structure 390 in the x direction/x direction, or may be located at the middle of the gate line slit structure 390 in the x direction/x direction. Both ends of the support structure 270 'contact the second stacked structure 310' at both sides of the gate line slit structure 390, and a middle portion of the support structure 270 'contacts the gate line slit structure 390 and connects both ends of the support structure 270'.

Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (16)

1. A method of fabricating a three-dimensional memory, wherein the method comprises:

forming a first laminated structure, and forming a channel sacrificial structure and an initial support structure which penetrate through the first laminated structure;

forming a second stacked structure on the first stacked structure and forming a second channel hole penetrating the second stacked structure, wherein the second channel hole is at least partially aligned with the corresponding channel sacrificial structure; and

and forming a grid line gap, wherein one part of the grid line gap penetrates through the first laminated structure and the second laminated structure, and the other part of the grid line gap penetrates through the second laminated structure and extends to the initial support structure.

2. The method of claim 1, wherein the forming of the gate line slit comprises:

forming a first etching mask layer including a gate line slit pattern on the second stacked structure; and

etching the second stacked structure, the first stacked structure, and the initial support structure via the gate line gap pattern to form the gate line gap.

3. The method of claim 2, wherein in the forming of the gate line slit, an etching rate of the initial support structure is less than an etching rate of the first laminate structure, so that at most a portion of the initial support structure corresponding to the gate line slit pattern is removed to form a support structure when the etching is completed.

4. The method of claim 3, wherein the grid line slit extends in a first direction, the support structure extends in a second direction that intersects the first direction,

wherein the first direction and the second direction are both perpendicular to a direction in which the first stacked structure and the second stacked structure are stacked.

5. The method of claim 4, wherein a projected shape of the support structure on a plane in which the first and second directions lie includes a first end portion, a second end portion, and a connection portion connecting the first and second end portions, the gate line slit crossing the connection portion.

6. The method of claim 1, wherein a plurality of the channel sacrificial structures are arranged in an array in a plane perpendicular to a stacking direction of the first and second stacked structures, the array comprising a plurality of rows extending in a first direction and a plurality of columns extending in a second direction, and

a plurality of the columns are spaced between two adjacent initial support structures along the first direction.

7. The method of claim 6, wherein a projected shape of the support structure on the plane includes a first end, a second end, and a connecting portion connecting the first end and the second end, the first end and the second end being located in two adjacent rows, respectively.

8. The method of claim 1, wherein the step of forming a channel sacrificial structure and an initial support structure through the first stack structure comprises:

forming a second etching mask layer comprising a first channel hole pattern and a supporting channel hole pattern on the first laminated structure;

etching the first laminated structure to form a first channel hole and a support channel hole which penetrate through the first laminated structure; and

filling a sacrificial material in the first channel hole and the support channel hole to form the channel sacrificial structure and the initial support structure, respectively.

9. The method of claim 1 or 8, further comprising, before forming the gate line slit:

removing the channel sacrificial structure through the second channel hole to expose the first channel hole; and

and forming a channel structure in the second channel hole and the first channel hole.

10. The method of claim 9, wherein the method further comprises:

forming said first stack on a substrate, an

The initial support structure extends through the first stack and to the substrate, and the channel structure extends through the first stack and the second stack and to the substrate.

11. A three-dimensional memory, comprising:

a first stacking structure through which a support structure is disposed;

a second stacked structure stacked on the first stacked structure; and

a gate line gap structure, a portion of the gate line gap structure penetrating through the first stacked structure and the second stacked structure, and another portion penetrating through the second stacked structure and extending to the support structure.

12. The three-dimensional memory of claim 11, wherein the gate line slit structure extends in a first direction, the support structure extends in a second direction that intersects the first direction,

wherein the first direction and the second direction are both perpendicular to a direction in which the first stacked structure and the second stacked structure are stacked.

13. The three-dimensional memory according to claim 12, wherein a projected shape of the support structure on a plane in which the first direction and the second direction are located includes a first end portion, a second end portion, and a connection portion connecting the first end portion and the second end portion, and the gate line slit crosses the connection portion.

14. The three-dimensional memory of claim 11, further comprising:

a channel structure extending through the first stack structure and the second stack structure,

wherein a plurality of the channel structures are arranged in an array in a plane perpendicular to a stacking direction of the first and second stacked structures, the array comprising a plurality of rows extending in a first direction and a plurality of columns extending in a second direction, an

Along the first direction, a plurality of columns are spaced between two adjacent support structures.

15. The three-dimensional memory according to claim 14, wherein a projected shape of the support structure on the plane includes a first end portion, a second end portion, and a connecting portion connecting the first end portion and the second end portion, the first end portion and the second end portion being respectively located in two adjacent rows.

16. The three-dimensional memory of claim 11, wherein the number of gate line slit structures comprises a plurality, each gate line slit structure extending along the first direction to at least one of the support structures.

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