CN114334809A - Method for manufacturing interconnection structure - Google Patents
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- CN114334809A CN114334809A CN202210229005.6A CN202210229005A CN114334809A CN 114334809 A CN114334809 A CN 114334809A CN 202210229005 A CN202210229005 A CN 202210229005A CN 114334809 A CN114334809 A CN 114334809A
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Abstract
The invention provides a method for preparing an interconnection structure, which comprises the following steps: providing a substrate, and forming a first metal layer, a second metal layer and a metal through hole for connecting the first metal layer and the second metal layer on the substrate, wherein the forming of the metal through hole comprises the following steps: and carrying out optical simulation graphic design on the metal through holes according to the extending directions and the distances of the metal wires in the first metal layer and the second metal layer so as to correct the metal through holes. According to the invention, the metal through holes are corrected through the optical simulation graph design according to the extending direction and the distance of the metal wires in the first metal layer and the second metal layer, the optical simulation graph design is used for converging the direction which can not be limited by the conventional hard mask layer, and further the short circuit of the metal wires at two sides of the metal through holes of a legal person caused by the undersize distance of the metal wires is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing an interconnection structure.
Background
The manufacture of semiconductor devices must go through a series of process flows that include various semiconductor device processing steps such as etching and photolithography. The conventional process flow is divided into two main sub-process flows, namely Front End of Line (FEOL) and Back End of Line (BEOL). The back end of the line process may include formation of metal layers, and formation of metal interconnects and vias between different layers of the wafer. Interconnect structures are important structures for achieving electrical connections between semiconductor chip devices, and various interconnect structures and formation processes, such as copper interconnect structures, have been developed.
In the advanced semiconductor process, the minimum Pitch ratio (Pitch) of the metal routing is reduced as much as possible in the back-end process in order to increase the density of the circuit routing, but the circuit routing includes a large number of Via structures (Via) in addition to the metal routing to meet the functional requirement of jumper connection, but under the complex condition that the current layer metal and the Via structures are added at such a small Pitch, the vias are easily short-circuited with the metal wires on both sides.
Disclosure of Invention
The invention aims to provide a method for manufacturing an interconnection structure, which is used for correcting a metal through hole so as to avoid short circuit of metal wires at two sides of the metal through hole due to too small space between the metal wires.
To achieve the above object, the present invention provides a method for manufacturing an interconnect structure, comprising: providing a substrate, and forming a first metal layer, a second metal layer and a metal through hole for connecting the first metal layer and the second metal layer on the substrate, wherein the forming of the metal through hole comprises the following steps: and carrying out optical simulation graphic design on the metal through holes according to the extending directions and the distances of the metal wires in the first metal layer and the second metal layer so as to correct the metal through holes.
Optionally, the first metal layer is a lower metal layer, the second metal layer is an upper metal layer, an extending direction of the first metal layer is perpendicular to an extending direction of the second metal layer, and the first metal layer and the second metal layer are perpendicular to the metal through hole.
Optionally, the first metal layer includes at least two first metal wires extending along a first direction, and a first distance is formed between adjacent first metal wires; the second metal layer comprises at least two second metal wires extending along a second direction, and a second space is formed between every two adjacent second metal wires; wherein the first pitch is smaller than the second pitch, the optical simulation graphical design comprising a dimension that retracts the metal vias in the second direction; the first pitch is greater than the second pitch, and the optical simulation graphical design includes a dimension that shrinks the metal vias inward along the first direction.
Optionally, the first pitch is smaller than or equal to the second pitch, and the optical simulation graphic design further includes expanding the size of the metal via along the first direction; the first distance is larger than the second distance, and the optical simulation graphic design further comprises expanding the size of the metal through holes along the second direction.
Optionally, the modified metal through hole has an oval transverse cross section, and a long axis of the oval extends along an extending direction in which the distance between the metal wires in the first metal layer and the second metal layer is small.
Optionally, an included angle between the side wall of the metal through hole and the first metal layer is 85-90 °.
Optionally, the size of the metal through hole which is retracted inwards along the first direction or the second direction is 1 nm-10 nm.
Optionally, the first metal layer and the second metal layer are both copper metal layers.
Optionally, an inter-metal dielectric layer is further formed between the first metal layer and the second metal layer, and the metal via penetrates through the inter-metal dielectric layer.
Optionally, the forming process of the metal via includes:
designing a mask plate of the metal through hole according to the optical simulation graph;
forming a hard mask layer on the intermetallic dielectric layer by using the mask;
etching the intermetallic dielectric layer to form a through hole penetrating through the intermetallic dielectric layer;
and filling a metal material in the through hole to form a metal through hole.
In summary, the present invention provides a method for manufacturing an interconnect structure, which performs an optical simulation pattern design on a metal via connecting a first metal layer and a second metal layer according to an extending direction and a distance between metal wires in the first metal layer and the second metal layer to correct the metal via, so as to converge a direction that an existing hard mask layer cannot be limited by the optical simulation pattern design, thereby avoiding a short circuit between the metal wires at two sides of the metal via due to an excessively small distance between the metal wires.
Drawings
FIG. 1A is a schematic diagram of an interconnect structure;
FIG. 1B is a schematic diagram of the interconnect structure formed on the silicon wafer after OPC correction in FIG. 1A;
fig. 2A is a schematic diagram illustrating a metal via correction in an interconnect structure according to an embodiment of the invention;
fig. 2B is a schematic diagram illustrating a metal via correction in an interconnect structure according to another embodiment of the invention;
FIG. 2C is a schematic diagram of a modified interconnect structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a modified interconnect structure of a metal via under electron microscope.
Wherein the reference numerals are:
m1 — first metal layer; m2 — second metal layer; V1-Metal Via
a1, a2 — the inward dimension of the radius of the metal via; b1, b2 — the expanded size of the radius of the metal via;
d1 — first pitch; d2 — second spacing.
Detailed Description
The method for fabricating the interconnect structure of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
With the rapid development of semiconductor technology, the feature size of a chip is continuously reduced, and the photolithography wavelength used in the semiconductor process is already far larger than the critical feature size (CD), which makes the optical proximity effect caused by diffraction, interference, etc. a critical factor affecting the photolithography process. Optical Proximity Correction (OPC) is a technique for solving the problem of distortion of a lithographic pattern, typically the phenomenon of line-end shortening edges after lithography, to the greatest possible extent by correcting a reticle pattern. In addition, as the feature size of the line width is continuously reduced, Mask Error Effect (MEEF) of an exposure pattern, especially a through hole structure, is also significantly increased, and accordingly, the small fluctuation of the pattern size of the Mask may cause the huge fluctuation of the line width of the pattern on the silicon wafer.
FIG. 1A is a schematic diagram of an interconnect structure, and FIG. 1B is a schematic diagram of the interconnect structure formed on a silicon wafer after OPC correction in FIG. 1A. As shown in fig. 1A and 1B, the first metal layer M1 and the second metal layer M2 are connected by a metal via V1 to form an interconnect structure. In the latter process, in order to increase the density of the circuit windings, the minimum Pitch ratio (Pitch) of the metal windings is reduced as much as possible, as shown in fig. 1A, the distance between two adjacent metal wires in the first metal layer M1 is small, and the etched metal via V1 is likely to cause short circuit of the metal wires on both sides. Before the metal through hole V1 is etched, the conventional Optical Proximity Correction (OPC) is generally used to correct the problems of the line width variation, edge placement error, pattern fracture, pattern bridging and other photolithographic pattern deformations of the through hole during the photolithography process within the optimum photolithography condition and the set focal depth energy range, and the short circuit problem caused by the small metal wire spacing is not well solved. As shown in fig. 1B, after performing conventional OPC correction on the target interconnect structure shown in fig. 1A, there is still a risk that the metal via will cause a short circuit between the metal wires on both sides.
In order to solve the above problems, this embodiment provides a method for manufacturing an interconnect structure, in which an optical simulation pattern design is performed on metal vias connecting a first metal layer and a second metal layer according to an extending direction and a distance between metal wires in the first metal layer and the second metal layer to correct the metal vias, so that the optical simulation pattern design can be used to converge a direction in which a hard mask layer cannot be limited, thereby avoiding a short circuit of the metal wires at two sides of the metal vias due to an excessively small distance between the metal wires.
The present embodiment provides a method for manufacturing an interconnect structure, including: providing a substrate, and forming a first metal layer, a second metal layer and a metal through hole for connecting the first metal layer and the second metal layer on the substrate; wherein the forming of the metal via includes: and carrying out optical simulation graphic design on the metal through holes according to the extending directions and the distances of the metal wires in the first metal layer and the second metal layer so as to correct the metal through holes.
As shown in fig. 2A, the first metal layer M1 is a lower metal layer, the second metal layer M2 is an upper metal layer, the extending direction of the first metal layer M1 is perpendicular to the extending direction of the second metal layer M2, and the first metal layer M1 and the second metal layer M2 are perpendicular to the metal via V1. The first metal layer M1 includes at least two first metal wires extending along a first direction (e.g., an X direction), and a first distance D1 is provided between adjacent first metal wires M1; the second metal layer M2 includes at least two second metal wires extending along a second direction (e.g., Y direction), and a second distance D2 is between adjacent second metal wires M2. When the first pitch D1 is smaller than the second pitch D2, the optical simulation pattern design includes a dimension of the metal via being retracted in the second direction, as shown in fig. 2A, the dimension of the metal via V1 is retracted in a second direction (Y direction) a1, i.e., a direction perpendicular to the extending direction of the metal layer with a small metal wire pitch. In other examples of the present invention, when the spacing between adjacent metal wires in the lower metal layer is larger than the spacing between adjacent metal wires in the upper metal layer, the optical simulation pattern design includes a dimension that is retracted in the first direction (Y direction) by the metal via V1; when the distance between the adjacent metal wires in the lower metal layer is equal to the distance between the adjacent metal wires in the upper metal layer, and the metal wire short circuit exists in the metal via V1, the size of the metal via V1 may be selectively corrected by using an optical simulation pattern design, and since the etched metal via V1 is generally trapezoidal, the size of the metal via V1 in the extending direction (second direction) of the upper metal layer is preferably corrected.
Further, in some embodiments of the present invention, after the dimension of the metal via V1 in the first direction or the second direction is correspondingly shrunk, the optical simulation graphic design further includes expanding the dimension of the metal via V1 in the second direction or the first direction. As shown in fig. 2B, when the first distance D1 between the adjacent metal wires in the first metal layer M1 is smaller than the second distance D2 between the adjacent metal wires in the second metal layer M2, the size of the metal via V1 is reduced inward a1 along the second direction (Y direction), and then the size of the metal via V1 is expanded B1 along the first direction (X direction). Accordingly, in other embodiments of the present invention, when the first distance D1 between adjacent metal wires in the first metal layer M1 is greater than the second distance D2 between adjacent metal wires in the second metal layer M2, the size of the metal via V1 is expanded by b1 in the second direction (Y direction) after the size of the metal via V1 is retracted by a1 in the first direction (X direction).
When the first distance D1 between the adjacent first metal layers M1 is too small, the metal wires of the first metal layers M1 on both sides of the metal via V1 are easily short-circuited by etching the metal via V1, the dimension of the metal via V1 is designed to be retracted a1 along the second direction (Y direction) by an optical simulation pattern, and then the dimension of the metal via V1 is retracted b1 along the first direction (X direction), so that the problem of depth of field of lithography exposure caused by the too small dimension area of the lithography pattern after the dimension of the metal via V1 is retracted a1 along the second direction or the problem of via open circuit caused by the dry etching dimension load effect can be avoided.
FIG. 2C is a schematic diagram of a modified interconnect structure. As shown in fig. 2C, the transverse cross section of the modified metal via V1 is an ellipse, and the major axis of the ellipse extends along the extending direction in which the distance between the metal wires in the first metal layer M1 and the second metal layer M2 is smaller, specifically, the first distance D1 between the first metal wires in the first metal layer M1 is smaller than the second distance D2 between the second metal wires in the second metal layer M2, the cross section of the modified metal via V1 is an ellipse, and the major axis of the ellipse extends along the extending direction of the first metal layer M1 (X direction), so as to avoid short circuit between the metal wires at two sides of the metal via due to the too small distance between the metal wires.
In the embodiment, the range of the a1 of the size of the metal through hole V1 which is retracted along the first direction or the second direction is 1 nm-10 nm, for example, a1 is 2nm, 4nm or 6 nm; the size of the metal through hole V1 extends along the first direction or the second direction, the range of b1 is 1 nm-8 nm, for example, b1 is 1nm, 3nm or 5 nm. The distance between the adjacent metal vias V1 is greater than the first spacing D1 between the first metal wires in the first metal layer M1, and further, as shown in fig. 2C, the distance between the metal vias V1 disposed on the adjacent second metal wires is greater than the first spacing D2 between the second metal wires in the second metal layer M2, and the distance between the metal vias V1 disposed on the adjacent second metal wires is greater than the first spacing D1 between the first metal wires in the first metal layer M1. Preferably, the sizes of the metal vias V1 in the same layer are the same in the same direction, i.e., a1= a2, and b1= b 2. In other embodiments, the size of the metal via V1 at the same layer, which is contracted or expanded in the same direction, may also be adjusted according to the actual circuit structure, and is not limited herein.
It should be noted that, here, the dimension of the metal through hole V1 contracting or expanding in the first direction or in the second direction means radially compressing or stretching in the first direction or in the second direction with the center of the original metal through hole as an origin, and in this embodiment, the radially compressing or stretching in the first direction or in the second direction is both bilaterally symmetric compression or stretching. In other embodiments of the present invention, the size of the metal via V1 may be compressed or stretched in a single direction, or in a second direction.
In this embodiment, an intermetal dielectric layer is further formed between the first metal layer M1 and the second metal layer M2, and the metal via V1 penetrates through the intermetal dielectric layer. The first metal layer and the second metal layer are both copper (Cu) metal layers, for example, and the material of the inter-metal dielectric layer may include a low dielectric constant (k value less than 5) material or an ultra-low dielectric constant (k value less than 3) material. For example, the inter-metal dielectric layer may be silicon dioxide, fluorine-doped silicon dioxide, a porous structure dielectric layer, or the like. The metal through hole V1 is filled with contact metal, and the contact metal includes copper (Cu) or tungsten (W).
In the method for fabricating an interconnect structure provided in this embodiment, the forming process of the metal via includes: and designing a mask of the metal through hole according to an optical simulation graph, forming a hard mask layer on the intermetallic dielectric layer by adopting the mask, etching the intermetallic dielectric layer to form a through hole penetrating through the intermetallic dielectric layer, and filling a metal material in the through hole to form the metal through hole.
Specifically, first, a first metal layer and an inter-metal dielectric layer are sequentially formed on a substrate; then, according to the distance between the metal wires in different metal layers in the internal connection line structure to be prepared, carrying out optical simulation graph design on the size of the metal through holes for connecting the different metal layers; then, designing a mask plate of the metal through hole according to an optical simulation graph, and forming a hard mask layer with a metal through hole pattern on the intermetallic dielectric layer by adopting the mask plate; etching the intermetallic dielectric layer according to the hard mask layer to form a through hole penetrating through the intermetallic dielectric layer, and filling a metal material in the through hole to form a metal through hole; and forming an upper metal layer on the intermetallic dielectric layer and the metal through hole after the metal through hole is formed.
In the prior art, when a metal through hole is formed by etching, the hard mask layer on the inter-metal dielectric layer cannot well limit the etching direction of the metal through hole, as shown in fig. 1B, in this embodiment, a mask of the metal through hole is formulated by an optical simulation pattern design to converge the direction that the existing hard mask layer cannot limit, so as to correct the metal through hole, and avoid short circuit of metal wires at two sides of the metal through hole due to too small distance between the metal wires. Fig. 3 is a schematic structural diagram of a metal via formed by the above method. As shown in fig. 3, the top of the metal via is rounded and almost has no loss, and the included angle θ between the sidewall of the metal via and the first metal layer M1 is 90 ° -85 °, which is close to a vertical angle. Therefore, by adopting the method for manufacturing the interconnect structure provided by the embodiment, the connection performance of the metal through holes is good, short circuit of the metal wires on two sides of the metal through holes due to too small space between the metal wires is avoided, and the performance of the interconnect structure is good.
It should be noted that the optical simulation pattern design in this embodiment may replace the existing Optical Proximity Correction (OPC), or may correct the metal via hole based on the existing Optical Proximity Correction (OPC), so as to achieve a better etching effect.
In summary, the present invention provides a method for manufacturing an interconnect structure, which performs an optical simulation pattern design on a metal via connecting a first metal layer and a second metal layer according to an extending direction and a distance between metal wires in the first metal layer and the second metal layer to correct the metal via, so as to converge a direction in which an existing hard mask layer cannot be limited by the optical simulation pattern design, thereby avoiding a short circuit of the metal wires at two sides of the metal via due to an excessively small distance between the metal wires.
It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the structural embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for fabricating an interconnect structure, comprising:
providing a substrate, and forming a first metal layer, a second metal layer and a metal through hole for connecting the first metal layer and the second metal layer on the substrate, wherein the forming of the metal through hole comprises the following steps: and carrying out optical simulation graphic design on the metal through holes according to the extending directions and the distances of the metal wires in the first metal layer and the second metal layer so as to correct the metal through holes.
2. The method of claim 1, wherein the first metal layer is a lower metal layer, the second metal layer is an upper metal layer, the extending direction of the first metal layer is perpendicular to the extending direction of the second metal layer, and the first metal layer and the second metal layer are perpendicular to the metal via.
3. The method of claim 2, wherein the first metal layer comprises at least two first metal lines extending along a first direction, and a first distance is formed between adjacent first metal lines; the second metal layer comprises at least two second metal wires extending along a second direction, and a second space is formed between every two adjacent second metal wires; wherein the first pitch is smaller than the second pitch, the optical simulation graphical design comprising a dimension that retracts the metal vias in the second direction; the first pitch is greater than the second pitch, and the optical simulation graphical design includes a dimension that shrinks the metal vias inward along the first direction.
4. The method of claim 3, wherein the first pitch is less than or equal to the second pitch, and the optical simulation pattern design further comprises expanding the size of the metal via along the first direction; the first distance is larger than the second distance, and the optical simulation graphic design further comprises expanding the size of the metal through holes along the second direction.
5. The method of claim 4, wherein the modified metal vias have elliptical cross-sections, and the major axes of the elliptical cross-sections extend along the direction of extension of the first metal layer and the second metal layer with the smaller metal wire spacing.
6. The method of claim 5, wherein an angle between the sidewall of the metal via and the first metal layer is in a range of 85 ° -90 °.
7. The method of claim 5, wherein the metal via is tapered along the first direction or the second direction to a dimension of 1nm to 10 nm.
8. The method of claim 1, wherein the first metal layer and the second metal layer are both copper metal layers.
9. The method of claim 1, wherein an inter-metal dielectric layer is further formed between the first metal layer and the second metal layer, and the metal via penetrates through the inter-metal dielectric layer.
10. The method of claim 9, wherein the forming of the metal via comprises:
designing a mask plate of the metal through hole according to the optical simulation graph;
forming a hard mask layer on the intermetallic dielectric layer by using the mask;
etching the intermetallic dielectric layer to form a through hole penetrating through the intermetallic dielectric layer;
and filling a metal material in the through hole to form a metal through hole.
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Application publication date: 20220412 |