CN114333952A - Memory operation circuit - Google Patents

Abstract

The application provides a memory operation circuit, which comprises a first chip, a second chip and a plurality of data pins. The first chip and the second chip are stacked in a three-dimensional mode, and the plurality of data pins are data pins of the first chip and are arranged in a two-dimensional array mode. The first chip includes a plurality of memory blocks, each memory block including a plurality of memory cells. The second chip comprises a plurality of operation blocks which are in one-to-one correspondence with the storage blocks, and each operation block comprises a read-write circuit and an intra-block operation circuit connected with the read-write circuit. According to the storage operation circuit, the first chip and the second chip are stacked in a three-dimensional mode, so that the data pins can be arranged in a two-dimensional array mode, the number of the data pins is not limited by the side length of the storage, the data pins can be read and written and transmit data which are more than one line of the existing storage to participate in operation in one reading and writing period, the bandwidth is improved, and the operation speed is further improved.

Description

Memory operation circuit

Technical Field

The present application relates to the field of integrated circuit technology, and more particularly, to a memory operation circuit.

Background

The storage operation circuit is a basic component circuit in the computer and is used for executing operation tasks in the computer.

At present, a common memory operation circuit includes two circuit modules located in the same chip and a plurality of data pins for data communication, where a memory is disposed in a first circuit module and includes a plurality of memory cells arranged in a two-dimensional array and a read/write circuit, an operation circuit is disposed in a second circuit module, and the data pins are located on one or more sides of the first circuit module and arranged in a one-dimensional vector manner. In one read-write cycle, data of one row in the memory can be read and written at most and transmitted to participate in operation.

However, the memory operation circuit in the same chip uses a row and column selection mechanism to read and write data stored in the memory, so that the bandwidth is limited, the operation speed is slow, and the memory operation circuit cannot be applied to high-level parallel operation tasks such as a neural network.

Disclosure of Invention

The application provides a memory operation circuit for improving operation speed.

In a first aspect, the present application provides a memory operation circuit, including: the device comprises a first chip, a second chip and a plurality of data pins; wherein the first chip is stacked with the second chip in three dimensions; the plurality of data pins are data pins of the first chip and are arranged in a two-dimensional array;

the first chip comprises a plurality of memory blocks; each memory block includes a plurality of memory cells;

the second chip comprises a plurality of operation blocks which are in one-to-one correspondence with the storage blocks; each operation block comprises a read-write circuit and an intra-block operation circuit connected with the read-write circuit.

Further, in the memory operation circuit as described above, for each memory block, one bit line is connected to one or more memory cells in the memory block; the bit lines correspond to the data pins one to one; bit lines correspondingly connected with all the memory cells in one memory block form a group of bit lines; the group of bit lines corresponds to a group of data pins;

the read-write circuit is in communication connection with a plurality of storage units in the storage block through a group of bit lines in the storage block corresponding to the operation block and a group of data pins corresponding to the group of bit lines.

Further, the memory operation circuit as described above, the memory unit, for storing data required for operation; wherein, one memory cell is used for storing one or more bits of data;

the read-write circuit is used for reading out the data stored in the storage unit through a data pin corresponding to the storage block corresponding to the arithmetic block and a bit line connected with the storage unit in the storage block corresponding to the arithmetic block, and transmitting the read-out data to the intra-block arithmetic circuit connected with the read-out data; in one read-write cycle, the read-write circuit is used for reading data stored in one or more target storage units in a storage block corresponding to the operation block;

the intra-block operation circuit is used for receiving the data transmitted by the read-write circuit connected with the intra-block operation circuit and operating the received data to obtain a first operation result; wherein the first operation result comprises an intermediate operation result or a final operation result.

Further, as for the storage operation circuit described above, when the first operation result obtained by the intra-block operation circuit is the final operation result, the read-write circuit is further configured to obtain the first operation result of the intra-block operation circuit connected thereto, and write the first operation result into the storage unit through the bit line connected to the storage unit in the storage block corresponding to the operation block via the data pin corresponding to the storage block corresponding to the operation block; in one read-write cycle, the read-write circuit is used for writing the first operation result into one or more target storage units in the storage block corresponding to the operation block.

Further, the memory operation circuit as described above, the operation block further includes: a register;

the register is connected with the read-write circuit and the intra-block operation circuit and used for storing a first operation result obtained by the intra-block operation circuit; when a first operation result obtained by the intra-block operation circuit is a final operation result, enabling a read-write circuit connected with the intra-block operation circuit to write the stored first operation result into a storage unit in a storage block corresponding to the operation block;

the register is also used for storing data read by the read-write circuit from one or more target storage units in the storage block corresponding to the operation block, and transmitting the data to the intra-block operation circuit.

Further, the memory operation circuit as described above, the operation block further includes: an intra-block control circuit; the intra-block control circuit is connected with the read-write circuit, and the read-write circuit is connected with the storage units in the storage blocks corresponding to the operation blocks through gate lines;

the intra-block control circuit is used for generating gating signals; the strobe signal is used for selecting one or more storage units from the storage blocks corresponding to the operation blocks in each read-write cycle as target storage units for data reading or data writing.

Further, the memory operation circuit as described above, the intra-block control circuit is further connected to the intra-block operation circuit and the register;

the intra-block control circuit is also used for generating an intra-block control signal; the intra-block control signal is used for controlling the read-write circuit, reading data stored in a target storage unit in a storage block corresponding to the operation block in the read-write period, and transmitting the read data to a register connected with the intra-block control signal;

the intra-block control signal is further used for controlling the intra-block operation circuit, receiving data transmitted by a register connected with the intra-block operation circuit, performing operation on the received data, and transmitting an obtained first operation result to the register connected with the intra-block operation circuit, so that the register stores the first operation result under the control of the intra-block control signal.

Further, the storage operation circuit as described above, when the first operation result obtained by the intra-block operation circuit is the final operation result, the intra-block control signal is further configured to control the read/write circuit to obtain the first operation result from the register connected thereto, and write the first operation result into the target storage unit in the storage block corresponding to the operation block in the read/write cycle.

Further, the memory operation circuit as described above, further comprising: a top-level arithmetic circuit;

the top-level operation circuit is respectively connected with the registers in each operation block and used for obtaining the intermediate operation results stored in the registers and carrying out top-level operation based on the obtained intermediate operation results to obtain the final operation result.

Further, the memory operation circuit as described above, further comprising: a top level control circuit;

the top control circuit is connected with the top operational circuit and used for generating a top control signal; the top control signal is used for controlling the top operational circuit, acquiring the intermediate operational result stored in each register in each read-write cycle, and performing top operation based on a plurality of intermediate operational results acquired in all the read-write cycles to acquire a final operational result.

The application provides a memory operation circuit, which comprises a first chip, a second chip and a plurality of data pins. The first chip and the second chip are stacked in a three-dimensional mode, and the plurality of data pins are data pins of the first chip and are arranged in a two-dimensional array mode. The first chip includes a plurality of memory blocks, each memory block including a plurality of memory cells. The second chip comprises a plurality of operation blocks which are in one-to-one correspondence with the storage blocks, and each operation block comprises a read-write circuit and an intra-block operation circuit. That is to say, in the memory operation circuit provided by the application, the first chip and the second chip are stacked in three dimensions, so that the data pins can be arranged in a two-dimensional array, the number of the data pins is not limited by the side length of the memory, and in one read-write period, data which is more than one line in the existing memory can be read and written and transmitted to participate in operation, thereby improving the bandwidth and further improving the operation speed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic structural diagram of a memory operation circuit provided in the prior art of the present application;

fig. 2 is a schematic structural diagram of a memory operation circuit according to an embodiment of the present disclosure;

fig. 3 is a first structural diagram of a memory block and an operation block corresponding to the memory block according to an embodiment of the present disclosure;

fig. 4 is a second structural diagram of a storage block and an operation block corresponding to the storage block according to an embodiment of the present disclosure;

FIG. 5 is a third structural diagram of a memory block and an operation block corresponding to the memory block according to an embodiment of the present disclosure;

fig. 6 is a fourth structural diagram of a storage block and an operation block corresponding to the storage block according to an embodiment of the present disclosure.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of memory-op circuits consistent with aspects of the present application.

The storage operation circuit is a basic component circuit in the computer and is used for executing operation tasks in the computer. At present, a common memory operation circuit includes two circuit modules located in the same chip and a plurality of data pins for data communication, where a memory is disposed in a first circuit module and includes a plurality of memory cells arranged in a two-dimensional array and a read/write circuit, an operation circuit is disposed in a second circuit module, and the data pins are located on one or more sides of the first circuit module and arranged in a one-dimensional vector manner. In one read-write cycle, data of one row in the memory can be read and written at most and transmitted to participate in operation.

In an example, fig. 1 is a schematic structural diagram of a memory operation circuit provided in the prior art of the present application, as shown in fig. 1, a first circuit module 1 is provided with p rows and q columns, a total of p × q memory cells 11 and a read/write circuit 12, each memory cell 11 stores n-bit data, a second circuit module 2 is provided with an operation circuit 21, a control circuit 22 and a register 23, and data pins 3 are provided corresponding to the columns of the memory cells 11, and the number is q. In one read-write cycle (set to T)_2D) At most, one row can be read, written and transmitted, namely q × n bit data participates in the operation.

For example, if 64 rows and 16 columns of 64 × 16 are set in the first circuit module 1, which is 1024 memory cells 11, the number of the data pins 3 is 16, which corresponds to each column of the memory cells 11, that is, at most, 16 × n bits of data can be read and transmitted to participate in the operation in one read/write cycle. Assuming that 1024-bit data is needed to complete one operation, it takes 1024/(16 × n) ═ 64/n read-write cycles T to transmit the data needed for each operation_2DThe bandwidth is 16 Xn/T_2D。

However, the above are located on the same chipThe internal storage arithmetic circuit uses a row and column selection mechanism to read and write the data stored in the memory, and the bandwidth (q multiplied by n/T)_2D) The method is limited, has low operation speed and cannot be suitable for high-level parallel operation tasks of a neural network.

The present application provides a memory operation circuit, which aims to solve the above technical problems in the prior art.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Fig. 2 is a schematic structural diagram of a memory operation circuit according to an embodiment of the present disclosure, and as shown in fig. 2, the memory operation circuit according to the embodiment includes: a first chip 100, a second chip 200, and a plurality of data pins 300. The first chip 100 and the second chip 200 are stacked three-dimensionally. The plurality of data pins 300 are data pins of the first chip 100, and are arranged in a two-dimensional array.

In the present embodiment, the first chip 100 includes a plurality of memory blocks 110. Each memory block 110 includes a plurality of memory cells 111. The second chip 200 includes a plurality of operation blocks 210 in one-to-one correspondence with the memory blocks 110. Each operation block 210 includes a read/write circuit 211 and an intra-block operation circuit 212 connected to the read/write circuit 211.

On the basis of the foregoing embodiment, in an optional implementation manner, for each memory block 110, one bit line is correspondingly connected to one or more memory cells 111 in the memory block 110, fig. 3 is a first structural schematic diagram of the memory block and the corresponding operation block thereof provided in the embodiment of the present application, as shown in fig. 3, in the memory block 110 and the corresponding operation block 210 thereof provided in the embodiment of the present application, one bit line 400 is correspondingly connected to a plurality of memory cells 111 in the memory block 110, where the bit lines 400 are in one-to-one correspondence with the data pins 300 shown in fig. 2, and the bit lines 400 correspondingly connected to all the memory cells 111 in one memory block 110 constitute a group of bit lines 40. A set of bit lines 40 corresponds to a set of data pins 30.

In the present embodiment, the read/write circuit 211 is communicatively connected to a plurality of memory cells 111 in the memory block 110 through a set of bit lines 40 in the memory block 110 corresponding to the operation block 210 and a set of data pins 30 corresponding to the set of bit lines 40.

On the basis of the above embodiment, in an alternative implementation, the storage unit 111 may be configured to store data required for operation. One memory cell 111 is used to store one or more bits of data.

The read/write circuit 211 may be configured to read data stored in the memory cell 111 through the bit line 400 connected to the memory cell 111 in the memory block 110 corresponding to the operation block 210 via the data pin 300 corresponding to the memory block 110 corresponding to the operation block 210, and transfer the read data to the intra-block operation circuit 212 connected thereto. In one read-write cycle, the read-write circuit 211 can read out the data stored in one or more target memory cells in the memory block 110 corresponding to the operation block 210.

The intra-block operation circuit 212 may be configured to receive data transmitted by the read/write circuit 211 connected thereto, and perform an operation on the received data to obtain a first operation result.

The first operation result may be a final operation result of the storage operation circuit or an intermediate operation result, which is not limited in this embodiment.

In addition to the above embodiment, in yet another alternative implementation, when the first operation result obtained by the intra-block operation circuit is the final operation result, the read/write circuit 211 may be further configured to obtain the first operation result of the intra-block operation circuit 212 connected thereto, and write the first operation result into the memory cell 111 through the data pin 300 corresponding to the memory block 110 corresponding to the operation block 210 via the bit line 400 connected to the memory cell 111 in the memory block 110 corresponding to the operation block 210, so that the final operation result may be stored. In one read-write cycle, the read-write circuit 211 may write the first operation result into one or more target memory cells in the memory block 110 corresponding to the operation block 210.

In an example, the first chip 100 includes 64 memory blocks 110, wherein each memory block 110 includes 16 memory cells 111, each memory cell 111 stores n-bit data, accordingly, 64 groups of data pins 30 are disposed on the first chip 100, and each group of data pins 30 includes 4 data pins 300, that is, in one read-write cycle, at most 64 × 4 × n-bit data can be read and written and transmitted to participate in the operation. Assuming that 1024-bit data is required for completing one operation, it takes 1024/(64 × 4 × n) ═ 4/n read-write cycles (T is assumed) to transfer the data required for each operation_3D) Bandwidth of 256 Xn/T_3D。

The memory operation circuit provided by the embodiment comprises a first chip, a second chip and a plurality of data pins. The first chip and the second chip are stacked in a three-dimensional mode, and the plurality of data pins are data pins of the first chip and are arranged in a two-dimensional array mode. The first chip includes a plurality of memory blocks, each memory block including a plurality of memory cells. The second chip comprises a plurality of operation blocks which are in one-to-one correspondence with the storage blocks, and each operation block comprises a read-write circuit and an intra-block operation circuit connected with the read-write circuit. That is to say, in the embodiment of the present application, the first chip and the second chip are stacked in three dimensions, so that the data pins can be arranged in a two-dimensional array, the number of the data pins is not limited by the side length of the memory, and in one read-write period, data that is more than one line in the existing memory can be read and written and transmitted to participate in the operation, thereby increasing the bandwidth and further increasing the operation speed.

On the basis of the foregoing embodiment, fig. 4 is a second schematic structural diagram of a storage block and an operation block corresponding to the storage block provided in the embodiment of the present application, as shown in fig. 4, in the storage block and the operation block corresponding to the storage block provided in the embodiment, the operation block 210 further includes: a register 213.

In this embodiment, the register 213 is connected to the read/write circuit 211 and the intra-block operation circuit 212, and stores a first operation result obtained by the intra-block operation circuit 212. When the first operation result obtained by the intra-block operation circuit 212 is the final operation result, the read/write circuit 211 connected thereto writes the stored first operation result into the memory cell 111 in the memory block 110 corresponding to the operation block 210.

In addition, the register 213 is also used for storing the data read by the read/write circuit 211 from one or more target memory cells in the memory block 110 corresponding to the operation block 210, and transmitting the data to the intra-block operation circuit 212.

In practical applications, the first operation result obtained by the intra-block operation circuit 212 may be stored by using the register 213, so as to perform different subsequent processes for different types of first operation results. In one example, when the first operation result obtained by the intra-block operation circuit 212 is the final operation result, the read/write circuit 211 connected thereto may be caused to write the stored first operation result into the storage unit 111 in the storage block 110 corresponding to the operation block 210, so as to realize the storage of the final operation result.

In yet another example, when the first operation result obtained by the intra-block operation circuit 212 is an intermediate operation result, it indicates that further operation is required on the obtained intermediate result in order to obtain a final operation result.

On the basis of the foregoing embodiment, in an optional implementation manner, the memory operation circuit further includes: and a top operational circuit.

In this embodiment, the top-level arithmetic circuit is connected to the registers 213 in each arithmetic block, and can acquire the intermediate arithmetic results stored in the registers 213, and perform the top-level arithmetic operation based on the acquired intermediate arithmetic results to acquire the final arithmetic result.

On the basis of the foregoing embodiment, in yet another optional implementation manner, the memory operation circuit further includes: and a top layer control circuit.

In this embodiment, the top control circuit is connected to the top arithmetic circuit for generating the top control signal. The top control signal may be used to control the top arithmetic circuit, obtain the intermediate arithmetic results stored in the different registers 213 in different read/write cycles, and perform the top arithmetic operation based on the plurality of intermediate arithmetic results obtained in all the read/write cycles to obtain the final arithmetic result.

In practical applications, after the top-level operation circuit obtains the final operation result through calculation, the obtained final operation result may be transmitted to the registers 213 in one or more operation blocks, so that the read/write circuit 211 connected to the registers 213 writes the final operation result obtained by the registers 213 into the storage unit 111 in the storage block 110 corresponding to the operation block 210, thereby implementing storage of the final operation result.

On the basis of the foregoing embodiment, fig. 5 is a schematic diagram of a third structure of a storage block and an operation block corresponding to the storage block provided in the embodiment of the present application, and as shown in fig. 5, in the storage block and the operation block corresponding to the storage block provided in the embodiment, the operation block 210 further includes: an intra-block control circuit 214. The intra-block control circuit 214 is connected to the read/write circuit 211, and the read/write circuit 211 is connected to the memory cells 111 in the memory block 110 corresponding to the operation block 210 via the gate lines 500.

In this embodiment, the intra-block control circuit 214 can be used to generate a strobe signal. The strobe signal may select one or more memory cells 111 from the memory block 110 corresponding to the operation block 210 as target memory cells 1110 for data reading or data writing in each read/write cycle. The target storage units 1110 selected in different read/write cycles may be the same target storage unit 1110, or may be different target storage units 1110, which is not limited in this embodiment.

In practical applications, the strobe signal may be a high level signal or a low level signal.

In one example, if the memory cells 111 are turned on at a low level, the intra-block control circuit 214 may generate a low level signal corresponding to one memory cell 111 and generate a high level signal corresponding to the other memory cells 111 in one read/write cycle, and transmit the signals to the memory cells 111 through the gate lines 500, where the memory cell 111 receiving the low level signal is the target memory cell 1110 for data reading or data writing in the read/write cycle.

Accordingly, in another example, if the memory cells 111 are turned on at a high level, the intra-block control circuit 214 may generate a high level signal corresponding to one memory cell 111 and generate a low level signal corresponding to the other memory cells 111 in one read/write cycle, and transmit the high level signal to each memory cell 111 through the gate line 500, where the memory cell 111 receiving the high level signal is the target memory cell 1110 for data reading or data writing in the read/write cycle.

On the basis of the foregoing embodiments, fig. 6 is a fourth schematic structural diagram of a memory block and a corresponding operation block thereof provided in the embodiments of the present application, and as shown in fig. 6, in the memory block and the corresponding operation block thereof provided in the embodiments of the present application, an intra-block control circuit 214 is further connected to the intra-block operation circuit 212 and the register 213.

In this embodiment, the intra-block control circuit is also used to generate an intra-block control signal. The intra-block control signal may be used to control the read/write circuit 211 to read out the data stored in the target memory cell 1110 in the memory block 110 corresponding to the operation block in the read/write cycle, and transmit the read data to the register 213 connected thereto.

The intra-block control signal may be used to control the intra-block operation circuit 212 to receive data transmitted from the register 213 connected thereto, perform an operation on the received data, and transmit the obtained first operation result to the register 213 connected thereto, so that the register 213 stores the first operation result under the control of the intra-block control signal.

On the basis of the above embodiment, in an optional implementation manner, when the first operation result obtained by the intra-block operation circuit 212 is the final operation result, the intra-block control signal may be further used to control the read/write circuit 211 to obtain the first operation result from the register 213 connected thereto, and to write the first operation result into the target storage unit 1110 in the storage block 110 corresponding to the operation block 210 in the read/write cycle, so as to store the final operation result.

The storage operation circuit provided by this embodiment controls the storage units through the strobe signal, so that it can be ensured that only the selected target storage unit in one storage block can read or write data in each read-write cycle, and smooth operation is ensured.

In the embodiments provided in the present application, it should be understood that the disclosed memory operation circuit may be implemented in other ways. For example, the above described embodiments of the memory-arithmetic circuit are merely illustrative, and for example, a division of modules is only one division of logic functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of the storage operation circuit or module through some interfaces, and may be in an electrical, mechanical or other form.

Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware form, and can also be realized in a form of hardware and a software functional module.

Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A memory arithmetic circuit, comprising: the device comprises a first chip, a second chip and a plurality of data pins; wherein the first chip is stacked with the second chip in three dimensions; the plurality of data pins are data pins of the first chip and are arranged in a two-dimensional array;

the first chip comprises a plurality of memory blocks; each memory block includes a plurality of memory cells;

the second chip comprises a plurality of operation blocks which are in one-to-one correspondence with the storage blocks; each operation block comprises a read-write circuit and an intra-block operation circuit connected with the read-write circuit.

2. The memory operation circuit according to claim 1, wherein one bit line is connected to one or more memory cells in each memory block; the bit lines correspond to the data pins one to one; bit lines correspondingly connected with all the memory cells in one memory block form a group of bit lines; the group of bit lines corresponds to a group of data pins;

the read-write circuit is in communication connection with a plurality of storage units in the storage block through a group of bit lines in the storage block corresponding to the operation block and a group of data pins corresponding to the group of bit lines.

3. The memory arithmetic circuit of claim 2,

the storage unit is used for storing data required by operation; wherein, one memory cell is used for storing one or more bits of data;

the read-write circuit is used for reading out the data stored in the storage unit through a data pin corresponding to the storage block corresponding to the arithmetic block and a bit line connected with the storage unit in the storage block corresponding to the arithmetic block, and transmitting the read-out data to the intra-block arithmetic circuit connected with the read-out data; in one read-write cycle, the read-write circuit is used for reading data stored in one or more target storage units in a storage block corresponding to the operation block;

the intra-block operation circuit is used for receiving the data transmitted by the read-write circuit connected with the intra-block operation circuit and operating the received data to obtain a first operation result; wherein the first operation result comprises an intermediate operation result or a final operation result.

4. The memory arithmetic circuit of claim 3,

when the first operation result obtained by the intra-block operation circuit is the final operation result, the read-write circuit is further used for obtaining the first operation result of the intra-block operation circuit connected with the read-write circuit, and writing the first operation result into the storage unit through the data pin corresponding to the storage block corresponding to the operation block and the bit line connected with the storage unit in the storage block corresponding to the operation block; in one read-write cycle, the read-write circuit is used for writing the first operation result into one or more target storage units in the storage block corresponding to the operation block.

5. The memory operation circuit according to claim 4, wherein the operation block further comprises: a register;

the register is connected with the read-write circuit and the intra-block operation circuit and used for storing a first operation result obtained by the intra-block operation circuit; when a first operation result obtained by the intra-block operation circuit is a final operation result, enabling a read-write circuit connected with the intra-block operation circuit to write the stored first operation result into a storage unit in a storage block corresponding to the operation block;

the register is also used for storing data read by the read-write circuit from one or more target storage units in the storage block corresponding to the operation block, and transmitting the data to the intra-block operation circuit.

6. The memory operation circuit according to claim 5, wherein the operation block further comprises: an intra-block control circuit; the intra-block control circuit is connected with the read-write circuit, and the read-write circuit is connected with the storage units in the storage blocks corresponding to the operation blocks through gate lines;

the intra-block control circuit is used for generating gating signals; the strobe signal is used for selecting one or more storage units from the storage blocks corresponding to the operation blocks in each read-write cycle as target storage units for data reading or data writing.

7. The memory arithmetic circuit of claim 6 wherein the intra-block control circuit is further coupled to the intra-block arithmetic circuit and the register;

the intra-block control circuit is also used for generating an intra-block control signal; the intra-block control signal is used for controlling the read-write circuit, reading data stored in a target storage unit in a storage block corresponding to the operation block in the read-write period, and transmitting the read data to a register connected with the intra-block control signal;

the intra-block control signal is further used for controlling the intra-block operation circuit, receiving data transmitted by a register connected with the intra-block operation circuit, performing operation on the received data, and transmitting an obtained first operation result to the register connected with the intra-block operation circuit, so that the register stores the first operation result under the control of the intra-block control signal.

8. The memory arithmetic circuit of claim 7,

and when the first operation result obtained by the intra-block operation circuit is the final operation result, the intra-block control signal is also used for controlling the read-write circuit, obtaining the first operation result from the register connected with the read-write circuit, and writing the first operation result into a target storage unit in the storage block corresponding to the operation block in the read-write period.

9. The memory operation circuit according to claim 8, further comprising: a top-level arithmetic circuit;

the top-level operation circuit is respectively connected with the registers in each operation block and used for obtaining the intermediate operation results stored in the registers and carrying out top-level operation based on the obtained intermediate operation results to obtain the final operation result.

10. The memory operation circuit according to claim 9, further comprising: a top level control circuit;

the top control circuit is connected with the top operational circuit and used for generating a top control signal; the top control signal is used for controlling the top operational circuit, acquiring the intermediate operational result stored in each register in each read-write cycle, and performing top operation based on a plurality of intermediate operational results acquired in all the read-write cycles to acquire a final operational result.

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