CN114333938A

CN114333938A - Ferroelectric capacitor write-in circuit and method adaptive to process fluctuation and electronic equipment

Info

Publication number: CN114333938A
Application number: CN202111618117.2A
Authority: CN
Inventors: 杨建国; 罗庆; 张栋林
Original assignee: Institute of Microelectronics of CAS; Beijing Superstring Academy of Memory Technology
Current assignee: Institute of Microelectronics of CAS; Beijing Superstring Academy of Memory Technology
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-04-12

Abstract

The invention discloses a ferroelectric capacitor write-in circuit and method adaptive to process fluctuation and electronic equipment, and relates to the technical field of microelectronics. The circuit comprises: the detection capacitor difference sub-circuit, a difference current mirror circuit connected with the detection capacitor difference sub-circuit through a bit line, and an operation voltage generation module electrically connected with the difference current mirror circuit; when the detection capacitance difference sub-circuit receives a written value, the bit line is controlled to return to zero, a first voltage difference is formed on the bit line, and the first voltage difference is used as an input voltage difference of the difference current mirror circuit; the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values; the operating voltage generation module determines the capacitor operating voltage based on at least three different output voltage difference values, can realize different output voltages to determine the capacitor operating voltage under different working condition scenes, can be self-adaptive to process fluctuation, realizes the adjustment of the capacitor operating voltage, and prolongs the service life of the ferroelectric capacitor.

Description

Ferroelectric capacitor write-in circuit and method adaptive to process fluctuation and electronic equipment

Technical Field

The invention relates to the technical field of microelectronics, in particular to a ferroelectric capacitor writing circuit and method adaptive to process fluctuation and electronic equipment.

Background

The ferroelectric capacitor based on the hafnium Oxide material has the characteristics of high reading and writing speed, low power consumption, nonvolatile storage, good micro-shrinkage, compatibility with Complementary Metal Oxide Semiconductor (CMOS) process, good radiation resistance and the like, thereby having great research heat and wide application scenes in the fields of nonvolatile storage, neural computation and memory logic.

However, all of these application scenarios rely on the stability of the stored logic state and an adequate read window. While the ferroelectric capacitor is easily affected by the operation pulse of the manufacturing process under the advanced node. For example, deposition technique, annealing temperature, doping concentration, and mechanical stress may directly affect the polarization, dielectric constant, and charge defect of the ferroelectric capacitor, which in turn directly affects the lifetime, retention characteristics, and read window of the ferroelectric capacitor. The correct setting of the operating pulse is also particularly important for ferroelectric capacitors because process fluctuations cause the operating pulses required for the device to reach a sufficient read window to be different, too large an operating pulse may reduce the lifetime of the device, and too small an operating pulse may cause the read window of the device to be unsatisfactory.

Under the condition that the process and the device are limited, in order to better optimize the overall performance of the ferroelectric capacitor, the device circuit is more and more mainstream in cooperation optimization, from the viewpoint of a circuit system, the circuit is adaptive to the process and the fluctuation of the device, operation parameters are corrected, the defects on the ferroelectric capacitor device and the deviation of the manufacturing process are made up, and the purposes of optimizing the retention characteristic of the ferroelectric capacitor, ensuring a reading window and prolonging the service life are achieved.

The current writing method is single, after the initial design is set, the use process of the current writing method cannot be changed, or only the whole voltage threshold can be changed, the current writing method cannot follow the fluctuation of the process, and the service life of the ferroelectric capacitor is short due to the fact that the power supply voltage of the circuit is dynamically adjusted. And by adopting a mechanism of large voltage awakening after small voltage reading and writing, although the cycle number of the ferroelectric capacitor can be improved, the influence of process fluctuation is still not eliminated, so that the service life of the ferroelectric capacitor is relatively short.

Disclosure of Invention

The invention aims to provide a ferroelectric capacitor writing circuit, a ferroelectric capacitor writing method and electronic equipment capable of adapting to process fluctuation, which are used for solving the problem of short service life of a ferroelectric capacitor caused in the conventional capacitor voltage writing process.

In a first aspect, the present invention provides a ferroelectric capacitor write circuit adaptive to process fluctuations, the circuit comprising:

the detection capacitor difference sub-circuit, a difference current mirror circuit connected with the detection capacitor difference sub-circuit through a bit line, and an operation voltage generation module electrically connected with the difference current mirror circuit;

the detection capacitance difference sub-circuit is configured to control the bit line to return to zero when a written value is received, form a first voltage difference on the bit line, and use the first voltage difference as an input voltage difference of the differential current mirror circuit;

the differential current mirror circuit configured to determine at least three different output voltage difference values based on the input voltage difference values;

the operating voltage generating module is configured to determine a capacitor operating voltage based on at least three different output voltage difference values, and complete control use of a target ferroelectric capacitor based on the capacitor operating voltage.

Compared with the prior art, the ferroelectric capacitor write-in circuit capable of adapting to process fluctuation provided by the embodiment of the application can control the bit line to return to zero when receiving a written-in value through the detection capacitor difference sub-circuit, form a first voltage difference on the bit line, and take the first voltage difference as an input voltage difference of the differential current mirror circuit; the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values; the operation voltage generation module determines capacitor operation voltage based on at least three different output voltage difference values, and controls and uses the target ferroelectric capacitor based on the capacitor operation voltage, so that different output voltages can be determined to the capacitor operation voltage under different working condition scenes, that is, the operation voltage generation module can be adaptive to process fluctuation, and the adjustment of the capacitor operation voltage is realized, thereby improving the overall robustness of the circuit, ensuring that the target ferroelectric capacitor has an enough reading window, can work correctly, and further improving the service life of the ferroelectric capacitor while using lower power consumption.

In a possible implementation manner, the circuit further includes a shaping sub-circuit and a latch unit, an input end of the shaping sub-circuit is electrically connected with an output end of the differential current mirror circuit, an output end of the shaping sub-circuit is electrically connected with an input end of the latch unit, and an output end of the latch unit is electrically connected with an input end of the operating voltage generating module;

the shaping sub-circuit is configured to shape the output voltage difference;

the latch unit is configured to buffer the output voltage difference after the shaping processing.

In one possible implementation, the detecting capacitance difference sub-circuit includes: the circuit comprises a first ferroelectric capacitor, a first N-type transistor, a second ferroelectric capacitor and a second N-type transistor, wherein the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor are connected through a word line, the drain electrode of the first N-type transistor is connected with the differential current mirror circuit through the bit line, the source electrode of the first N-type transistor is connected with one end of the first ferroelectric capacitor, the other end of the first ferroelectric capacitor is connected with one end of the second ferroelectric capacitor through a plate line, the drain electrode of the second N-type transistor is connected with the differential current mirror circuit through the bit line, and the source electrode of the second N-type transistor is connected with the other end of the second ferroelectric capacitor.

In one possible implementation, the differential current mirror circuit includes: the four groups of differential current mirror units, each group the differential current mirror unit includes a P type transistor and an N type transistor, wherein, each group the source electrode of P type transistor all connects the power, the grid of P type transistor is connected altogether, the drain electrode of P type transistor is connected with the drain electrode of the N type transistor that corresponds, the grid of N type transistor pass through the bit line with first N type transistor or the drain electrode of second N type transistor is connected, the source electrode of N type transistor all connects the power.

In one possible implementation, the operating voltage generating module is configured to determine a capacitor operating voltage based on at least three different output voltage difference values, and complete a control use of a target ferroelectric capacitor based on the capacitor operating voltage, and includes:

the operating voltage generating module is configured to determine a preset maximum operating voltage as the capacitor operating voltage when the output voltage difference is 0, and complete control and use of a target ferroelectric capacitor based on the capacitor operating voltage;

the operating voltage generating module is configured to determine a preset minimum operating voltage as the capacitor operating voltage when the output voltage difference is 1, and complete control and use of a target ferroelectric capacitor based on the capacitor operating voltage.

In a second aspect, the present invention further provides a writing method of a ferroelectric capacitor with adaptive process fluctuation, which is applied to any one of the writing circuits of the ferroelectric capacitor with adaptive process fluctuation in the first aspect, and the method includes:

when the detection capacitance difference sub-circuit receives a written value, the bit line is controlled to return to zero, a first voltage difference is formed on the bit line, and the first voltage difference is used as an input voltage difference of the differential current mirror circuit;

the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values;

the operating voltage generation module determines capacitor operating voltages based on at least three different output voltage difference values, and controls and uses the target ferroelectric capacitor based on the capacitor operating voltages.

In one possible implementation, the circuit further includes a shaping sub-circuit and a latch unit; after the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values, the method further comprises:

the shaping sub-circuit shapes the output voltage difference;

and the latch unit buffers the output voltage difference after the shaping processing.

In one possible implementation manner, the operating voltage generating module determines a capacitor operating voltage based on at least three different output voltage difference values, and completes the control use of the target ferroelectric capacitor based on the capacitor operating voltage, including:

and when the output voltage difference is 0, the operating voltage generating module determines that the preset maximum operating voltage is the capacitor operating voltage, and the control and use of the target ferroelectric capacitor are completed based on the capacitor operating voltage.

and when the output voltage difference is 1, the operating voltage generating module determines that a preset minimum operating voltage is the capacitor operating voltage, and the control and use of the target ferroelectric capacitor are completed based on the capacitor operating voltage.

In a third aspect, the present invention also provides an electronic device, including: one or more processors; and one or more machine readable media having instructions stored thereon that when executed by the one or more processors cause performance of the adaptive process fluctuating ferroelectric capacitance writing method of any one of the second aspects.

Compared with the prior art, the beneficial effects of the ferroelectric capacitor writing method and the electronic device capable of adapting to the process fluctuation provided by the invention are the same as the beneficial effects of the ferroelectric capacitor writing circuit capable of adapting to the process fluctuation in the technical scheme, and the detailed description is omitted here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic circuit diagram of a ferroelectric capacitor write circuit with adaptive process fluctuation according to an embodiment of the present application;

FIG. 2 is a timing diagram illustrating an operation provided by an embodiment of the present application;

FIG. 3 is a schematic flow chart of a ferroelectric capacitor writing method with adaptive process fluctuation according to an embodiment of the present application;

FIG. 4 is a schematic flow chart of another adaptive process fluctuation ferroelectric capacitor writing method provided in the embodiments of the present application;

fig. 5 is a schematic diagram of a hardware structure of a technology level determination device in an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present invention.

Reference numerals:

01-detecting a capacitance difference sub-circuit; 02-differential current mirror circuit; 03-an operating voltage generating module; BL-bit line; 04-a shaping sub-circuit; 05-a latch unit; c₀-a first ferroelectric capacitance; 011-first N-type transistor; c₁-a second ferroelectric capacitance; 012-a second N-type transistor; a-a differential current mirror unit; 021-P type transistor; 022-N type transistors; 30-an electronic device; 301-a processor; 301-1-a first processor; 301-2-a second processor; 302-a communication interface; 303 — a communication line; 304-a memory; 40-chip; 405-bus system.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

Fig. 1 is a schematic circuit diagram illustrating a ferroelectric capacitor writing circuit capable of adapting to process fluctuation according to an embodiment of the present application, where the circuit includes:

the circuit comprises a detection capacitance difference sub-circuit 01, a differential current mirror circuit 02 connected with the detection capacitance difference sub-circuit 01 through a bit line BL, and an operation voltage generation module 03 electrically connected with the differential current mirror circuit 02;

the detection capacitance difference sub-circuit 01 is configured to control the bit line to return to zero when a written value is received, form a first voltage difference on the bit line, and use the first voltage difference as an input voltage difference of the differential current mirror circuit 02;

the differential current mirror circuit 02 configured to determine at least three different output voltage difference values based on the input voltage difference values;

the operating voltage generating module 03 is configured to determine a capacitor operating voltage based on at least three different output voltage difference values, and complete a control use of a target ferroelectric capacitor based on the capacitor operating voltage.

In summary, in the ferroelectric capacitor write-in circuit with adaptive process fluctuation provided in the experimental embodiment of the present application, when receiving a written-in value, the detection capacitance difference sub-circuit may control the bit line to return to zero, form a first voltage difference on the bit line, and use the first voltage difference as an input voltage difference of the differential current mirror circuit; the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values; the operation voltage generation module determines capacitor operation voltage based on at least three different output voltage difference values, and controls and uses the target ferroelectric capacitor based on the capacitor operation voltage, so that different output voltages can be determined to the capacitor operation voltage under different working condition scenes, that is, the operation voltage generation module can be adaptive to process fluctuation, and the adjustment of the capacitor operation voltage is realized, thereby improving the overall robustness of the circuit, ensuring that the target ferroelectric capacitor has an enough reading window, can work correctly, and further improving the service life of the ferroelectric capacitor while using lower power consumption.

In the present application, referring to fig. 1, the circuit further includes a shaping sub-circuit 04 and a latch unit 05, an input terminal of the shaping sub-circuit 04 is electrically connected to an output terminal of the differential current mirror circuit 02, an output terminal of the shaping sub-circuit 04 is electrically connected to an input terminal of the latch unit 05, and an output terminal of the latch unit 05 is electrically connected to an input terminal of the operating voltage generating module 03;

the shaping sub-circuit 04 is configured to shape the output voltage difference;

the latch unit 05 is configured to buffer the output voltage difference after the shaping processing.

In the present application, see FIG. 1, wherein the bit lines BL comprise bit lines BL₁And bit line BL₀As shown in fig. 1, the detection capacitance difference sub-circuit 01 includes: a first ferroelectric capacitor C₀A first N-type transistor 011, a second ferroelectric capacitor C₁And a second N-type transistor 012, wherein a gate of the first N-type transistor 011 and a gate of the second N-type transistor 012 are connected by a word line WL, and a drain of the first N-type transistor 011 is connected by the bit line BL₁A source of the first N-type transistor 011 and the first ferroelectric capacitor C connected to the differential current mirror circuit 02₀Is connected to said first ferroelectric capacitor C₀And the other end of the second ferroelectric capacitor C₁Is connected to the other end of the first N-type transistor 012 through a plate line PL, and the drain of the second N-type transistor 012 is connected to the bit line BL through the bit line BL₀A source of the second N-type transistor 012 connected to the differential current mirror circuit 02, and the second ferroelectric capacitor C₁The other end of the connecting rod is connected.

The first ferroelectric capacitor and the second ferroelectric capacitor are also process detection capacitors, and the ferroelectric capacitor with the smallest unit area can be selected as the first ferroelectric capacitor and the second ferroelectric capacitor.

In the present application, as shown in fig. 1, the differential current mirror circuit 02 includes: four sets of differential current mirror unit A, every group differential current mirror unit A includes a P type transistor 021 and an N type transistor 022, wherein, every group the source electrode of P type transistor 021 is all connected with the power, the grid of P type transistor 021 is connected altogether, the drain electrode of P type transistor 021 and the drain electrode of the N type transistor 022 that corresponds are connected, the grid of N type transistor 022 pass through the bit line BL with first N type transistor 011 or the drain electrode of second N type transistor 012 is connected, the source electrode of N type transistor 022 is all connected with the power.

The shaping subcircuit may include three shapers, the shapers being connected to three sets of differential current mirror units, the latch unit including three latches, each latch being connected to a corresponding shaper.

In this application, the operating voltage generation module configured to determine a capacitor operating voltage based on at least three different output voltage difference values, and to complete a control use of a target ferroelectric capacitor based on the capacitor operating voltage, includes:

Alternatively, the first ferroelectric capacitors C can be individually programmed using standard voltages₀And a second ferroelectric capacitor C₁Write 0 and 1, then bit line BL₁And BL₀Return to zero, word line WL voltage is high, and plate line PL applies a pulse due to first ferroelectric capacitor C₀And a second ferroelectric capacitor C₁Different polarization states can form a voltage difference on the bit line, namely an input voltage difference.

Meanwhile, the bit line is connected to the differential current mirror circuit, so that different output voltage differences corresponding to different input voltage differences can be output by reasonably designing the noise margins of the P-type transistor and the N-type transistor in the differential current mirror circuit, as shown in fig. 1, that is, different ENs are output₀、EN₁、EN₂。

For example, table 1 shows an output voltage difference (EN) provided in the embodiments of the present application₀、EN₁、EN₂) Table corresponding to the relationship of the capacitor operating voltage (V0, V1, V2 or V3), where V0 is greater than V1, V1 is greater than V2, and V2 is greater than V3, as shown in table 1:

TABLE 1

In this application, fig. 2 shows a schematic diagram of an operation timing sequence provided by an embodiment of the present application, and in this application, the first ferroelectric capacitor C may be disposed in combination with fig. 2 and table 1₀ Writing 0 in the second ferroelectric capacitor C₁1 is written, so the voltage of BL1 is higher than the voltage of BL0 when reading. When the voltage difference is small, i.e. the read window is small, the differentiator cannot distinguish, and the output is 0, corresponding to the maximum operating voltage V0. At this time, because the operating voltage cannot completely turn over the ferroelectric domain inside the ferroelectric capacitor due to process fluctuation, the voltage needs to be increased to ensure a sufficient read window and ensure the correctness of the function, that is, the operating voltage of the capacitor is set to the operating voltage V0 which is not the maximum, so that the process fluctuation is avoided, and the sufficient read window is ensured, thereby ensuring the correctness of the function.

Further, referring to fig. 2 and table 1, when the voltage difference is large, that is, all differentiators (i.e., the differential current mirror unit in this application) can sense, the output is 1, and the operating voltage is the minimum V3, because at this time, under the standard voltage, the ferroelectric domain can be completely inverted, and a sufficient readout window is generated, and at this time, the minimum operating voltage V3 is generated, so that the stress applied to the ferroelectric capacitor can be reduced, and the lifetime of the ferroelectric capacitor can be improved.

As another example, referring to fig. 2 and table 1, in the case where there is one voltage difference of 1, the corresponding capacitor operating voltage is V1, and in the case where there are two voltage differences of 1, the corresponding capacitor operating voltage is V2.

Fig. 3 is a schematic flowchart of a ferroelectric capacitor writing method with adaptive process fluctuation according to an embodiment of the present application, which is applied to the ferroelectric capacitor writing circuit with adaptive process fluctuation shown in fig. 1, and as shown in fig. 2, the ferroelectric capacitor writing method with adaptive process fluctuation includes:

step 101: and when receiving a written value, the detection capacitance difference sub-circuit controls the bit line to return to zero, forms a first voltage difference on the bit line, and takes the first voltage difference as an input voltage difference of the differential current mirror circuit.

Step 102: the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values.

Step 103: the operating voltage generation module determines capacitor operating voltages based on at least three different output voltage difference values, and controls and uses the target ferroelectric capacitor based on the capacitor operating voltages.

To sum up, in the ferroelectric capacitor writing method capable of adapting to process fluctuation provided in the embodiment of the present application, when a written value is received by the detection capacitor difference sub-circuit, the bit line is controlled to return to zero, a first voltage difference is formed on the bit line, and the first voltage difference is used as an input voltage difference of the differential current mirror circuit; the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values; the operation voltage generation module determines capacitor operation voltage based on at least three different output voltage difference values, and controls and uses the target ferroelectric capacitor based on the capacitor operation voltage, so that different output voltages can be determined to the capacitor operation voltage under different working condition scenes, that is, the operation voltage generation module can be adaptive to process fluctuation, and the adjustment of the capacitor operation voltage is realized, thereby improving the overall robustness of the circuit, ensuring that the target ferroelectric capacitor has an enough reading window, can work correctly, and further improving the service life of the ferroelectric capacitor while using lower power consumption.

Fig. 4 is a schematic flow chart of another adaptive process fluctuation ferroelectric capacitor writing method provided in this embodiment of the present application, which is applied to the adaptive process fluctuation ferroelectric capacitor writing circuit shown in fig. 1, the circuit further includes a shaping sub-circuit and a latch unit, as shown in fig. 3, the adaptive process fluctuation ferroelectric capacitor writing method includes:

step 201: and when receiving a written value, the detection capacitance difference sub-circuit controls the bit line to return to zero, forms a first voltage difference on the bit line, and takes the first voltage difference as an input voltage difference of the differential current mirror circuit.

Step 202: the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values.

Step 203: and the shaping sub-circuit shapes the output voltage difference.

Step 204: and the latch unit buffers the output voltage difference after the shaping processing.

Step 205: the operating voltage generation module determines capacitor operating voltages based on at least three different output voltage difference values, and controls and uses the target ferroelectric capacitor based on the capacitor operating voltages.

In this application, when the output voltage difference is 0, the operating voltage generation module determines that a preset maximum operating voltage is the capacitor operating voltage, and controls and uses the target ferroelectric capacitor based on the capacitor operating voltage.

All relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

In some possible implementations, the method for writing a ferroelectric capacitor with adaptive process fluctuation may further include a storage module for storing program codes and data of the base station.

The Processing module may be a Processor or a controller, and may be, for example, a Central Processing Unit (CPU), a general-purpose Processor, a Digital Signal Processor (DSP), an Application-Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others. The communication module may be a transceiver, a transceiving circuit or a communication interface, etc. The storage module may be a memory.

When the processing module is a processor, the communication module is a communication interface, and the storage module is a memory, the ferroelectric capacitor writing method capable of adapting to process fluctuation according to the embodiment of the present invention may be the electronic device shown in fig. 5.

Optionally, an embodiment of the present application further provides an electronic device, including: one or more processors; and one or more machine readable media having instructions stored thereon that when executed by the one or more processors cause performance of the adaptive process fluctuating ferroelectric capacitance writing method of any one of the first aspects.

Fig. 5 is a schematic diagram illustrating a hardware structure of an electronic device according to an embodiment of the present invention. As shown in fig. 5, the electronic device 30 includes a processor 301 and a communication interface 302.

As shown in fig. 5, the processor may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present invention. The number of the communication interfaces may be one or more. The communication interface may use any transceiver or the like for communicating with other devices or communication networks.

As shown in fig. 5, the terminal device may further include a communication line 303. The communication link may include a path for transmitting information between the aforementioned components.

Optionally, as shown in fig. 5, the terminal device may further include a memory 304. The memory is used for storing computer-executable instructions for implementing the inventive arrangements and is controlled by the processor for execution. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.

As shown in fig. 5, the memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a Random Access Memory (RAM) or other types of dynamic storage devices that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory may be separate and coupled to the processor via a communication link. The memory may also be integral to the processor.

Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.

In particular implementations, as one embodiment, as shown in FIG. 5, processor 301 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 5.

In one embodiment, as shown in fig. 5, the terminal device may include a plurality of processors, such as the first processor 301-1 and the second processor 301-2 in fig. 5. Each of these processors may be a single core processor or a multi-core processor.

Fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present invention. As shown in fig. 6, the chip 40 includes one or more (including two) processors 301 and a communication interface 302.

Optionally, as shown in FIG. 6, the chip also includes a memory 304, which may include both read-only memory and random access memory, and provides operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).

In some embodiments, as shown in FIG. 6, the memory stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present invention, as shown in fig. 6, by calling an operation instruction stored in the memory (the operation instruction may be stored in the operating system), a corresponding operation is performed.

As shown in fig. 6, a processor, which may also be referred to as a Central Processing Unit (CPU), controls the processing operations of any of the terminal devices.

As shown in fig. 6, the memories may include both read-only memories and random access memories and provide instructions and data to the processor. The portion of memory may also include NVRAM. For example, in applications where the memory, communication interface, and memory are coupled together by a bus system that may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 405 in fig. 6.

As shown in fig. 6, the method disclosed in the above embodiments of the present invention may be applied to a processor, or may be implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

In one aspect, a computer-readable storage medium is provided, in which instructions are stored, and when executed, implement the functions performed by the technology level determination device in the above embodiments.

In one aspect, a chip is provided, where the chip is applied in a terminal device, and the chip includes at least one processor and a communication interface, where the communication interface is coupled with the at least one processor, and the processor is configured to execute instructions to implement the functions performed by the technology level determining device in the foregoing embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A ferroelectric capacitor write circuit adaptive to process fluctuations, the circuit comprising:

2. A process fluctuation adaptive ferroelectric capacitor write circuit as in claim 1, further comprising a shaping sub-circuit having an input electrically connected to an output of said differential current mirror circuit, and a latch unit having an output electrically connected to an input of said latch unit, and an output of said latch unit electrically connected to an input of said operating voltage generating block;

the shaping sub-circuit is configured to shape the output voltage difference;

3. A process fluctuation adaptive ferroelectric capacitor write circuit as in claim 1, wherein the detection capacitance difference sub-circuit comprises: the circuit comprises a first ferroelectric capacitor, a first N-type transistor, a second ferroelectric capacitor and a second N-type transistor, wherein the grid electrode of the first N-type transistor and the grid electrode of the second N-type transistor are connected through a word line, the drain electrode of the first N-type transistor is connected with the differential current mirror circuit through the bit line, the source electrode of the first N-type transistor is connected with one end of the first ferroelectric capacitor, the other end of the first ferroelectric capacitor is connected with one end of the second ferroelectric capacitor through a plate line, the drain electrode of the second N-type transistor is connected with the differential current mirror circuit through the bit line, and the source electrode of the second N-type transistor is connected with the other end of the second ferroelectric capacitor.

4. A ferroelectric, adaptive process fluctuation, capacitive write circuit as recited in claim 3, wherein the differential current mirror circuit comprises: the four groups of differential current mirror units, each group the differential current mirror unit includes a P type transistor and an N type transistor, wherein, each group the source electrode of P type transistor all connects the power, the grid of P type transistor is connected altogether, the drain electrode of P type transistor is connected with the drain electrode of the N type transistor that corresponds, the grid of N type transistor pass through the bit line with first N type transistor or the drain electrode of second N type transistor is connected, the source electrode of N type transistor all connects the power.

5. A ferroelectric, adaptive process swing, capacitance write circuit as recited in claim 4, wherein the operating voltage generation module, configured to determine a capacitance operating voltage based on at least three different differences in the output voltages, to complete the controlled use of a target ferroelectric capacitance based on the capacitance operating voltage, comprises:

6. A process fluctuation adaptive ferroelectric capacitor writing method applied to the process fluctuation adaptive ferroelectric capacitor writing circuit according to any one of claims 1 to 5, the method comprising:

7. A method of adaptive process swing ferroelectric capacitor writing as in claim 6, wherein said circuit further comprises, a shaping subcircuit and a latching unit; after the differential current mirror circuit determines at least three different output voltage difference values based on the input voltage difference values, the method further comprises:

the shaping sub-circuit shapes the output voltage difference;

8. The adaptive process fluctuation ferroelectric capacitor writing method as recited in claim 6, wherein the operation voltage generation module determines a capacitor operation voltage based on at least three different output voltage difference values, and performs a controlled use of a target ferroelectric capacitor based on the capacitor operation voltage, comprising:

9. The adaptive process fluctuation ferroelectric capacitor writing method as recited in claim 6, wherein the operation voltage generation module determines a capacitor operation voltage based on at least three different output voltage difference values, and performs a controlled use of a target ferroelectric capacitor based on the capacitor operation voltage, comprising:

10. An electronic device, comprising: one or more processors; and one or more machine readable media having instructions stored thereon that when executed by the one or more processors cause performance of the adaptive process fluctuating ferroelectric capacitance writing method of any one of claims 6 to 9.