CN114330730A

CN114330730A - Quantum line block compiling method, device, equipment, storage medium and product

Info

Publication number: CN114330730A
Application number: CN202111605750.8A
Authority: CN
Inventors: 胡孟军; 许宏泽; 庄伟峰; 刘�东; 普亚南; 顾炎武; 钱鹏; 肖骁; 钱辰; 柴绪丹; 马运恒
Original assignee: Beijing Institute Of Quantum Information Science
Current assignee: Beijing Institute Of Quantum Information Science
Priority date: 2021-12-25
Filing date: 2021-12-25
Publication date: 2022-04-12

Abstract

The application relates to a quantum circuit block compiling method, a device, equipment, storage medium and a product, which are characterized in that a target logic quantum circuit is converted into a physical quantum circuit matched with a quantum processor topological structure chart according to the quantum processor topological structure chart, the physical quantum circuit is divided into a plurality of sub-circuit block sets according to a plurality of preset bit group sets, and the plurality of bit group sets are obtained by grouping physical bits in the physical quantum circuit according to the quantum processor topological structure chart. The method can reduce the time consumed by sub-line partitioning and improve the efficiency of quantum line partitioning, thereby improving the speed of quantum compiling.

Description

Quantum line block compiling method, device, equipment, storage medium and product

Technical Field

The present application relates to the field of quantum technologies, and in particular, to a quantum circuit block compiling method, apparatus, device, storage medium, and product.

Background

With the development of quantum computers, the number of qubits has increased, which requires better quantum compilers to optimize large-scale quantum wires.

In the related art, an QGo compiler is adopted to divide a large-scale quantum circuit by a brute force search method, a sub-circuit block containing the maximum quantum gate is divided from the large-scale quantum circuit each time, then the gate contained in the sub-circuit block is removed from the original quantum circuit, and a sub-circuit block containing the maximum quantum gate is divided from the rest quantum circuits until the original large-scale quantum circuit is divided.

However, the quantum wire partitioning method in the related art is inefficient, and reduces the speed of quantum compilation.

Disclosure of Invention

In view of the above, it is desirable to provide a quantum line chunking compiling method, device, apparatus, storage medium, and product, which can reduce the time consumed by quantum line chunking, improve the efficiency of quantum line partitioning, and thereby improve the speed of quantum compiling.

In a first aspect, the present application provides a quantum line partitioning method, including:

converting the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart;

dividing the physical quantum circuit into a plurality of sub-circuit block sets according to a plurality of preset bit group sets; the bit group sets are obtained by grouping the physical bits in the physical quantum circuit according to the topological structure chart of the quantum processor;

wherein the running time for dividing the physical quantum wire into the plurality of sub-wire block sets is linear with the number of bits in the physical quantum wire.

In one embodiment, the target logic quantum circuit comprises a single-bit gate and a controllable not gate, wherein the single-bit gate is a gate formed by one bit, and the controllable not gate is a gate formed by two bits;

converting the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart, and the method comprises the following steps:

mapping the logic bits in the target logic quantum circuit into physical bits according to the quantum processor topological structure diagram, and exchanging the sequence of the physical bits in the target logic quantum circuit by adding a quantum exchange gate to obtain an exchanged controllable NOT gate, wherein the exchanged controllable NOT gate can be executed on the quantum processor;

and generating a physical quantum line according to the physical bit, the switched controllable NOT gate and the single bit gate.

In one embodiment, dividing the physical quantum wires into a plurality of sub-wire block sets according to a preset plurality of bit group sets includes:

carrying out layering processing on the first candidate physical quantum circuit to obtain a plurality of circuit layers; the first candidate physical quantum wire is the physical quantum wire without the single-bit gate;

according to a plurality of preset bit group sets, performing line blocking step layer by layer on each line layer in a first candidate physical quantum line to obtain a plurality of controllable NOT sub-line block sets;

and adding a single bit gate into the corresponding controllable NOT gate sub-line block set according to the execution sequence to obtain a plurality of sub-line block sets.

In one embodiment, the line blocking step includes:

searching an initial sub-line block combined by controllable NOT gates in a first layer of a plurality of line layers according to a plurality of preset bit group sets; each initial sub-circuit block comprises at least one controllable NOT gate;

acquiring candidate sub-line blocks according to the number of the controllable NOT gates in the initial sub-line block and the second line layer;

acquiring a sub-line block set according to the number of the candidate sub-line blocks;

and removing the controllable NOT gates in the sub-line block sets in the first candidate physical quantum line to obtain a second candidate physical quantum line, executing a line blocking step on the second candidate physical quantum line until no controllable NOT gate exists in the new candidate physical quantum line, and determining all the obtained sub-line block sets as a plurality of controllable NOT gate sub-line block sets.

In one embodiment, before removing the controllable not gates in the set of sub-line blocks in the first candidate physical quantum line, the method further comprises:

if the number of the controllable NOT gates in the sub-line block set is smaller than the preset number and the current layer is smaller than the total number of the first candidate physical quantum lines, performing incremental processing on the number of bit groups in the plurality of bit group sets to obtain a plurality of new bit group sets;

and according to the new bit group sets, executing a step of obtaining a plurality of controllable NOT sub-line block sets by executing a line blocking step layer by layer on each line layer in the first candidate physical quantum line.

In one embodiment, obtaining the sub-line block set according to the number of candidate sub-line blocks includes:

if the candidate sub-line block is equal to 1, adding a controllable NOT which is matched with the candidate sub-line block in a line layer behind the second line layer into the candidate sub-line block from the second line layer until no controllable NOT which is matched with the candidate sub-line block exists;

and if the number of the controllable NOT gates in the candidate sub-line block is larger than or equal to the preset number, taking the candidate sub-line block as a sub-line block set.

and if the candidate sub-line block is larger than 1 and the current layer number is smaller than the preset maximum search depth, adding the controllable NOT matched with the candidate sub-line block in the second line layer into the candidate sub-line block, acquiring a new candidate sub-line block according to the candidate sub-line block and the number of the controllable NOT in the candidate sub-line block after considering the next layer of the second line layer, and re-executing the step of acquiring the sub-line block set according to the number of the candidate sub-line blocks on the new candidate sub-line block.

if the candidate sub-line block is larger than 1 and the current layer number is larger than or equal to the preset maximum search depth, determining a target candidate sub-line block from the candidate sub-line blocks through a preset random algorithm;

adding the controllable NOT gate matched with the target candidate sub-line block in the line layer after the current layer number into the target candidate sub-line block until no controllable NOT gate matched with the target candidate sub-line block exists;

and if the number of the controllable NOT gates in the target candidate sub-line block is equal to or equal to the preset number, determining the target candidate sub-line block as a sub-line block set.

In one embodiment, obtaining the candidate sub-line block according to the number of controllable not gates in the initial sub-line block and the second line layer comprises:

calculating a cost function according to the number of controllable NOT gates in the initial sub-line block; calculating a heuristic function according to the number of controllable NOT gates matched with the initial sub-line blocks in the second line layer;

generating a cost estimation function according to the cost function and the heuristic function; the cost estimation function represents the number of controllable NOT gates included in the initial sub-line block estimated according to the number of controllable NOT gates in the second line layer;

and determining the sub-circuit block corresponding to the maximum cost estimation function value as a candidate sub-circuit block.

In one embodiment, the method further comprises:

optimizing each sub-line block in the plurality of sub-line block sets in a parallel mode through a preset quantum line synthesis algorithm of quantum topology perception to obtain a plurality of optimized sub-line block sets;

and integrating the sub-line blocks in the optimized sub-line block sets according to the bit group sets corresponding to the sub-line block sets to obtain the optimized quantum line of the target logic quantum line.

In a second aspect, the present application further provides a quantum line partitioning apparatus, including:

the conversion module is used for converting the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart;

the dividing module is used for dividing the physical quantum circuit into a plurality of sub-circuit block sets according to a plurality of preset bit group sets; the bit group sets are obtained by grouping the physical bits in the physical quantum circuit according to the topological structure chart of the quantum processor; wherein a running time for dividing the physical quantum wire into the plurality of sub-wire block sets is linearly related to the number of bits of the physical bits in the physical quantum wire.

In a third aspect, an embodiment of the present application provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the method provided in any one of the foregoing first aspects when executing the computer program.

In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method provided in any one of the embodiments in the first aspect.

In a fifth aspect, this application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the method provided in any one of the embodiments in the first aspect.

The quantum circuit block compiling method, the device, the equipment, the storage medium and the product convert the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart, divide the physical quantum circuit into a plurality of sub-circuit block sets according to a plurality of preset bit group sets, and obtain the quantum circuit block compiling method, the device, the equipment, the storage medium and the product after grouping the physical bits in the physical quantum circuit according to the quantum processor topological structure chart. In the method, firstly, a target logic quantum circuit is converted into a physical quantum circuit according to a topological structure diagram of a quantum processor, then the physical quantum circuit is divided into a plurality of sub-circuit block sets, the time for dividing the physical quantum circuit into the plurality of sub-circuit block sets is in a linear relation with the number of bits in the physical quantum circuit, and the time for dividing the quantum circuit in the prior art is in a power relation with the number of bits of the quantum circuit, so the method in the application reduces the time consumed by quantum circuit block division, and particularly when the number of bits of the physical quantum circuit is large, the time efficiency improved by the method in the embodiment of the application is very obvious, so the method can reduce the time consumed by sub-circuit block division, improve the efficiency of quantum circuit division, and further improve the speed of quantum compiling.

Drawings

FIG. 1 is a diagram of an exemplary embodiment of a quantum wire blocking method;

FIG. 2 is a schematic flow diagram of a quantum wire blocking method in one embodiment;

FIG. 3 is a diagram of the topology of the quantum wire chunking method in one embodiment;

FIG. 4 is a schematic flow chart of a quantum wire blocking method in another embodiment;

FIG. 5 is a schematic diagram of an embodiment of a quantum wire blocking method;

FIG. 6 is a schematic diagram of a quantum gate swap in a quantum wire blocking method in one embodiment;

FIG. 7 is a schematic diagram of a quantum wire blocking method in another embodiment;

FIG. 8 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 9 is a schematic diagram of a quantum wire blocking method in another embodiment;

FIG. 10 is a schematic diagram of the line partitioning of a quantum line blocking method in one embodiment;

FIG. 11 is a schematic diagram of the line division of a quantum line blocking method in another embodiment;

FIG. 12 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 13 is a schematic flow chart of a quantum wire blocking method in another embodiment;

FIG. 14 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 15 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 16 is a sub-line optimization diagram of a quantum line tiling method in one embodiment;

FIG. 17 is a schematic diagram of a quantum wire blocking method according to another embodiment;

FIG. 18 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 19 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 20 is a flow chart of a quantum wire blocking method in another embodiment;

FIG. 21 is a block diagram of the construction of a quantum wire blocking device in one embodiment;

FIG. 22 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The quantum wire blocking method provided by the embodiment of the application can be applied to the application environment shown in fig. 1. Wherein the quantum computer 102 communicates with the server 104 over a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104, or may be located on the cloud or other network server. The quantum computer 102 includes a quantum transistor, a quantum memory, a quantum well laser, a quantum interference element sensor, a quantum effect device, a qubit quantum computer, and the like, and the server 104 may be implemented by an independent server or a server cluster composed of a plurality of servers.

The data storage system stores a target logic quantum circuit, acquires a quantum processor topological structure diagram from a quantum computer 102, sends the target logic quantum circuit and the quantum processor topological structure diagram to a server 104, converts the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure diagram in the server 104 according to the quantum processor topological structure diagram, and divides the physical quantum circuit into a plurality of sub-circuit block sets according to a plurality of preset bit group sets.

Quantum computers are a class of devices that perform high-speed computation by processing quantum information data using the fundamental laws of quantum mechanics. The systems for realizing quantum computers include superconducting qubits, ion traps, semiconductor quantum dots, nuclear magnetic resonance systems, quantum optical systems, and the like. Regardless of the computing system, the quantum compiling technology cannot be used for operating the quantum program. Quantum compilation is just a technique that transforms any pristine quantum wire into a quantum wire that can be executed on a quantum computer. Quantum compilation can be said to be a bridge connecting quantum programs and quantum computer hardware.

With the development of superconducting quantum computers, namely sycamore, optical quantum computing prototypes, namely nine chapters, and superconducting quantum computers, namely ancestor rush, the number of quantum bits will gradually increase, and a better quantum compiler is needed to optimize large-scale quantum circuits.

In real quantum processors, the fidelity of multi-bit gates is lower than that of single-bit gates, so one of the main goals of quantum compilation optimization is to reduce the number of multi-bit gates in the quantum wires. In a general case, if a quantum wire contains more controllable not gates (CNOT), then the optimization may reduce more CNOT gates; if a quantum wire contains fewer CNOT gates, it is already difficult to optimize it further. Therefore, in the first step of QGo compiler, using the brute force search method, each time a sub-line block containing the most CNOT gates is divided from the large-scale quantum lines, and then the gates contained in the sub-line block are removed from the original quantum lines; and then, by using a force search method, a sub-circuit block containing the most CNOT gates is divided from the rest quantum circuits until the original large-scale quantum circuits are divided. The quantum line division method using the brute force search is relatively inefficient, the time consumed by the line division increases in power as the quantum line scale increases, and the QGo algorithm quantum line division time complexity is O (n)^kg) In that respect From a practical point of view, it is unacceptable to wait a long time if one wants to optimize a quantum wire.

Moreover, the sub-line blocks partitioned by the QGo compiler all have the same number of bits, which makes the QGo compiler inflexible and has many invalid partitions. If the number of CNOTs contained in a sub-line block is small, it is difficult to optimize it further, and therefore the division of these sub-line blocks containing a small number of CNOTs is inefficient, requiring the division of these CNOT gates into sub-lines with a larger number of bits.

Based on this, embodiments of the present application provide a quantum line chunking compiling method, apparatus, device, storage medium, and product, which can reduce time consumed by quantum line chunking, and improve efficiency of quantum line partitioning, thereby improving a speed of quantum compiling.

The following describes in detail the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems by embodiments and with reference to the drawings. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments.

In one embodiment, as shown in FIG. 2, a quantum line blocking method is provided, which includes the steps of:

and S201, converting the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart.

Quantum Processors (QPUs) are composed of qubits, the number of qubits in a Quantum processor is not limited, as shown in fig. 3, and fig. 3 is a topological structure diagram of a Quantum processor with 5 qubits.

A logical quantum wire is a quantum wire composed of basic gates executable in a quantum computer, but not necessarily a topological structure diagram that satisfies a sufficient number of sub-processors; the target logical quantum wire is a logical quantum wire corresponding to a problem to be handled in the quantum processor.

Logical quantum wires include a plurality of logical bits, but the logical bits are dummy bits on the logical quantum wires, and therefore, it is necessary to convert the logical quantum wires into physical quantum wires that can be directly run on a quantum processor, and to convert the logical bits into real physical bits in the quantum processor.

Alternatively, in practical applications, the number of bits of the quantum processor should be equal to or greater than the number of bits of the logical quantum wire. Taking the bit number of the quantum processor as 5 as an example, the number of logical bits on the target logical quantum wire should be no more than 5, and may be 5, 4, and so on.

In one embodiment, the target logical quantum wire may be converted into a physical quantum wire matching the quantum processor topology structure map by calling an open source library, a Qiskit and t | key > library, etc. according to the quantum processor topology structure map to directly convert the target logical quantum wire into a physical quantum wire matching the quantum processor topology structure map.

And S202, dividing the physical quantum wires into a plurality of sub-wire block sets according to a plurality of preset bit group sets.

The bit group sets are obtained by grouping physical bits in a physical quantum circuit according to a quantum processor topological structure chart; the runtime used to divide a physical quantum wire into a plurality of sub-wire block sets is linear with the number of bits of the physical bits in the physical quantum wire.

With continued reference to fig. 3, if there are 5 physical bits in the physical quantum wires, the physical bits of the physical quantum wires are grouped according to the topology of the quantum processor to obtain a plurality of bit group sets, and when grouping, the 3 physical bits may be grouped into one group, or 4 physical bits may be grouped into one group, taking 3 physical bits and 4 physical bits as an example, and the plurality of bit group sets are represented by GQ.

In one embodiment, the manner of determining the plurality of bit group sets may be determined according to a grouping algorithm, and the quantum processor topology, the physical bits of the physical quantum wires, and the number of groups are used as inputs of the grouping algorithm, and the plurality of bit group sets are obtained by running the algorithm.

Optionally, each bit group set is connected on the quantum processor topology structure diagram, and in a specific application, the number of bits in the bit group set is not limited, and may be set according to an actual situation.

In one embodiment, the way of dividing the physical quantum wires into a plurality of sub-wire block sets may be by a dynamic blocking method, and sub-wire blocks obtained by the dynamic blocking method are basically all valid; the sub-circuit block with large bit number can reduce more quantum gates, but the circuit optimization also consumes more time; on the contrary, a sub-pipeline block with a small number of bits consumes less time, but has fewer reduced quantum gates, so that the time consumption and the quantum gate reduction can be balanced by using a dynamic blocking method.

In another embodiment, the method for dividing the physical quantum wire into the plurality of sub-wire block sets may also be that a plurality of bit group sets and the physical quantum wire are used as inputs of a preset division algorithm through the preset division algorithm, and the plurality of sub-wire blocks are determined by running the division algorithm.

In another embodiment, the method of dividing the physical quantum circuit into a plurality of sub-circuit block sets may also be obtained by using a preset neural network model, and the plurality of bit group sets and the physical quantum circuit are used as inputs of the preset neural network model, and the plurality of sub-circuit blocks are finally output by training the neural network model.

An example, assume a physical quantum wire C_pThe total number of bits is n, the total number of quantum gates in the physical quantum line is g, the number of CNOT gates is c, and the search depth is D_maxThe bit number of the sub-line block is k, and n > k is generally the case; the search starts with the CNOT gate of the first layer of the physical quantum wire and the single bit gate is removed, since the CNOT gate is a two bit gate, thus considering the worst case, the first layer contains n/2 number of CNOT gates. Since the CNOT gate couples two bits, the branching factor is 2 in the embodiment, and in the worst case, a search is needed

The stripe path can find the largest sub-line block. In addition, because a loop is needed to obtain a sub-line block, and in the worst case, each CNOT gate is individually blocked, so that a loop step c is needed, the time complexity of the embodiment is a linear function of the number n of line bits, and the time complexity used by the quantum line dividing module is as follows:

in the quantum circuit blocking method, a target logic quantum circuit is converted into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart, the physical quantum circuit is divided into a plurality of sub-circuit block sets according to a plurality of preset bit group sets, and the plurality of bit group sets are obtained by grouping physical bits in the physical quantum circuit according to the quantum processor topological structure chart. In the method, firstly, a target logic quantum circuit is converted into a physical quantum circuit according to a topological structure diagram of a quantum processor, then the physical quantum circuit is divided into a plurality of sub-circuit block sets, the time for dividing the physical quantum circuit into the plurality of sub-circuit block sets is in a linear relation with the number of bits in the physical quantum circuit, and the time for dividing the quantum circuit in the prior art is in a power relation with the number of bits of the quantum circuit, so the method in the application reduces the time consumed by quantum circuit block division, and particularly when the number of bits of the physical quantum circuit is large, the time efficiency improved by the method in the embodiment of the application is very obvious, so the method can reduce the time consumed by sub-circuit block division, improve the efficiency of quantum circuit division, and further improve the speed of quantum compiling.

In one embodiment, as shown in fig. 4, the target logic quantum wire includes a single-bit gate and a controllable not gate, the single-bit gate is a gate formed by one bit, and the controllable not gate is a gate formed by two bits; converting the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart, and the method comprises the following steps:

s401, mapping the logic bits in the target logic quantum circuit into physical bits according to the quantum processor topological structure diagram, and exchanging the sequence of the physical bits in the target logic quantum circuit by adding a quantum exchange gate to obtain an exchanged controllable NOT gate, wherein the exchanged controllable NOT gate can be executed on the quantum processor.

In logic quantum circuitsAs shown in fig. 5, fig. 5 is a 5-bit target logic quantum circuit, where the target logic quantum circuit includes a single-bit gate and a two-bit gate, and optionally, for convenience of description, the two-bit gate in this application is illustrated as a Controllable Not (CNOT) gate, and other two-bit gates are also included in this application. G in FIG. 5₁-g₁₅Are all single bit gates, the rest are two bit gates, v₀-v₄Is a logical bit in the target logical quantum wire.

As shown in fig. 6, a mapping relationship between quantum switching gates (SWAP gates) and controllable not gates is shown in fig. 6, and one SWAP gate may be represented by three CNOT gates.

In one embodiment, the manner of converting the logical bits in the target logical quantum wires into the physical bits is to invoke a preset conversion algorithm according to the quantum processor topology structure diagram by using a preset conversion algorithm to convert the logical bits into the physical bits.

After the logical bits in the target logical quantum wire are converted into physical bits, the non-executable controlled not gates are converted into controllable not gates executable on the quantum processor by adding appropriate quantum switching gates. Then, according to the equivalence relation between the SWAP gate and the controllable not gate in fig. 6, the added 1 quantum switching gate can be converted into 3 controllable not gates, and then a physical quantum line is obtained.

And S402, generating a physical quantum line according to the physical bit, the switched controllable NOT gate and the switched single-bit gate.

In one embodiment, the physical quantum circuit may be generated by generating a physical quantum circuit through a preset neural network model, taking the quantum processor topology structure diagram and the target logical quantum circuit as inputs of the neural network model, and training the neural network model to obtain the physical quantum circuit.

FIG. 7 shows a generated physical quantum wire, FIG. 7 including 5 physical bits q₀-q₄With continuing reference to fig. 5 and 3, when the target logical quantum wire of fig. 5 is converted into the physical quantum wire of fig. 7, because v exists in fig. 5₀And v₂Controllable not gate of, however v₀And v₂Does not satisfy the quantum processor topology of fig. 3, and therefore, a quantum switching gate, such as the first quantum switching gate in fig. 7, needs to be added to couple v to v₂And v₃Is adjusted to obtain q in FIG. 7₂And q is₃V originally present in FIG. 5 after addition of a quantum exchange gate₀And v₃The controllable NOT gate becomes v₀And v₂Therefore, it is necessary to add a quantum switching gate, such as the second quantum switching gate in fig. 7.

Optionally, the physical quantum wire is a physical quantum wire conforming to a quantum processor topology.

In the quantum circuit blocking method, according to a quantum processor topological structure diagram, logical bits in a target logical quantum circuit are mapped into physical bits, the sequence of the physical bits in the target logical quantum circuit is exchanged by adding a quantum exchange gate to obtain an exchanged controllable not gate, the exchanged controllable not gate can be executed on the quantum processor, and the physical quantum circuit is generated according to the physical bits, the exchanged controllable not gate and a single bit gate. The method can reduce time consumed by sub-line partitioning and improve efficiency of quantum line partitioning, thereby improving speed of quantum compiling

In one embodiment, as shown in fig. 8, dividing the physical quantum wire into a plurality of sets of sub-wire blocks according to a preset plurality of sets of bit groups includes the following steps:

s801, layering a first candidate physical quantum line to obtain a plurality of line layers; the first candidate physical quantum wire is a physical quantum wire with the single-bit gate removed.

Since the single-bit gate is not coupled to other bits and therefore does not affect the blocking of the line, the single-bit gate in the physical quantum line can be removed to obtain a first candidate physical quantum line.

Optionally, the first candidate physical quantum line from which the single-bit gate is removed is layered, and the layered processing may be performed by layering the first candidate physical quantum line through a brute force method, or layering the first candidate physical quantum line through an existing open source library Qiskit and t | key > library, and the like, where the layering process further includes a scheduling process.

As shown in fig. 9, fig. 9 shows a plurality of line layers obtained by layering first candidate physical quantum lines, where the first candidate quantum lines are divided into 10 layers, and l represents the number of layers of the lines; it should be noted that, the specific division of the first candidate physical quantum wire into several layers is not limited, and the first candidate physical quantum wire is layered according to specific practical situations.

It should be noted that, when being executed, the multiple line layers of the quantum lines need to be executed layer by layer, that is, only in the case that the quantum gates of the previous layer are executed, the quantum gates of the next layer can be executed next, and the quantum gates of the same layer can be executed simultaneously.

All controllable NOT gates in multiple line layers of a quantum line are denoted as

Where l represents the l-th layer of the quantum wire, 'ij' represents the quantum bit of CNOT gate effect as q_iAnd q is_jThus, each CNOT gate in multiple line layers will be uniquely labeled.

S802, according to a plurality of preset bit group sets, performing line blocking step layer by layer on each line layer in the first candidate physical quantum line to obtain a plurality of controllable NOT sub-line block sets.

The line blocking step is a line blocking step set according to the bit group set and the characteristics of each line layer of the physical quantum line, and a controllable not gate sub-line block set composed of a plurality of controllable not gates can be obtained by performing the line blocking step for each line layer in the first candidate physical quantum line.

Optionally, the minimum number of controllable NOT gates in each sub-line block set is preset, and the minimum number of controllable NOT gates in each sub-line block set is set

And ensuring the effectiveness of each sub-line after being blocked.

There is also an embodiment in which a plurality of controllable NOT-gate sub-line blocks E_nAdded to the set of sub-line blocks B and corresponding groups of bits

Is added to the set M.

And S803, adding a single bit gate into the corresponding controllable NOT gate sub-line block set according to the execution sequence to obtain a plurality of sub-line block sets.

In the above embodiment, the sub-line block set obtained after the first candidate physical quantum line passes through the line blocking step is obtained, and then the previously removed single bit gates are added to the corresponding controllable not gate sub-line block set according to the execution sequence.

In one embodiment, the manner of adding the single bit gate to the corresponding controlled not gate sub-line block set may be that, through a preset addition algorithm, the execution order of the single bit gates in the physical quantum line and the corresponding single bit gate are used as the input of the preset addition algorithm, and by calling the addition algorithm, the plurality of sub-line sets are obtained.

As shown in FIG. 10, FIG. 10 shows the set of controlled not sub-line blocks obtained in the above embodiment, which results in 4 controlled not sub-line blocks, each E₁({q₂，q₃，q₄})、E₂({q₀，q₁，q₂})、E₃({q₀，q₁，q₃})、E₄({q₀，q₂，q₃，q₄Fig. 11 is a plurality of sub-line block sets obtained by adding a single-bit gate to the controllable not gate sub-line set in fig. 10. Wherein the plurality of sets of sub-lines B and the corresponding set of bit groups M may be represented as:

wherein, the elements in B and M correspond one to one.

In the quantum circuit blocking method, a first candidate physical quantum circuit is layered to obtain a plurality of circuit layers, a plurality of controllable NOT gate sub-circuit block sets are obtained by executing circuit blocking steps on each circuit layer in the first candidate physical quantum circuit layer by layer according to a plurality of preset bit group sets, and a single bit gate is added to the corresponding controllable NOT gate sub-circuit block sets according to an execution sequence to obtain a plurality of sub-circuit block sets. In the algorithm, a plurality of controllable NOT gate sub-line block sets are obtained by carrying out layering processing on a first candidate physical quantum line and carrying out a line blocking step layer by layer on a plurality of obtained line layers, and the removed single bit gate is added into the corresponding controllable NOT gate sub-line block set to obtain a plurality of sub-line block sets.

In one embodiment, as shown in fig. 12, the line blocking step includes the steps of:

s1201, searching an initial sub-line block combined by controllable NOT gates in a first layer of a plurality of line layers according to a plurality of preset bit group sets.

Wherein each initial sub-line block comprises at least one controllable NOT gate.

In one embodiment, the manner of determining the initial sub-line block may be directly obtained by using a search algorithm, and the initial sub-line block is obtained by searching one by one using the first layer lines of the plurality of bit group sets and the first candidate physical quantum lines as inputs of the search algorithm.

In another embodiment, the manner of determining the initial sub-line block may be obtained by using a preset neural network model, using the plurality of bit group sets and a plurality of line layers in the first candidate physical quantum line as inputs of the neural network model, and obtaining the initial sub-line block corresponding to the controllable not gate of the first layer in the plurality of line layers by training the neural network model, where the initial sub-line block includes at least one controllable not gate, and the initial sub-line block includes at least one controllable not gate.

Finding the first layer from the set of bit groups GQ

Executable initial sub-line block E composed of gates_nEach sub-line block E_nComprising one or more CNOT gates, the number of CNOT gates and the bit group

The number of bits k involved is related. Let the integer part of k/2 be k₂Then E is_nContaining 1 to k₂A CNOT gate; with continued reference to FIG. 9, the controllable NOT gate in the first level of FIG. 9 includes q₀-q₁Controllable NOT gate and q₃-q₄A controllable NOT gate, which is based on a plurality of preset bit group sets, taking the number of bits in a bit group as 3 as an example, and an initial sub-line block as

And

and S1202, acquiring candidate sub-line blocks according to the number of the controllable NOT gates in the initial sub-line block and the second line layer.

Optionally, according to the initial sub-line block obtained from the first layer in the above embodiment, the controllable not gate corresponding to the initial sub-line block is continuously searched in the second line layer, with reference to fig. 9, in the second line layer of fig. 9, a q is included₂-q₃Controllable NOT gate, known from the initial sub-line block, q₂-q₃Controllable NOT gate corresponding initial sub-circuit block

Thus, the initial sub-line block

Is a candidate sub-line block.

In one embodiment, the candidate sub-line block may be determined by using a preset neural network model, using the plurality of bit group sets and the candidate physical quantum lines as inputs of the neural network model, and training the neural network model to obtain the candidate sub-line block.

S1203, acquiring a sub-line block set according to the number of the candidate sub-line blocks.

According to the above embodiment, the number of candidate sub-line blocks includes at least one, but may be 2 or more, and therefore, the sub-line block set may be determined according to the number of candidate sub-line blocks.

In one embodiment, if the candidate sub-line block is equal to 1, starting from the second line layer, adding the controllable not gates matched with the candidate sub-line block in the line layer after the second line layer into the candidate sub-line block until there are no controllable not gates matched with the candidate sub-line block, and if the number of controllable not gates in the candidate sub-line block is greater than or equal to a preset number, taking the candidate sub-line block as the sub-line block set.

If the number of the candidate sub-line blocks is equal to 1, continuously searching a controllable NOT gate which can be matched with the bit group set corresponding to the candidate sub-line block from the second line layer, if the controllable NOT gate which can be matched with the bit group set corresponding to the candidate sub-line block can be found in the second line layer, adding the controllable NOT gate into the candidate sub-line block, and updating

And continuously searching the controllable NOT gates matched with the bit group set corresponding to the candidate sub-line block layer by layer until the controllable NOT gates matched with the bit group set corresponding to the candidate sub-line block do not exist in a certain searched line layer, and stopping searching.

For example, with continued reference to FIG. 9, the candidate sub-line block in FIG. 9 is determined as

Corresponding set of bit groups as

Then q in the second line level₂-q₃The controllable NOT gate matches the set of bit groups corresponding to the candidate sub-line block, thus matching q in the second line layer₂-q₃Adding the controlled not gate to the candidate sub-line block, and continuing to compare whether the controlled not gate in the third circuit layer matches with the bit group set corresponding to the candidate sub-line block, as can be seen from fig. 9, the controlled not gate in the third circuit layer is q₂-q₃Controllable NOT gates are added into the candidate sub-line block, and whether the controllable NOT gates in the fourth line layer are matched with the bit group set corresponding to the candidate sub-line block or not is continuously compared, wherein the controllable NOT gates in the fourth line layer are q₂-q₃A controllable not gate.

Therefore, the controlled not gate in the fourth line layer is added to the candidate sub-line block, and then whether the controlled not gate in the fifth line layer matches with the set of bit groups corresponding to the candidate sub-line block is compared, and as can be seen from fig. 9, the controlled not gate in the fifth line layer does not match with the set of bit groups corresponding to the candidate sub-line block, and therefore, the search for the controlled not gate matching with the candidate sub-line block is stopped.

After the controllable NOT gates matched with the candidate sub-line blocks are stopped being searched, the number of the controllable NOT gates in the candidate sub-line blocks is calculated, and if the number of the controllable NOT gates in the candidate sub-line blocks is larger than or equal to the preset number, the candidate sub-line blocks are used as a sub-line block set; the preset number refers to the minimum number of controllable not gates in the preset sub-line block, and the effectiveness of the divided sub-line block can be guaranteed by setting the minimum number of controllable not gates in the sub-line block.

In another embodiment, if the candidate sub-line block is greater than 1 and the number of current layers is less than the preset maximum search depth, adding a controllable not gate matched with the candidate sub-line block in the second line layer into the candidate sub-line block, acquiring a new candidate sub-line block according to the candidate sub-line block and the number of controllable not gates in the candidate sub-line block after considering the next layer of the second line layer, and re-executing the step of acquiring the sub-line block set according to the number of candidate sub-line blocks on the new candidate sub-line block; wherein the maximum search depth represents the maximum number of search layers of the sub-line block.

If the number of the candidate sub-line blocks is more than 1, judging whether the current layer is less than the preset maximum search depth, if the current layer is less than the preset maximum search depth, adding a controllable NOT gate matched with a bit group set corresponding to the candidate sub-line block in the second line layer into the corresponding candidate sub-line block, at the moment, updating the candidate sub-line block,

i.e. in the next layer

Door joining of corresponding E_nThen, a new candidate sub-line block is obtained based on the updated candidate sub-line block and the number of candidate sub-line blocks after the controllable not gate in the next layer of the second line layer is considered, and then the step of obtaining the sub-line block set based on the number of candidate sub-line blocks is re-executed for the new candidate sub-line block.

In another embodiment, if the candidate sub-line block is greater than 1 and the current layer number is greater than or equal to the preset maximum search depth, determining a target candidate sub-line block from the plurality of candidate sub-line blocks through a preset random algorithm, and adding a controllable not gate matched with the target candidate sub-line block in the line layer after the current layer number into the target candidate sub-line block until no controllable not gate matched with the target candidate sub-line block exists; and if the number of the controllable NOT gates in the target candidate sub-line block is greater than or equal to the preset number, determining the target candidate sub-line block as a sub-line block set.

At this time, the target candidate sub-lineThe number of controllable NOT gates in the block is greater than or equal to the preset number, and the target candidate sub-line block E is represented_nAre valid partitions.

If the number of the candidate sub-line blocks is larger than 1 and the current layer number is larger than or equal to the preset maximum search depth, one candidate sub-line block is selected from the candidate sub-line blocks through a random algorithm, and the selected candidate sub-line block is used as a target candidate sub-line block.

And then, continuously searching a controllable NOT gate matched with the corresponding bit group set in the target candidate sub-line block from the next layer of the current layer number, and adding the controllable NOT gate matched with the corresponding bit group set in the target candidate sub-line block into the target candidate sub-line block until no controllable NOT gate matched with the target candidate sub-line block exists in the next layer of the current layer number.

Finally, whether the number of controllable NOT gates in the target candidate sub-line block is larger than or equal to a preset number or not is judged, and if the number of controllable NOT gates in the target candidate sub-line block is larger than or equal to the preset number, the target candidate sub-line block is determined to be a sub-line block set; the preset number is the minimum number of controllable NOT gates in the sub-line blocks, and the effectiveness of the divided sub-line blocks is guaranteed.

S1204, remove controllable NOT gate in the sub-line block set in the first candidate physical quantum line, get the second candidate physical quantum line, and to the second candidate physical quantum line, carry out the line blocking step, until there is no controllable NOT gate in the new candidate physical quantum line, confirm all sub-line block sets got as a plurality of controllable NOT gate sub-line block sets.

The sub-line block in the above-described embodiment is obtained, and then the controllable not gate in the sub-line block included in the first candidate physical quantum line is driven from the first candidate physical quantum line

Removing and updating

Carrying out layering processing on the removed first candidate physical quantum wires to obtain second candidate physical quantum wires; and then, executing a line blocking step on the second candidate physical quantum line until no controllable NOT exists in the new candidate physical quantum line, and finally determining all the obtained sub-line block sets as a plurality of controllable NOT sub-line block sets.

If no controllable NOT gate exists in the new candidate physical quantum wire, the quantum wire block is completed.

In the quantum line blocking method, an initial sub-line block combined by controllable NOT gates in a first layer in a plurality of line layers is searched according to a preset plurality of bit group sets; each initial sub-line block comprises at least one controllable NOT gate, and candidate sub-line blocks are obtained according to the number of the controllable NOT gates in the initial sub-line blocks and the number of the controllable NOT gates in the second line layer; acquiring a sub-line block set according to the number of the candidate sub-line blocks; and removing the controllable NOT gates in the sub-line block sets in the first candidate physical quantum line to obtain a second candidate physical quantum line, executing a line blocking step on the second candidate physical quantum line until no controllable NOT gate exists in the new candidate physical quantum line, and determining all the obtained sub-line block sets as a plurality of controllable NOT gate sub-line block sets. The method can reduce the time consumed by sub-line partitioning and improve the efficiency of quantum line partitioning, thereby improving the speed of quantum compiling.

In one embodiment, as shown in fig. 13, before removing the controllable not gates in the sub-line block set in the first candidate physical quantum line, there is also a case that the number of controllable not gates in the sub-line block set is less than a preset number, and the current layer is less than the total number of layers of the first candidate physical quantum line, which includes the following steps:

and S1301, if the number of the controllable NOT gates in the sub-line block set is smaller than the preset number and the current layer is smaller than the total number of the first candidate physical quantum lines, performing incremental processing on the number of the bit groups in the bit group sets to obtain a plurality of new bit group sets.

If the number of controllable not gates in the sub-line block set is smaller than the preset number and the current layer is smaller than the total number of layers of the first candidate physical quantum line, performing incremental processing on the number of bits in the plurality of bit group sets, for example, if the number of bits in the plurality of bit group sets is originally 3, increasing the number of bits included in the bit group, setting the number of bits in the bit group set to 4, that is, k ← k +1, and then obtaining a plurality of new bit group sets corresponding to the number of bits of 4.

Alternatively, the preset number is the minimum number of controllable not gates in the preset sub-circuit block, and the total number of layers is the total number of layers of the quantum circuits, as shown in fig. 9, and the total number of layers of the quantum circuits in fig. 9 is 10.

And S1302, according to the new bit group sets, executing a step of obtaining a plurality of controllable NOT sub-line block sets by executing a line blocking step layer by layer for each line layer in the first candidate physical quantum line.

And according to the obtained new bit group sets, continuously executing the step of executing line blocking step layer by layer on each line layer in the first candidate physical quantum line to obtain a plurality of controllable NOT sub-line block sets.

In the quantum circuit blocking method, if the number of controllable not gates in the sub-circuit block set is less than the preset number and the current layer is less than the total number of the first candidate physical quantum circuits, the number of bit groups in the plurality of bit group sets is subjected to incremental processing to obtain a plurality of new bit group sets; and according to the new bit group sets, executing a step of obtaining a plurality of controllable NOT sub-line block sets by executing a line blocking step layer by layer on each line layer in the first candidate physical quantum line. The method ensures the effectiveness of dividing the sub-line block set by setting the minimum number of the controllable NOT gates in the sub-line block, and further can reduce more quantum gate numbers in the subsequent line optimization, thereby improving the fidelity of the quantum line when running on a quantum computer.

In one embodiment, as shown in fig. 14, obtaining the candidate sub-line block according to the number of controllable not gates in the initial sub-line block and the second line layer includes the following steps:

s1401, calculating a cost function according to the number of controllable NOT gates in the initial sub-line block; and calculating a heuristic function according to the number of controllable NOT gates matched with the initial sub-circuit blocks in the second circuit layer.

The cost function is the number of controllable NOT gates already contained in the initial sub-line block, and the heuristic function is the number of controllable NOT gates which can be added to the initial sub-line by the next line layer of the current layer number.

In one embodiment, the number of controllable NOT gates in the initial sub-line block is the value of the cost function, and the number of controllable NOT gates in the second line layer that match the initial sub-line block is the value of the heuristic function.

S1402, generating a cost estimation function according to the cost function and the heuristic function; the cost estimation function represents the number of controllable NOT gates included in the initial sub-line block estimated according to the number of controllable NOT gates in the second line layer.

Alternatively, the cost estimation function represents the estimated number of controllable not gates of the initial sub-line block under the consideration of the number of controllable not gates of the next layer line which can be added into the initial sub-line block, and the cost function and the heuristic function obtained according to the above embodiment generate the cost estimation function if the cost function is g (E)_n) The heuristic function is h (E)_n) Then the cost estimation function can be expressed as f (E)_n)＝g(E_n)+h(E_n)，f(E_n) Largest sub-line block E_nThere may be more than one.

For example, if the number of controllable not gates in the initial sub-line block is 2, i.e. the cost function is 2, and the number of controllable not gates that can be added to the initial sub-line block in the next line layer of the current layer number of the initial sub-line block is 1, i.e. the heuristic function is 1, then the cost estimation function is 3.

And S1403, determining the sub-line block corresponding to the maximum cost estimation function value as a candidate sub-line block.

And if two initial sub-line blocks exist, determining the initial sub-line block with the maximum value as a candidate sub-line block after calculating the cost estimation function of the two initial sub-line blocks.

Alternatively, the number of the initial sub-line blocks is not limited and may be 1 or more.

In the quantum line blocking method, a cost function is calculated according to the number of controllable NOT gates in the initial sub-line block, a heuristic function is calculated according to the number of controllable NOT gates matched with the initial sub-line block in the second line layer, a cost estimation function is generated according to the cost function and the heuristic function, the cost estimation function represents the number of controllable NOT gates included in the initial sub-line block estimated according to the number of controllable NOT gates in the second line layer, and the corresponding sub-line block when the cost estimation function value is maximum is determined as a candidate sub-line block. The method can reduce the time consumed by sub-line partitioning and improve the efficiency of quantum line partitioning, thereby improving the speed of quantum compiling.

In one embodiment, as shown in fig. 15, this embodiment includes the steps of:

s1501, optimizing each sub-line block in the plurality of sub-line block sets in a parallel mode through a preset quantum line synthesis algorithm of quantum topology perception to obtain the plurality of optimized sub-line block sets.

One embodiment, for each sub-line block E in the plurality of sub-line block sets B_nAnd optimizing each sub-line block in a parallel mode by adopting a preset quantum line synthesis algorithm of quantum topology perception to obtain an optimized sub-line block E ', and obtaining a plurality of optimized sub-line block sets B' after the parallel operation is finished.

In another embodiment, for each sub-line block E in the plurality of sub-line block sets B_nThe optimization can be carried out, and other algorithms or existing open source libraries can be accessed according to specific situations, such as KAK algorithm, Qiskit and t | key>Libraries, etc.

In yet another embodiment, for each sub-line block E in the plurality of sub-line block sets B_nThe optimization can be obtained by adopting a neural network model. Training a neural network by using the quantum circuit and the corresponding optimized quantum circuit as inputs to obtain a trained nerveNetwork model, and sub-line block E in parallel_nInputting the data into a trained neural network to obtain an optimized sub-line block E ', and obtaining a plurality of optimized sub-line block sets B' after parallel operation is finished.

It can be stated that, in practical application, if the sub-line block E 'is optimized'_nThe number of the included controllable NOT gates is more than or equal to the original sub-circuit block E_nThe number of the controllable NOT gates in the sub-circuit block E is still used_nI.e. E' ← E_n。

One embodiment optimizes multiple sub-line sets in FIG. 11, with a single bit quantum gate g in a sub-line set₁-g₁₅And can be a Hadamard gate, Rx, Rz gate, etc.; e₁，E₄CNOT gate in (1) is not decremented, thus E'₁＝E₁，E′₄＝E₄(ii) a And E₂，E₃Optimized, corresponding optimized sub-line block E 'is obtained'₂，E′₃FIG. 16 is a view showing a sub-line block E in FIG. 16₂，E₃Optimized sub-line block E'₂，E′₃(ii) a U in optimized sub-line block₃The door is a universal single-bit revolving door with three Euler angles and is shown as

Wherein, theta, phi and lambda are parameters.

And S1502, integrating the sub-line blocks in the optimized sub-line block sets according to the bit group sets corresponding to the sub-line block sets to obtain the optimized quantum line of the target logic quantum line.

As shown in fig. 17, fig. 17 is an optimized quantum wire of the target logical quantum wire, and with continued reference to fig. 16, arbitrary U's in the optimized sub-wire block₃The gate multiplication can still be expressed as U₃The gates, only the parameters theta, phi, lambda will change, thus combining the multiplied U in the optimized quantum wire of the target logical quantum wire₃And a door.

In the quantum circuit blocking method, each sub-circuit block in a plurality of sub-circuit block sets is optimized in a parallel mode through a preset quantum circuit synthesis algorithm of quantum topology perception, and the optimized sub-circuit block sets are obtained; and integrating the sub-line blocks in the optimized sub-line block sets according to the bit group sets corresponding to the sub-line block sets to obtain the optimized quantum line of the target logic quantum line. According to the method, the quantum circuit is divided into blocks to obtain a plurality of sub-circuit blocks, and a parallel processing mode is considered for each sub-circuit block, so that when the sub-circuit blocks are optimized, only a certain sub-circuit which consumes the longest time is considered, and the method is irrelevant to the original large-scale quantum circuit, and therefore the method can efficiently process the large-scale quantum circuit.

In one embodiment, the large-scale line is divided into sub-line blocks with a small number of bits, so that the sub-line block optimization part can access other optimization algorithms and open source libraries, such as KAK algorithm, Qiskit and t | key > open source libraries, and the like. And for the physical bit mapping module, an appropriate quantum circuit mapping algorithm can be accessed. Therefore, the compiling framework of the invention has good compatibility and expandability.

In one embodiment, as shown in fig. 18, fig. 18 is an overall flowchart of a quantum wire block compiling method, specifically, first, according to a logical quantum wire G and a quantum processor topological structure diagram G of an original problem, then a physical bit mapping module is combined with the quantum processor topological structure diagram G, logical bits are mapped to physical bits, and the logical quantum wire C is mapped by adding a SWAP gate_lPhysical quantum wire C transformed to conform to quantum processor topology_p(ii) a The quantum bit grouping module groups physical bits into a series of bit group sets according to the quantum processor topological structure chart G

Then the quantum line dividing module divides the physical quantum line C according to the bit group set GQ_pDivided into a series of sets of sub-line blocksCombination of Chinese herbs

And corresponding set of bit groups

Each sub-line block

Containing k physical bits and in corresponding bit groups

The lower sub-line block is executable on the quantum processor, for convenience, the following

Abbreviated as E_n。

Then, the sub-line set B ═ { E ] obtained by the quantum line division module_nAnd the sub-line block parallel distribution module calculates resources for each sub-line block according to the number of bits in the sub-line block>Number of CNOT gates>The number of single bit gates is distributed, and the larger the sub-circuit scale is, the more computing resources are distributed, including a CPU or a GPU; the sub-circuit optimizing module obtains a sub-circuit block E_nOptimizing to obtain an optimized sub-line block E'_nPrepared from E'_nAdding to an optimized sub-line block set B'; the sub-line block integration module integrates the optimized sub-line block sets B ' into a complete line C ' according to the bit group set M '_pOutput optimization line C'_p。

In one embodiment, as shown in fig. 19, fig. 19 is a flow chart of a physical quantum wire being divided into a plurality of sub-wire block sets in a quantum wire blocking method; specifically, first, a physical quantum wire C is input_pAnd a set of bit groups GQ, C_pRemoving single-bit gate to obtain the circuit only containing CNOT gate

Initializing a memory sub-lineRoad block E_nAnd storing corresponding bit groups

A set M of (A); then to

Performing line blocking to obtain sub-line block set, and sequentially adding the removed single-bit gates to corresponding sub-line blocks E according to the sequence of the gates_nIn, i.e. E_n←E_nAnd + single bit gate, outputting the final sub-line block set B and bit group set M.

The circuit blocking step is as follows: initializing parameters: the number of bit groups k is initialized to ensure that the minimum number of valid CNOT gates for a sub-line block is

Maximum search depth of D_maxLine of

The total layer number L and the initial layer number L; then, the first layer is found out according to the bit group set GQ

All executable sub-lines E of the gate composition_n(ii) a Judging whether l is larger than D_max。

If l is not greater than D_maxCalculating a cost function g (E)_n) Heuristic function h (E)_n) Cost estimation function f (E)_n)＝g(E_n)+h(E_n) Find out so that f (E)_n) Largest sub-line block E_nThen f (E) is judged_n) Largest sub-line block E_nIf there is only one, if there is more than one, adding the CNOT gate of the next layer into the corresponding sub-line block E_nI.e. updating the largest sub-line block

Then increasing layer number l ← l +1, and continuously judging whether l is in existenceGreater than D_max。

If l is greater than D_maxAfter randomly selecting a sub-line block, or, f (E)_n) Largest sub-line block E_nOnly one, then find the line after l layers, will add to E_nTo which the CNOT gates are added in sequence, i.e.

Then judging the sub-line block E_nIn (1)

Or l>If the condition is not satisfied, then the number k ← k +1 of bit groups is used, and then the step of finding out the first layer from the set GQ of bit groups is performed

All executable sub-lines E of the gate composition_nA step (2); if the condition is satisfied, E_nAdded to set B, i.e., B.apppend (E)_n) Will correspond to

Adding M, i.e.

Sub-line block E_nDoor from

Removing and updating

Namely, it is

Updating

Including after being updated

Layering again; judgment of

And whether the number of the middle CNOT gates is 0 or not, and if not, continuing to execute the line blocking step.

If it is not

The number of middle CNOT gates is 0, and then the previously removed single-bit gates are sequentially added to the corresponding sub-line block E in the order in which the gates are executed_nIn, i.e. E_n←E_nAnd + single bit gate, outputting the final sub-line block set B and bit group set M.

In one embodiment, as shown in fig. 20, the first signal is represented by k-3, L-10,

D_maxas an example, this embodiment includes the following steps:

s2001, mapping the logical bits to physical bits according to the logical quantum wire and quantum processor topology of the original problem, and converting the logical quantum wire into a physical quantum wire by adding SWAP gates.

S2002, grouping the physical bits in the physical quantum wires according to the quantum processor topology, to obtain a bit group set.

S2003, removing single bit gates from the physical quantum wires, and layering the physical quantum wires having only two bit gates.

S2004, parameterizing and setting the number of the initialization bit groups k and the minimum number of effective CNOT gates of the sub-circuit blocks to be

Maximum search depth of D_maxThe total number of layers L of the physical quantum circuit, wherein the initial number of layers L is 1;

s2005, according to the bit group set, all executable sub-line blocks composed by the first layer CNOT gate are found out.

S2006, if l<＝D_maxCalculating a cost estimation function to obtain the number of CNOT gates which the sub-line block can predict to contain under the condition of considering the next layer of line, if only one maximum sub-line block exists, executing S2007, and if not, updating the maximum sub-line block, increasing the layer number, and executing S2006 again.

S2007, finding the line behind the layer l, and adding the CNOT gates which can be added to the sub-line block into the sub-line block in sequence.

S2008, judging in the sub-line block

Or l>Executing S2009 as L; otherwise, let k be k +1, S2005 is executed.

And S2009, adding the sub-line block into the storage set, adding the bit group corresponding to the sub-line block into the set of storage bit groups, then removing the CNOT gate in the sub-line from the physical quantum line, and re-layering the physical quantum line from which the sub-line is removed.

S2010, if the CNOT gate in the physical quantum line is 0, adding the single bit gates removed from the original physical line into the corresponding sub-line blocks in sequence according to the sequence of executed gates, and outputting a final sub-line set and a bit group set; otherwise, S2004 is executed.

S2011, optimizing the sub-line blocks in a parallel mode to obtain the optimized sub-line blocks, if the optimized sub-line blocks are E'_nIf the number of CNOT gates included is greater than or equal to the number of CNOT gates in the original sub-line block, the original sub-line block is still used.

And S2012, merging the optimized sub-line blocks into a complete line according to the bit group set, namely the final optimized line of the original logic quantum line.

In an embodiment, please continue to refer to fig. 1, convert the original problem into a target logical quantum line and store the target logical quantum line in the data storage system, obtain a quantum processor topological structure diagram from the quantum computer 102, send the target logical quantum line and the quantum processor topological structure diagram to the server 104, convert the target logical quantum line into a physical quantum line matched with the quantum processor topological structure diagram in the server 104 according to the quantum processor topological structure diagram, divide the physical quantum line into a plurality of sub-line block sets according to a plurality of preset bit group sets, then obtain a final compiled and optimized physical quantum line through the parallel distribution module, the sub-line optimization module, and the sub-line integration module, and send the optimized physical quantum line to the quantum computer 102 for calculation.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

The embodiment of the present application further provides a quantum circuit partitioning system, which includes a physical bit mapping module, a quantum bit grouping module, a quantum circuit partitioning module, a sub-circuit block parallel distribution module, a sub-circuit optimization module, and a sub-circuit block integration module, wherein:

and the physical bit mapping module is used for converting the target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart.

And the quantum bit grouping module is used for grouping the physical bits in the physical quantum circuit into a plurality of bit group sets according to the quantum processor topological structure diagram.

And the quantum line dividing module is used for dividing the physical quantum line into a plurality of sub-line block sets according to a plurality of preset bit group sets.

And the sub-line block parallel distribution module is used for distributing computing resources (CPU/GPU core number) according to the bit number and the bit gate number of the sub-line blocks in the plurality of sub-line block sets.

The computing resources are distributed according to the bit number > CNOT gate number > single bit gate number in the sub-line block, that is, the more the bit number of the sub-line block is, the more the computing resources are distributed, when the bit number is the same, the more the CNOT gate number in the sub-line block is, the more the computing resources are distributed, and when the CNOT gate number is also the same, the more the computing resources are distributed.

And the sub-line optimization module is used for optimizing each sub-line block in the plurality of sub-line block sets in a parallel mode through a preset quantum line synthesis algorithm of quantum topology perception to obtain a plurality of optimized sub-line block sets.

And the sub-line block integration module is used for integrating the sub-line blocks in the optimized sub-line block sets according to the bit group sets corresponding to the sub-line block sets to obtain the optimized quantum line of the target logic quantum line.

The various modules in the quantum wire block system described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

Based on the same inventive concept, the embodiments of the present application also provide a quantum wire blocking apparatus for implementing the quantum wire blocking method mentioned above. The solution of the problem provided by the device is similar to the solution described in the above method, so the specific limitations in one or more embodiments of the quantum wire blocking device provided below can be referred to the limitations of the quantum wire blocking method in the above, and are not described herein again.

In one embodiment, as shown in fig. 21, there is provided a quantum line blocking apparatus 2100 comprising a conversion module 2101 and a dividing module 2102, wherein:

the conversion module 2101 is used for converting the target logical quantum line into a physical quantum line matched with the quantum processor topological structure diagram according to the quantum processor topological structure diagram;

a dividing module 2102 configured to divide the physical quantum wire into a plurality of sub-wire block sets according to a preset plurality of bit group sets; the bit group sets are obtained by grouping the physical bits in the physical quantum circuit according to the topological structure chart of the quantum processor; wherein a running time for dividing the physical quantum wire into the plurality of sub-wire block sets is linearly related to the number of bits of the physical bits in the physical quantum wire.

In one embodiment, the conversion module 2101 includes:

the mapping unit is used for mapping the logic bits in the target logic quantum circuit into physical bits according to the quantum processor topological structure diagram, and exchanging the sequence of the physical bits in the target logic quantum circuit by adding a quantum exchange gate to obtain an exchanged controllable NOT gate, wherein the exchanged controllable NOT gate can be executed on the quantum processor;

and the generation unit is used for generating the physical quantum circuit according to the physical bit, the exchanged controllable NOT gate and the single bit gate.

In one embodiment, the partitioning module 2102 comprises:

the layering unit is used for layering the first candidate physical quantum circuit to obtain a plurality of circuit layers; the first candidate physical quantum wire is the physical quantum wire without the single-bit gate;

the blocking unit is used for executing a line blocking step on each line layer in the first candidate physical quantum line layer by layer according to a plurality of preset bit group sets to obtain a plurality of controllable NOT sub-line block sets;

and the adding unit is used for adding a single bit gate into the corresponding controllable NOT gate sub-line block set according to the execution sequence to obtain a plurality of sub-line block sets.

In one embodiment, the blocking unit includes:

the searching subunit is used for searching an initial sub-line block combined by controllable NOT gates in a first layer of a plurality of line layers according to a plurality of preset bit group sets; each initial sub-circuit block comprises at least one controllable NOT gate;

the first acquisition subunit is used for acquiring candidate sub-line blocks according to the number of the controllable NOT gates in the initial sub-line block and the second line layer;

a second obtaining subunit, configured to obtain a sub-line block set according to the number of candidate sub-line blocks;

and the first determining subunit is used for removing the controllable NOT gates in the sub-line block set in the first candidate physical quantum line to obtain a second candidate physical quantum line, executing a line blocking step on the second candidate physical quantum line until no controllable NOT gate exists in the new candidate physical quantum line, and determining all the obtained sub-line block sets as a plurality of controllable NOT gate sub-line block sets.

In one embodiment, the apparatus 2100 further comprises:

the incremental module is used for performing incremental processing on the number of bit groups in the plurality of bit group sets to obtain a plurality of new bit group sets if the number of controllable NOT gates in the sub-line block set is smaller than the preset number and the current layer is smaller than the total number of the first candidate physical quantum lines;

and the execution module is used for executing a line blocking step on each line layer in the first candidate physical quantum line layer by layer according to the plurality of new bit group sets to obtain a plurality of controllable NOT sub-line block sets.

In one embodiment, the second acquisition subunit includes:

the first judgment subunit is configured to, if the candidate sub-line block is equal to 1, add, from the second line layer, a controllable not gate, which is matched with the candidate sub-line block, in the line layer subsequent to the second line layer into the candidate sub-line block until there is no controllable not gate matched with the candidate sub-line block;

and the second judgment subunit is used for taking the candidate sub-line block as the sub-line block set if the number of the controllable not gates in the candidate sub-line block is greater than or equal to the preset number.

In one embodiment, the second acquisition subunit includes:

and the third judging subunit is configured to, if the candidate sub-line block is greater than 1 and the current layer number is smaller than the preset maximum search depth, add the controlled not gate, which is matched with the candidate sub-line block, in the second line layer to the candidate sub-line block, acquire a new candidate sub-line block according to the candidate sub-line block and the number of controlled not gates in the candidate sub-line block after considering a next layer of the second line layer, and re-execute the step of acquiring the sub-line block set according to the number of candidate sub-line blocks on the new candidate sub-line block.

In one embodiment, the second acquisition subunit includes:

the fourth judging subunit is configured to determine, through a preset random algorithm, a target candidate sub-line block from the plurality of candidate sub-line blocks if the candidate sub-line block is greater than 1 and the current layer number is greater than or equal to a preset maximum search depth;

the adding subunit is used for adding the controllable NOT gate matched with the target candidate sub-line block in the line layer after the current layer number into the target candidate sub-line block until no controllable NOT gate matched with the target candidate sub-line block exists;

and the fifth judging subunit is used for determining the target candidate sub-line block as the sub-line block set if the number of the controllable not gates in the target candidate sub-line block is greater than or equal to the preset number.

In one embodiment, the first acquisition subunit includes:

the calculating subunit is used for calculating a cost function according to the number of the controllable NOT gates in the initial sub-line block; calculating a heuristic function according to the number of controllable NOT gates matched with the initial sub-line blocks in the second line layer;

the generating subunit is used for generating a cost estimation function according to the cost function and the heuristic function; the cost estimation function represents the number of controllable NOT gates included in the initial sub-line block estimated according to the number of controllable NOT gates in the second line layer;

and the second determining subunit is used for determining the sub-circuit block corresponding to the maximum cost estimation function value as the candidate sub-circuit block.

In one embodiment, the apparatus 2100 further comprises: the optimization module is used for optimizing each sub-line block in the plurality of sub-line block sets in a parallel mode through a preset quantum line synthesis algorithm of quantum topology perception to obtain a plurality of optimized sub-line block sets;

and the integration module is used for integrating the sub-line blocks in the optimized sub-line block sets according to the bit group sets corresponding to the sub-line block sets to obtain the optimized quantum line of the target logic quantum line.

The respective modules in the quantum wire block apparatus described above may be implemented in whole or in part by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 22. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used to store sub-line block data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a quantum circuit partitioning method.

Those skilled in the art will appreciate that the architecture shown in fig. 22 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

The implementation principle and technical effect of each step implemented by the processor in this embodiment are similar to those of the above quantum wire blocking method, and are not described herein again.

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In the embodiments, the implementation principle and technical effect of each step implemented when the computer program is executed by the processor are similar to those of the above quantum circuit blocking method, and are not described herein again.

In an embodiment, a computer program product is provided, comprising a computer program which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

It should be noted that, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A quantum line blocking method, the method comprising:

converting a target logic quantum circuit into a physical quantum circuit matched with the quantum processor topological structure chart according to the quantum processor topological structure chart;

dividing the physical quantum circuit into a plurality of sub-circuit block sets according to a plurality of preset bit group sets; the bit group sets are obtained by grouping the physical bits in the physical quantum circuit according to the topological structure diagram of the quantum processor;

wherein a running time for dividing the physical quantum wire into a plurality of sub-wire block sets is linear with a number of bits in the physical quantum wire.

2. The method of claim 1, wherein the target logic quantum wire comprises a single-bit gate and a controllable not gate, the single-bit gate is a gate formed by one bit, and the controllable not gate is a gate formed by two bits;

the method for converting the target logic quantum circuit into the physical quantum circuit matched with the quantum processor topological structure diagram according to the quantum processor topological structure diagram comprises the following steps:

mapping the logic bits in the target logic quantum circuit into physical bits according to the quantum processor topological structure diagram, and exchanging the sequence of the physical bits in the target logic quantum circuit by adding a quantum exchange gate to obtain an exchanged controllable not gate, wherein the exchanged controllable not gate can be executed on a quantum processor;

and generating the physical quantum circuit according to the physical bit, the switched controllable NOT gate and the single-bit gate.

3. The method of claim 2, wherein the dividing the physical quantum wires into a plurality of sub-wire block sets according to a preset plurality of bit group sets comprises:

carrying out layering processing on the first candidate physical quantum circuit to obtain a plurality of circuit layers; the first candidate physical quantum wire is a physical quantum wire with a single-bit gate removed;

according to the preset bit group sets, performing line blocking step on each line layer in the first candidate physical quantum line layer by layer to obtain a plurality of controllable NOT gate line block sets;

and adding the single-bit gate into the corresponding controllable NOT gate sub-line block set according to the execution sequence to obtain the plurality of sub-line block sets.

4. The method of claim 3, wherein the line blocking step comprises:

searching an initial sub-line block combined by controllable NOT gates in a first layer of the plurality of line layers according to the preset plurality of bit group sets; each initial sub-circuit block comprises at least one controllable NOT gate;

and removing the controllable NOT gates in the sub-line block sets in the first candidate physical quantum line to obtain a second candidate physical quantum line, executing the line blocking step on the second candidate physical quantum line until no controllable NOT gate exists in the new candidate physical quantum line, and determining all the obtained sub-line block sets as the plurality of controllable NOT gate sub-line block sets.

5. The method of claim 4, wherein prior to said removing controllable NOT gates in the set of sub-line blocks in the first candidate physical quantum line, the method further comprises:

and according to the new bit group sets, executing a step of obtaining a plurality of controllable not gate sub-line block sets by executing a line blocking step layer by layer on each line layer in the first candidate physical quantum line.

6. The method according to claim 4 or 5, wherein the obtaining a sub-line block set according to the number of candidate sub-line blocks comprises:

and if the number of the controllable NOT gates in the candidate sub-line block is greater than or equal to the preset number, taking the candidate sub-line block as the sub-line block set.

7. The method according to claim 4 or 5, wherein the obtaining a sub-line block set according to the number of candidate sub-line blocks comprises:

if the candidate sub-line block is larger than 1 and the current layer number is smaller than the preset maximum search depth, adding a controllable NOT (not gate) matched with the candidate sub-line block in the second line layer into the candidate sub-line block, acquiring a new candidate sub-line block according to the candidate sub-line block and the number of controllable NOT (not gates) in the candidate sub-line block after the next layer of the second line layer is considered, and re-executing the step of acquiring a sub-line block set for the new candidate sub-line block according to the number of the candidate sub-line block.

8. The method according to claim 4 or 5, wherein the obtaining a sub-line block set according to the number of candidate sub-line blocks comprises:

and if the number of the controllable NOT gates in the target candidate sub-line block is greater than or equal to the preset number, determining the target candidate sub-line block as the sub-line block set.

9. The method of claim 4 or 5, wherein the obtaining candidate sub-line blocks according to the number of controllable NOT gates in the initial sub-line block and the second line layer comprises:

and determining the sub-line block corresponding to the maximum cost estimation function value as the candidate sub-line block.

10. The method according to any one of claims 1 to 4, further comprising:

11. A quantum line partitioning apparatus, comprising:

the dividing module is used for dividing the physical quantum circuit into a plurality of sub-circuit block sets according to a plurality of preset bit group sets; the bit group sets are obtained by grouping the physical bits in the physical quantum circuit according to the topological structure diagram of the quantum processor; wherein a running time for dividing the physical quantum wire into a plurality of sub-wire block sets is linearly related to a number of bits of physical bits in the physical quantum wire.

12. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method of any one of claims 1 to 10 when executing the computer program.

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 10.

14. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 10 when executed by a processor.