CN114330228B - High-voltage transistor simulation model and modeling method - Google Patents
High-voltage transistor simulation model and modeling method Download PDFInfo
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Abstract
The invention provides a high-voltage transistor simulation model and a modeling method. The simulation model and the modeling method are based on a BSIM simulation model, a variable resistor is connected in series at the drain end of a high-voltage transistor, and the resistance value of the variable resistor is in direct proportion to a polynomial function of the gate-source voltage and the drain-source voltage of the high-voltage transistor under a certain temperature condition. The relation of the variable resistor is extracted through test data of the high-voltage transistor and called by an SPICE tool, an optimized BSIM simulation model can be obtained, and experimental data show that the problem of non-convergence existing in the simulation only by adopting a general BSIM simulation model can be solved by using the optimized BSIM simulation model to simulate the characteristic curve of the high-voltage transistor, so that the efficiency and the accuracy of the design of a high-voltage device can be improved, the design period of a product can be shortened, and the cost can be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-voltage transistor simulation model and a modeling method of the high-voltage transistor simulation model.
Background
The device simulation model plays an important role in semiconductor circuit design, and the design and production period of a product can be shortened by using the device simulation model, so that the yield of the product is improved, and the cost is saved. In addition, high voltage transistors are widely used in wireless communication, switching applications (e.g., printers, audio equipment, etc.), automation applications, and the like due to their voltage withstanding characteristics. However, the accuracy of current high voltage transistor models is not high. The main reason is that the I-V (current-voltage) curve of the high voltage transistor is complex, and Quasi-saturation effect (Quasi-saturation effect) exists when conventional BSIM (BSIM 3V3 and BSIM 4) simulation (for example) which is widely used in common transistors is adopted, as shown in fig. 1. In order to accurately model a high-voltage transistor, the prior art adopts a method of combining a JFET model and a BSIM model, a method of adding a current model and a voltage model, and the like. However, these models require the addition of discontinuous current and/or voltage sources when simulating the design of the guest circuit, and have the problem of non-convergence.
Therefore, there is still a need for a compact simulation model of high voltage transistors that can improve the non-convergence problem for semiconductor circuit designs including high voltage transistors.
Disclosure of Invention
In order to solve the problem of the existing high-voltage transistor simulation model, the invention provides a modeling method of the high-voltage transistor simulation model and the high-voltage transistor simulation model.
In one aspect, the present invention provides a modeling method for a high-voltage transistor simulation model, where the modeling method includes:
on the basis of a BSIM simulation model, a variable resistor is connected in series with the drain end of a high-voltage transistor, and the resistance value of the variable resistor and the gate-source voltage of the high-voltage transistor are connected under a certain temperature conditionVgsAnd drain-source voltageVdsPolynomial function off（Vgs，Vds) Proportional, said polynomial functionf（Vgs，Vds) The following relation is satisfied:
f（Vgs，Vds）=p0 + pg1*Vgs + pg2*Vgs 2 + pg3*Vgs 3 +pd1*Vds
+pd2*Vds
2
+pd3*Vds
3
+pdg11*Vds*Vgs+pdg12*Vds*Vgs
2
+pdg22*Vds 2 *Vgs 2 +pdg21*Vds 2 *Vgs，
wherein the content of the first and second substances,p0、pg1、pg2、pg3、pd1、pd2、pd3、pdg11、pdg12、pdg22andpdg21to testAnd (4) parameters.
Optionally, under the condition that the channel length of the high-voltage transistor is not changed, the resistance value of the variable resistor and the channel width of the high-voltage transistorWTemperature ofTAnd the polynomial functionf（Vgs，Vds) The relationship between them is:
Optionally, in the modeling method, at least two channel size ranges are set according to different values of the channel width of the high-voltage transistor, and the polynomial function is applied to each channel size rangef（Vgs，Vds) With a corresponding set of said test parameters.
Optionally, at least two channel size ranges are set according to different values of channel width and different values of channel length, and the polynomial function is applied to each channel size rangef（Vgs，Vds) With a corresponding set of said test parameters.
Optionally, the modeling method further includes:
and calling the variable resistor by using an SPICE tool to obtain an optimized BSIM simulation model.
In one aspect, the invention provides a high-voltage transistor simulation model, which is based on a BSIM simulation model, and is characterized in that a variable resistor is connected in series with the drain end of a high-voltage transistor, and the resistance value of the variable resistor and the gate-source voltage of the high-voltage transistorVgsAnd drain-source voltageVdsPolynomial function off（Vgs，Vds) Proportional, said polynomial functionf（Vgs，Vds) Satisfies the following relation:
f（Vgs，Vds）=p0 + pg1*Vgs + pg2*Vgs 2 + pg3*Vgs 3 +pd1*Vds
+pd2*Vds
2
+pd3*Vds
3
+pdg11*Vds*Vgs+pdg12*Vds*Vgs
2
+pdg22*Vds 2 *Vgs 2 +pdg21*Vds 2 *Vgs，
wherein the content of the first and second substances,p0、pg1、pg2、pg3、pd1、pd2、pd3、pdg11、pdg12、pdg22andpdg21are the test parameters.
Optionally, under the condition that the channel length of the high-voltage transistor is not changed, the resistance value of the variable resistor and the channel width of the high-voltage transistorWTemperature ofTAnd the polynomial functionf（Vgs，Vds) The relation of (A) is as follows:
Optionally, the high-voltage transistor simulation model is provided with at least two channel size ranges according to the variation of the channel width of the high-voltage transistor to be simulated, and for each channel size range, the polynomial functionf（Vgs，Vds) Each having a corresponding set of said test parameters.
Optionally, the high-voltage transistor simulation model is provided with at least two channel size ranges according to the variation of the channel width and the channel length of the high-voltage transistor to be simulated, and for each channel size range, the polynomial functionf（Vgs，Vds) Each having a corresponding set of said test parameters.
The modeling method provided by the invention can obtain the relational expression of the variable resistor on the basis of the test data of the high-voltage transistor, and can be called by an SPICE tool to obtain an optimized BSIM simulation model.
Compared with a general BSIM model, the high-voltage transistor simulation model provided by the invention can solve the problem of non-convergence, is beneficial to improving the efficiency and accuracy of high-voltage device design, shortens the product design period and reduces the cost.
Drawings
FIG. 1 is a diagram of a high voltage transistor using only the common BSIM modelVds-IdsAnd (5) simulation results of the characteristic curve.
Fig. 2 is a schematic circuit diagram of a high-voltage transistor used in the modeling method of the high-voltage transistor simulation model according to the embodiment of the invention.
FIG. 3 is a diagram of a high-voltage transistor using a modeling method of a high-voltage transistor simulation model according to an embodiment of the present inventionVgs-IdAnd (5) characteristic simulation results.
FIG. 4 shows a high-voltage transistor using a modeling method of a high-voltage transistor simulation model according to an embodiment of the present inventionVds-IdsAnd (5) characteristic simulation results.
FIG. 5 is based on drain-source voltageVdsScanning range and drain-source current ofIdsThe simulation range in fig. 4 is divided into four quadrants as schematically shown.
Detailed Description
The simulation model and modeling method of the high-voltage transistor of the present invention are further described in detail with reference to the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, but merely as a convenient and clear aid in describing embodiments of the invention, which should not be construed as limited to the specific shapes of regions illustrated in the drawings.
Fig. 2 is a schematic circuit diagram of a high-voltage transistor used in the modeling method of the high-voltage transistor simulation model according to the embodiment of the present invention. Referring to fig. 2, the modeling method of the high-voltage transistor simulation model according to the embodiment of the present invention is performed based on a well-known and general BSIM simulation model, for example, a BSIM3V3 model or a BSIM4 model. Specifically, the modeling method is based on BSIM simulation model, and a variable resistor is connected in series with the drain end of the high-voltage transistor (so as toRdexRepresentation). The high-voltage transistor is, for example, an N-type LDMOSFET (i.e., a lateral diffusion MOSFET), or may be another high-voltage transistor, such as an N-type HDMOSFET (i.e., a longitudinal diffusion MOSFET) or a P-type high-voltage transistor, in some embodiments, a withstand voltage of the high-voltage transistor is, for example, in a range of 400V to 1000V, but is not limited thereto, and in other embodiments, the withstand voltage of the high-voltage transistor may also be less than 400V or greater than 1000V. As shown in FIG. 2, the resistance between the drain node D ʹ and the Source node S ʹ of the high voltage transistor is denoted as the internal resistance Rdin, the Source node S ʹ is connected to the Source terminal (Source), the Gate node G ʹ is connected to the Gate terminal (Gate), the drain node D ʹ and the variable resistorRdexIs connected to one end of a variable resistorRdexThe other terminal of which is connected to the Drain terminal (Drain). It can be seen that, compared with the circuit of BSIM model, the high-voltage transistor circuit adopted in the embodiment of the invention only adds the variable resistorRdexThe circuit is simpler. As shown in FIG. 2, this embodiment will include a variable resistorRdexThe high-voltage transistor circuit is marked as a Macro sub-circuit (Macro-circuit), and the Macro sub-circuit is used as a simulation circuit in the modeling method of the high-voltage transistor simulation model of the embodiment of the invention.
Research shows that if the characteristics of the high-voltage MOSFET are simulated only by adopting the BSIM model, the problems of divergence (divergence) and non-convergence (non-convergence) are easy to occur due to the Quasi-saturation effect. Specifically, when the high-voltage transistor is simulated only by adopting the BSIM4 model (as shown by the dashed circle in fig. 2), only the internal resistance Rdin is calculated, which is a function of the channel width W, the gate-source voltage Vgs and the temperature T of the high-voltage transistor, and is denoted as f (W, T, Vgs), and the function f (W, T, Vgs) satisfies the following relational expression:
wherein Rdsw is a drain-source resistance parameter, and Prwg is a resistance correlation coefficient of a gate-source voltage Vgs.
Fig. 1 is a result of a simulation of the Vds-Ids characteristic curve of a high-voltage transistor using only a general BSIM model. Referring to fig. 1, there are problems of deviation and non-convergence between the Vds-Ids characteristic simulation result using only the BSIM model and the actual Vds-Ids characteristic test result of the device. Fig. 4 is a simulation result of Vds-Ids characteristics of a high-voltage transistor to which the modeling method of the embodiment of the present invention is applied. Comparing fig. 1 and fig. 4, it can be seen that, compared with the simulation only using the general BSIM model, after the modeling method of the embodiment of the present invention is used for modeling, the simulation result can better match with the test result, the problems of deviation and non-convergence are improved, and the simulation accuracy is higher, which is helpful for improving the efficiency and accuracy of high-voltage device design, shortening the product design period, and reducing the cost.
The modeling method of the high-voltage transistor simulation model according to the embodiment of the invention is further explained below.
In the modeling method of the high-voltage transistor simulation model according to the embodiment of the invention, under a certain temperature condition (for example, room temperature 25 ℃ or other temperatures), the resistance value of the variable resistor arranged at the drain end and the gate-source voltage of the high-voltage transistorVgsAnd drain-source voltageVdsPolynomial function f (of (1)Vgs，Vds) In direct proportion, the polynomial function f (Vgs，Vds) The following relation is satisfied:
f（Vgs，Vds）=p0 + pg1*Vgs + pg2*Vgs 2 + pg3*Vgs 3 +pd1*Vds+ pd2*Vds 2
+pd3*Vds
3
+pdg11*Vds*Vgs+pdg12*Vds*Vgs
2
+pdg22*Vds 2 *Vgs 2 +pdg21*Vds 2 *Vgs ，
wherein, the first and the second end of the pipe are connected with each other,p0、pg1、pg2、pg3、pd1、pd2、pd3、pdg11、pdg12、pdg22andpdg21the test parameters are specifically test parameters obtained by verifying direct current and voltage parameters of the device, namely DC test parameters.
Further, in the case where the channel length (denoted as L) of the high voltage transistor is constant, the resistance value (denoted as L) of the variable resistor is constantRdex) And the channel width of the transistor (denoted asW) Temperature (shown asT) And the above polynomial functionf（Vgs，Vds) The relationship between them is:
it is found that the channel size (especially the channel width W) has a large influence on the characteristics of the high voltage transistor, and optionally, in the modeling method, at least two channel size ranges are set for different values of the channel width of the high voltage transistor, and modeling is performed for each channel size range, so that the polynomial function is madef（Vgs，Vds) With a corresponding set of said test parameters, test data may be passed in particular for different channel size rangesFitting to obtain a polynomial functionf（Vgs，Vds) The relational expression (c) of (c). In one embodiment, more than two channel width ranges are provided, for example, one embodiment provides the following six ranges: w is not less than 3 mu<4μ，4μ≤W<8μ，8μ≤W<10μ，10μ≤W<20 mu and W ≧ 20 mu, and different polynomial functions are obtained with the six channel width ranges respectivelyf（Vgs，Vds) The test parameters of (1).
Optionally, the modeling method may further obtain a polynomial function based on different value ranges of two parameters, i.e., the channel width W and the channel length Lf（Vgs，Vds) The relational expression (c) of (c). Specifically, two or more channel size ranges may be set according to different values of the channel width W and different values of the channel length L, for example, the channel width W may be set to two or more ranges, and each range of the channel width W may be further divided into a plurality of sub-ranges according to different ranges of the channel length L, each sub-range being used as one channel size range, for example, W is greater than or equal to 3 μ and less than or equal to W<A channel width range of 4 μ, in combination with five ranges for channel length L as follows: l is less than or equal to 3.5 mu<3.7μ，3.7μ≤L<5μ，5μ≤L<8μ，8μ≤L<The size of 10 mu and L is more than or equal to 10 mu, thus obtaining five channel size ranges. For each of the channel size ranges, making the polynomial functionf（Vgs，Vds) With a corresponding set of said test parameters.
To obtain a variable resistorRdexAfter the relational expression (b), the modeling method further comprises: and calling the variable resistor by using an SPICE tool to obtain an optimized BSIM simulation model. In particular, the variable resistor may be usedRdexAnd inserting the optimized BSIM device model into the existing device model file of the SPICE tool. Variable resistorRdexIn addition, the setting of the optimized BSIM device model may adopt the setting disclosed in the art, and is not described herein again.
FIG. 3 shows a high voltage transistor using a modeling method of a high voltage transistor simulation model according to an embodiment of the present inventionVgs-IdAnd (5) characteristic simulation results. FIG. 4 shows a high-voltage transistor using a modeling method of a high-voltage transistor simulation model according to an embodiment of the present inventionVds-IdsAnd (5) characteristic simulation results. Wherein the dotted line is a test curve (Mea.), and the continuous line is a simulation curve (Sim. (Macro sub-circuit)). The three curves in fig. 3 correspond to different temperatures T (temp.), respectively. The four curves in fig. 4 correspond to different gate-source voltages respectivelyVgs. Referring to fig. 3 and 4, the variable resistance can be extracted based on the test data of the high voltage transistor by using the modeling method of the embodiment of the inventionRdexThe optimized BSIM simulation model is obtained by directly calling the SPICE tool, and the characteristics of the device are simulated, so that a simulation result can be obtained. The modeling method of the high-voltage transistor simulation model provided by the embodiment of the invention has the advantages that the accuracy of the simulation result is higher, and the problem of non-convergence existing in the simulation only by using the BSIM simulation model can be solved.
The inventor researches and discovers that the polynomial functionf（Vgs，Vds) Among the various test parameters of (a) to (b),p0can be used as the overall control parameter, and the other test parameters have different functions in different simulation ranges, so the polynomial function of the embodiment of the inventionf（Vgs，Vds) By multiple test parameters to drain-source voltageVdsAnd gate source voltageVgsThe corresponding items are limited, and the accuracy of the simulation model is improved. FIG. 5 is based on drain-source voltageVdsScanning range and drain-source current ofIdsThe simulation range in fig. 4 is divided into four quadrants as schematically shown. As shown in FIG. 5, the X-axis and Y-axis will be the drain-source voltage, as an exampleVdsScanning range and drain-source current ofIdsThe test range of (a) is divided into four quadrants, respectively: quadrant a, quadrant B, quadrant C, and quadrant D. Drain-source voltage corresponding to each quadrantVdsScanning range and/or drain-source current ofIdsThe test range of (c) is different. The research finds that in quadrant A, the drain-source voltageVdsAnd gate source voltageVgsThe values are all larger, pdg22, pd3 and pg3 in the test parameters play a dominant role in simulation, and the gate-source voltage in quadrant B isVgsLarger, pg3 dominates the simulation, while in quadrant D, the drain-source voltageVdsLarger, pd3 dominates the simulation.
The modeling method provided by the invention can obtain the relational expression of the variable resistor on the basis of the measurement data of the high-voltage transistor, and can be called by an SPICE tool (a circuit design simulation software) so as to obtain an optimized BSIM simulation model.
The embodiment of the invention also relates to a high-voltage transistor simulation model which is based on the BSIM simulation model, a variable resistor is connected in series at the drain end of the high-voltage transistor, and the resistance value of the variable resistor and the gate-source voltage of the high-voltage transistorVgsAnd drain-source voltageVdsPolynomial function of (2)f（Vgs，Vds) Proportional, said polynomial functionf（Vgs，Vds) Satisfies the following relation:
f（Vgs，Vds）=p0 + pg1*Vgs + pg2*Vgs 2 + pg3*Vgs 3 +pd1*Vds+ pd2*Vds 2
+pd3*Vds
3
+pdg11*Vds*Vgs+pdg12*Vds*Vgs
2
+pdg22*Vds 2 *Vgs 2 +pdg21*Vds 2 *Vgs ，
wherein the content of the first and second substances,p0、pg1、pg2、pg3、pd1、pd2、pd3、pdg11、pdg12、pdg22andpdg21are the test parameters.
Further, under the condition that the channel length (L) of the high-voltage transistor is not changed, the resistance value of the variable resistor is equal to that of the variable resistorChannel width of the high voltage transistorWTemperature ofTAnd the polynomial functionf（Vgs，Vds) The relation of (A) is as follows:
The high-voltage transistor simulation model can simulate various high-voltage transistors with different channel widths and/or channel lengths. In an alternative embodiment, the high voltage transistor simulation model is provided with at least two channel size ranges according to the variation of the channel width of the high voltage transistor to be simulated, and the polynomial function is used for each channel size rangef（Vgs，Vds) Each having a corresponding set of the test parameters. In yet another alternative embodiment, the high voltage transistor simulation model is provided with at least two channel size ranges according to the variation of the channel width and the channel length of the high voltage transistor to be simulated, and the polynomial function is used for each channel size rangef（Vgs，Vds) Each having a corresponding set of said test parameters.
The high-voltage transistor simulation model can be obtained by adopting the modeling method, belongs to the same inventive concept, so that the description is simpler, and related parts can be understood by reference. Compared with a general BSIM model, the high-voltage transistor simulation model can solve the problem of non-convergence, is simple in simulation circuit, and is beneficial to improving the efficiency and accuracy of high-voltage device design, shortening the product design period and reducing the cost.
The above description is only for the purpose of describing preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art may make possible variations and modifications of the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications of the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims (7)
1. A modeling method of a high-voltage transistor simulation model is characterized by comprising the following steps:
on the basis of a BSIM simulation model, a variable resistor is connected in series with the drain end of a high-voltage transistor, and the resistance value of the variable resistor and the gate-source voltage of the high-voltage transistor are connected under a certain temperature conditionVgsAnd drain-source voltageVdsPolynomial function off（Vgs，Vds) Proportional, said polynomial functionf（Vgs，Vds) Satisfies the following relation:
f（Vgs，Vds）=p0 + pg1*Vgs + pg2*Vgs 2 + pg3*Vgs 3 +pd1*Vds
+pd2*Vds
2
+pd3*Vds
3
+pdg11*Vds*Vgs+pdg12*Vds*Vgs
2
+pdg22*Vds 2 *Vgs 2 +pdg21*Vds 2 *Vgs，
wherein the content of the first and second substances,p0、pg1、pg2、pg3、pd1、pd2、pd3、pdg11、pdg12、pdg22andpdg21is a test parameter;
under the condition that the channel length of the high-voltage transistor is not changed, the resistance value of the variable resistor and the channel width of the high-voltage transistorWTemperature ofTAnd the polynomial functionf（Vgs，Vds) The relationship between them is:
2. The modeling method according to claim 1, wherein at least two channel size ranges are set according to different values of the channel width of the high-voltage transistor, and the polynomial function is made for each of the channel size rangesf（Vgs，Vds) With a corresponding set of said test parameters.
3. The modeling method according to claim 1, wherein in the modeling method, at least two channel size ranges are set according to different values of a channel width and different values of a channel length, and the polynomial function is made for each of the channel size rangesf（Vgs，Vds) With a corresponding set of said test parameters.
4. The modeling method of claim 1, further comprising:
and calling the variable resistor by using an SPICE tool to obtain an optimized BSIM simulation model.
5. The high-voltage transistor simulation model is characterized in that the high-voltage transistor simulation model is based on a BSIM simulation model, a variable resistor is connected in series with the drain end of a high-voltage transistor, and the resistance value of the variable resistor and the gate-source voltage of the high-voltage transistorVgsAnd drain-source voltageVdsPolynomial function off（Vgs，Vds) Proportional, said polynomial functionf（Vgs， Vds) The following relation is satisfied:
f（Vgs，Vds）=p0 + pg1*Vgs + pg2*Vgs 2 + pg3*Vgs 3 +pd1*Vds
+pd2*Vds
2
+pd3*Vds
3
+pdg11*Vds*Vgs+pdg12*Vds*Vgs
2
+pdg22*Vds 2 *Vgs 2 +pdg21*Vds 2 *Vgs，
wherein, the first and the second end of the pipe are connected with each other,p0、pg1、pg2、pg3、pd1、pd2、pd3、pdg11、pdg12、pdg22andpdg21is a test parameter;
under the condition that the channel length of the high-voltage transistor is not changed, the resistance value of the variable resistor and the channel width of the high-voltage transistorWTemperature ofTAnd the polynomial functionf（Vgs，Vds) The relation of (A) is as follows:
6. The high-voltage transistor simulation model of claim 5, wherein the high-voltage transistor simulation model is provided with at least two channel size ranges in accordance with variations in channel width of a high-voltage transistor to be simulated, the polynomial function for each of the channel size rangesf（Vgs，Vds) Each having a corresponding set of said test parameters.
7. The high-voltage transistor simulation model of claim 5, wherein the high-voltage transistor simulation model is based on a channel width and a channel length of a high-voltage transistor to be simulatedVarying, providing at least two channel size ranges, for each of which said polynomial functionf（Vgs，Vds) Each having a corresponding set of said test parameters.
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