CN114328060A - Reusable test case framework, construction method and electronic equipment - Google Patents
Reusable test case framework, construction method and electronic equipment Download PDFInfo
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Abstract
The invention discloses a reusable test case frame, a construction method and electronic equipment, wherein the reusable test case frame is integrated with a test function library, a template function interface layer, a chip type selection table, a test list and an analysis and reuse main program; according to the scheme provided by the embodiment of the invention, the difference between the chip test case and the actual chip can be separated by using the test function library and the template function interface layer, so that the operator characteristics are abandoned when different operators are tested in different chips, the operator characteristics are unified into an abstract test interface, and various different test functions can be matched through the template function interface only by updating the test function library, so that the aim of reusable test is fulfilled; the test list can effectively control a plurality of test functions, so that the chip operator can perform the plurality of test functions in batch, and the test workload of testers is saved; the chip type selection table is used, so that a chip test case set and different chip types can be separated, and test cases can be multiplexed on different chips.
Description
Technical Field
The invention relates to the technical field of reconfigurable chips, in particular to a reusable test case framework, a construction method and electronic equipment.
Background
In the field of general computing acceleration and reconfigurable chips, each chip design has respective basic operators or instructions (such as ADD, SUB, MUL and other instructions) and more complex function functions composed of the basic operators or instructions, such as MFCC, FFT and the like; for a chip, a complex function is required to be used as a test case to test a basic operator, so that verification of the basic operator/instruction by using the test case is a very important link in the chip development process.
At present, because chips are various in types and different in instructions, each chip has an independent test environment for testing the chip, and a test software platform cannot be unified, so that the chip development needs to perform too many repeated test case development works; meanwhile, the input and output of operators/instructions are different, so that the test cases have larger differences and are difficult to unify in an integrated test environment for batch test.
Disclosure of Invention
In order to solve the problems in the prior art, the embodiment of the invention provides a reusable test case framework, a construction method and electronic equipment. The technical scheme is as follows:
the first aspect provides a reusable test case framework, which is integrated with a test function library, a template function interface layer, a chip type selection table, a test list and an analysis and reuse main program; wherein the content of the first and second substances,
the test function library comprises test functions for forming test cases, wherein the test cases are basic operators for testing the chip and cases of the function functions expanded according to the basic operators;
the template function interface layer comprises a test function interface for calling a test function in the test function library;
the chip model selection table is used for receiving the chip model of the chip to be tested;
the test list is used for receiving the characteristic identification of the test case running on the chip to be tested;
the analysis multiplexing main program is used for analyzing the chip model in the chip model selection table to determine a chip to be tested, the feature identification in the analysis test list determines a test case for running on the chip to be tested, a test function for forming the test case running on the chip to be tested is called from the test function library through the template function interface layer, and the test case is formed based on the called test function to realize multiplexing.
Optionally, the test functions in the test function library are classified and stored according to a predetermined classification principle, where the predetermined classification principle is a principle of classifying the test functions with the same feature identifier into one class;
a test function interface in the template function interface layer corresponds to a type of test function in the test function library.
Optionally, the feature identifier includes: function name, number of parameters, whether there is a return value, whether there is input data, whether there is output data, whether input data length is specified, and whether output data length is specified.
In a second aspect, a method for constructing a reusable test case framework is provided, which includes:
counting a basic operator of the chip and a function expanded according to the basic operator, and formulating a test function according to a counting result, wherein the test function is a function for forming a test case, and the test case is a case for testing the basic operator and the function;
the method comprises the steps of defining functions of test functions, dividing the test functions with the same characteristic identification into a class, determining a test function interface corresponding to each class of test functions according to the class uniform abstraction, and creating a template function interface layer based on the test function interfaces;
packing the same type of test functions, and compiling the test functions into a pre-established test function library for classified storage;
creating a chip type selection table, a test list and an analysis multiplexing main program, wherein the chip type selection table is used for receiving the chip type of a chip to be tested; the test list is used for receiving the characteristic identification of the test case running on the chip to be tested; the analysis multiplexing main program is used for analyzing the chip model in the chip model selection table to determine a chip to be tested, the feature identification in the analysis test list determines a test case for running on the chip to be tested, a test function for forming the test case running on the chip to be tested is called from a test function library through a template function interface layer, and the test case is formed based on the called test function to realize multiplexing;
compiling the test function library, the template function interface layer, the chip type selection table, the test list and the analysis and reuse main program to construct a reusable test case frame.
Optionally, the feature identifier includes: function name, number of parameters, whether there is a return value, whether there is input data, whether there is output data, whether input data length is specified, and whether output data length is specified.
In a third aspect, an electronic device is provided, which includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
and a processor, configured to implement the construction method according to the second aspect when executing the program stored in the memory.
According to the scheme provided by the embodiment of the invention, the difference between the chip test case and the actual chip can be separated by using the test function library and the template function interface layer, so that the operator characteristics are abandoned when different operators are tested in different chips, the operator characteristics are unified into an abstract test interface, and various different test functions can be matched through the test function interface only by updating the test function library, so that the aim of reusable test is fulfilled; the test list can effectively control a plurality of test functions, so that the chip operator can perform the plurality of test functions in batch, and the test workload of testers is saved; the chip type selection table is used, so that a chip test case set and different chip types can be separated, and test cases can be multiplexed on different chips.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a reusable test case framework according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a reusable test case framework building method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1, a reusable test case framework provided in the embodiment of the present invention is integrated with a test function library 100, a template function interface layer 110, a chip type selection table 120, a test list 130, and an analysis multiplexing main program 140; wherein the content of the first and second substances,
the test function library 100 contains test functions for forming test cases, wherein the test cases are basic operators for testing chips and cases of function functions expanded according to the basic operators;
the template function interface layer 110 includes a test function interface for calling a test function in the test function library 100;
the chip type selection table 120 is used for receiving the chip type of the chip to be tested;
the test list 130 is used for receiving the feature identifier of the test case running on the chip to be tested;
the analysis multiplexing main program 140 is used for analyzing the chip model in the chip model selection table 120 to determine a chip to be tested, analyzing the feature identifier in the test list 130 to determine a test case for running on the chip to be tested, calling a test function for forming the test case running on the chip to be tested from the test function library 100 through the template function interface layer 110, and forming the test case based on the called test function to realize multiplexing.
In implementation, an operator manual of a general-purpose computing chip can be used for counting basic operators of the chip and function functions expanded according to the basic operators, a test function is formulated based on a statistical result, function definition is performed on the test function after formulation, specifically, function definition is performed on information such as input data, output data, return values, parameter numbers and the like of the test function, and function implementation is performed after definition is completed, including implementation of operation functions such as control over some registers of the chip, calling of operator functions in the chip, starting execution, data transmission and the like.
The test functions in the test function library 100 are classified and stored according to a predetermined classification principle, wherein the predetermined classification principle is a principle of classifying the test functions with the same feature identifier into one class;
a test function interface within the template function interface layer 110 corresponds to a type of test function within the test function library 100.
After the function definition of the test function is completed, analyzing all function definition information to find out that the functions with the same characteristic identification are divided into a class, specifically classifying the functions according to the name of the test function, the number of parameters, whether return values are provided, whether input data are provided, whether output data are provided, whether input data length is specified, whether output data length is specified, whether special parameter transmission and other characteristic identifications are provided, and shielding the details of each test function, such as specific parameter values and the like, by using methods such as macro definition, variable parameters and the like after classification; then, the test function interfaces are abstracted uniformly according to the classes and a template function interface layer 110 is created, so that one test function interface corresponds to one class of test functions in the test function library 100.
When multiplexing the test case, inputting a characteristic identifier in the test list as a test option, for example, inputting a test case name as a test option, setting a parameter and a return value field as test options for analyzing the multiplexing main program and determining which template function interface layer to call through, wherein the test options in the test list can be added and deleted at will, and specifically, a configuration file or a test code file can be used for creating the test list;
the chip model selection table takes the chip model as a test option for selecting different chip tests.
The analysis multiplexing main program can also store case parameters common to the test cases and used for carrying out assignment on the test cases in the multiplexing process; and the special parameters specific to a certain test case can be obtained from the test list and then assigned.
According to the scheme provided by the embodiment of the invention, the difference between the chip test case and the actual chip can be separated by using the test function library and the template function interface layer, so that the operator characteristics are abandoned when different operators are tested in different chips, the operator characteristics are unified to an abstract test interface, and various different test functions can be matched through the test function interface of the template function interface layer only by updating the test function library, so that the aim of reusable test is fulfilled; the test list can effectively control a plurality of test functions, so that the chip operator can perform the plurality of test functions in batch, and the test workload of testers is saved; the chip type selection table is used, so that a chip test case set and different chip types can be separated, and test cases can be multiplexed on different chips.
Referring to fig. 2, a method for constructing a reusable test case framework according to an embodiment of the present invention includes:
s200, counting basic operators of the chip and function functions expanded according to the basic operators, and formulating test functions according to the counting results, wherein the test functions are functions for forming test cases, and the test cases are cases for testing the basic operators and the function functions;
s210, performing function definition on the test functions, dividing the test functions with the same characteristic identification into a class, determining a test function interface corresponding to each class of test functions according to class uniform abstraction, and creating a template function interface layer based on the test function interfaces;
s220, packaging the same type of test functions, and compiling the test functions into a pre-established test function library for classified storage;
s230, creating a chip model selection table, a test list and an analysis multiplexing main program, wherein the chip model selection table is used for receiving the chip model of the chip to be tested; the test list is used for receiving the characteristic identification of the test case running on the chip to be tested; the analysis multiplexing main program is used for analyzing the chip model in the chip model selection table to determine a chip to be tested, the feature identification in the analysis test list determines a test case for running on the chip to be tested, a test function for forming the test case running on the chip to be tested is called from a test function library through a template function interface layer, and the test case is formed based on the called test function to realize multiplexing;
s240, compiling the test function library, the template function interface layer, the chip model selection table, the test list and the analysis multiplexing main program to construct a multiplexing test case frame.
The characteristic identification comprises the following steps: function name, number of parameters, whether there is a return value, whether there is input data, whether there is output data, whether input data length is specified, and whether output data length is specified.
According to the scheme provided by the embodiment of the invention, the difference between the chip test case and the actual chip can be separated by using the test function library and the template function interface layer, so that the operator characteristics are abandoned when different operators are tested in different chips, the operator characteristics are unified to an abstract test interface, and various different test functions can be matched through the test function interface of the template function interface layer only by updating the test function library, so that the aim of reusable test is fulfilled; the test list can effectively control a plurality of test functions, so that the chip operator can perform the plurality of test functions in batch, and the test workload of testers is saved; the chip type selection table is used, so that a chip test case set and different chip types can be separated, and test cases can be multiplexed on different chips.
An embodiment of the present invention further provides an electronic device, as shown in fig. 3, including a processor 001, a communication interface 002, a memory 003 and a communication bus 004, where the processor 001, the communication interface 002 and the memory 003 complete mutual communication through the communication bus 004,
a memory 003 for storing a computer program;
the processor 001, when executing the program stored in the memory 003, implements the method described above, and the method includes:
counting a basic operator of the chip and a function expanded according to the basic operator, and formulating a test function according to a counting result, wherein the test function is a function for forming a test case, and the test case is a case for testing the basic operator and the function;
the method comprises the steps of defining functions of test functions, dividing the test functions with the same characteristic identification into a class, determining a test function interface corresponding to each class of test functions according to the class uniform abstraction, and creating a template function interface layer based on the test function interfaces;
packing the same type of test functions, and compiling the test functions into a pre-established test function library for classified storage;
creating a chip type selection table, a test list and an analysis multiplexing main program, wherein the chip type selection table is used for receiving the chip type of a chip to be tested; the test list is used for receiving the characteristic identification of the test case running on the chip to be tested; the analysis multiplexing main program is used for analyzing the chip model in the chip model selection table to determine a chip to be tested, the feature identification in the analysis test list determines a test case for running on the chip to be tested, a test function for forming the test case running on the chip to be tested is called from a test function library through a template function interface layer, and the test case is formed based on the called test function to realize multiplexing;
compiling the test function library, the template function interface layer, the chip type selection table, the test list and the analysis and reuse main program to construct a reusable test case frame.
According to the scheme provided by the embodiment of the invention, the difference between the chip test case and the actual chip can be separated by using the test function library and the template function interface layer, so that the operator characteristics are abandoned when different operators are tested in different chips, the operator characteristics are unified to an abstract test interface, and various different test functions can be matched through the test function interface of the template function interface layer only by updating the test function library, so that the aim of reusable test is fulfilled; the test list can effectively control a plurality of test functions, so that the chip operator can perform the plurality of test functions in batch, and the test workload of testers is saved; the chip type selection table is used, so that a chip test case set and different chip types can be separated, and test cases can be multiplexed on different chips.
The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the embodiments of the apparatus and the electronic device, since they are substantially similar to the embodiments of the method, the description is simple, and the relevant points can be referred to only in the partial description of the embodiments of the method.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (6)
1. A reusable test case frame is characterized in that a test function library, a template function interface layer, a chip type selection table, a test list and an analysis and reuse main program are integrated; wherein the content of the first and second substances,
the test function library comprises test functions for forming test cases, wherein the test cases are basic operators for testing the chip and cases of the function functions expanded according to the basic operators;
the template function interface layer comprises a test function interface for calling a test function in the test function library;
the chip model selection table is used for receiving the chip model of the chip to be tested;
the test list is used for receiving the characteristic identification of the test case running on the chip to be tested;
the analysis multiplexing main program is used for analyzing the chip model in the chip model selection table to determine a chip to be tested, the feature identification in the analysis test list determines a test case for running on the chip to be tested, a test function for forming the test case running on the chip to be tested is called from the test function library through the template function interface layer, and the test case is formed based on the called test function to realize multiplexing.
2. The reusable test case framework according to claim 1, wherein the test functions in the test function library are classified and stored according to a predetermined classification rule, and the predetermined classification rule is a rule of classifying the test functions with the same feature identifier into one class;
a test function interface in the template function interface layer corresponds to a type of test function in the test function library.
3. The reusable test case framework of claim 2, wherein the characteristic identification comprises: function name, number of parameters, whether there is a return value, whether there is input data, whether there is output data, whether input data length is specified, and whether output data length is specified.
4. A construction method of a reusable test case framework is characterized by comprising the following steps:
counting a basic operator of the chip and a function expanded according to the basic operator, and formulating a test function according to a counting result, wherein the test function is a function for forming a test case, and the test case is a case for testing the basic operator and the function;
the method comprises the steps of defining functions of test functions, dividing the test functions with the same characteristic identification into a class, determining a test function interface corresponding to each class of test functions according to the class uniform abstraction, and creating a template function interface layer based on the test function interfaces;
packing the same type of test functions, and compiling the test functions into a pre-established test function library for classified storage;
creating a chip type selection table, a test list and an analysis multiplexing main program, wherein the chip type selection table is used for receiving the chip type of a chip to be tested; the test list is used for receiving the characteristic identification of the test case running on the chip to be tested; the analysis multiplexing main program is used for analyzing the chip model in the chip model selection table to determine a chip to be tested, the feature identification in the analysis test list determines a test case for running on the chip to be tested, a test function for forming the test case running on the chip to be tested is called from a test function library through a template function interface layer, and the test case is formed based on the called test function to realize multiplexing;
compiling the test function library, the template function interface layer, the chip type selection table, the test list and the analysis and reuse main program to construct a reusable test case frame.
5. The construction method according to claim 4, wherein the feature identification includes: function name, number of parameters, whether there is a return value, whether there is input data, whether there is output data, whether input data length is specified, and whether output data length is specified.
6. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;
a memory for storing a computer program;
a processor for implementing the construction method according to any one of claims 4 to 5 when executing the program stored in the memory.
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