CN114313314A - Satellite in-orbit digital baseband platform - Google Patents
Satellite in-orbit digital baseband platform Download PDFInfo
- Publication number
- CN114313314A CN114313314A CN202111679269.3A CN202111679269A CN114313314A CN 114313314 A CN114313314 A CN 114313314A CN 202111679269 A CN202111679269 A CN 202111679269A CN 114313314 A CN114313314 A CN 114313314A
- Authority
- CN
- China
- Prior art keywords
- control unit
- satellite
- program
- reconstruction
- storage unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012795 verification Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 description 14
- 230000006870 function Effects 0.000 description 10
- 238000013461 design Methods 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000037452 priming Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Landscapes
- Stored Programmes (AREA)
Abstract
The application provides a satellite in orbit digital baseband platform includes: the satellite navigation system comprises a main control unit, a plurality of satellite control units, at least one first nonvolatile storage unit and at least one second nonvolatile storage unit; the first nonvolatile storage unit is used for storing an original program for controlling the operation of the satellite control chip unit; the satellite control unit is used for executing the on-orbit task of the satellite; and the main control unit is used for receiving a reconstruction program for the original program sent by the ground station, writing the reconstruction program into the second nonvolatile storage unit, controlling the satellite control unit to restart, and loading the reconstruction program stored in the second nonvolatile storage unit to control the satellite control unit to work so as to realize the in-orbit reconstruction of the satellite.
Description
Technical Field
The application relates to the technical field of aerospace, in particular to an in-orbit digital baseband platform for a satellite.
Background
With the expansion of the civil aerospace market, the demands of users become various, and the functions that the satellite needs to realize become more and more complex, so that the algorithm of software running on the satellite becomes more and more complex, and the software scale also increases continuously, so that a plurality of Field Programmable Gate Arrays (FPGAs) need to be used for realizing the required functions in a division and cooperation manner.
During the in-orbit operation of the satellite, if the software running on the satellite fails or needs to update new functions in the operation process, the in-orbit reconstruction can be performed on the FPGA chip, so that the repair of the failure and the upgrade of the functions are realized.
However, because the running program of the V7 series FPGA chip is large, when software running on the satellite runs by using multiple FPGA chips, the program of the FPGA chip is fixed, and on-orbit reconstruction cannot be realized.
Disclosure of Invention
The application provides an in-orbit digital baseband platform for a satellite, which is used for solving the problem that in-orbit reconstruction cannot be realized by a plurality of FPGA chips.
In one aspect, the present application provides a satellite in-orbit digital baseband platform, comprising: the satellite navigation system comprises a main control unit, a plurality of satellite control units, at least one first nonvolatile storage unit and at least one second nonvolatile storage unit;
the first nonvolatile storage unit is used for storing an original program for controlling the operation of the satellite control chip;
the satellite control unit is used for executing the on-orbit task of the satellite;
and the main control unit is used for receiving a reconstruction program for the original program sent by the ground station, writing the reconstruction program into the second nonvolatile storage unit, and controlling the satellite control unit to restart and load the reconstruction program stored in the second nonvolatile storage unit.
The satellite in-orbit digital baseband platform comprises a main control unit, a storage unit, a plurality of satellite control units used for executing satellite in-orbit tasks, one or more first non-volatile storage units used for storing original programs for controlling the satellite control units to run and one or more second non-volatile storage units. When the ground station sends the reconstruction program, the main control unit receives the reconstruction program, writes the reconstruction program into the second nonvolatile storage unit, and controls the satellite control unit to restart so as to load the reconstruction program stored in the second nonvolatile storage unit, thereby completing the in-orbit reconstruction of the satellite control unit.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic view of an application scenario of in-orbit satellite reconstruction provided in an embodiment of the present application;
fig. 2 is a first schematic structural diagram of an in-orbit digital baseband platform of a satellite according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a satellite in-orbit digital baseband platform according to an embodiment of the present application;
fig. 4 is a flowchart of a method for implementing in-orbit reconstruction of a satellite in-orbit digital baseband platform according to an embodiment of the present application.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terms referred to in this application are explained first:
field programmable gate array FPGA: the programmable logic device is a novel high-density programmable logic device, has high speed and reliability, and has a logic function which can be defined repeatedly by a user, namely the programmable logic device has the characteristic of being capable of being programmed repeatedly.
Cyclic redundancy check code: the cyclic code is a commonly used check code with error detection and correction capabilities.
Reconfigurable design: the design method refers to a design method for flexibly changing the self system structure by using reusable software and hardware resources according to different application requirements.
In one aspect, a large-scale electronic system is a combination of various logical functional blocks. From the time axis, the various functional modules in the system are not active at any time, but are alternately or cyclically activated or active according to overall requirements external to the system. As the system scale increases, the resource utilization of each functional block circuit decreases. Therefore, the system design needs to fully utilize limited resources to realize larger-scale logic design, and the resource utilization rate is improved. Based on the reconfigurable function of the large-scale programmable device FPGA, the aims of repeatedly utilizing hardware resources, reducing the volume, reducing the power consumption, increasing the flexibility, reducing the complexity of system hardware and the like can be achieved.
With the expansion of the civil aerospace market, the demands of users become various, and the functions of the satellite to be realized become more and more complex, so that the software algorithm running on the satellite becomes more and more complex, the software scale is continuously increased, and sometimes, a plurality of pieces of FPGA need to be used for realizing the required functions in a division and cooperation manner. At present, V7 series FPGA chips are used more, the maximum program capacity of the device is about 20 megabytes, the device cannot be stored through a conventional PROM chip, and only flash type large-capacity memory chips can be selected. And because the FPGA belongs to a single-particle sensitive device, the FPGA is easy to cause abnormal work due to high-energy particle factors in space, and the working reliability of the FPGA needs to be considered in the design of aerospace products to adopt program redundancy design, so that the required resources are multiplied, and the on-orbit reconstruction cannot be realized at present.
The embodiment of the application provides a satellite in-orbit digital baseband platform which comprises a main control unit, one or more satellite control units for controlling the running state of a satellite, a first nonvolatile storage unit for storing original programs of the satellite control units and a second nonvolatile storage unit for storing reconstructed programs. The number of the first nonvolatile storage unit and the second nonvolatile storage unit can be one or more, and the storage space of the first nonvolatile storage unit and the second nonvolatile storage unit can store the original program and the reconstructed program. And the main control unit receives the reconstruction program sent by the ground station, writes the reconstruction program into the second nonvolatile storage unit, controls the satellite control unit to restart and load the reconstruction program, and completes the reconstruction of the satellite control unit.
Fig. 1 is a schematic view of an application scenario of in-orbit satellite reconstruction according to an embodiment of the present application. As shown in fig. 1, when a satellite control unit that controls an operation state of a satellite is reconstructed during an in-orbit operation of the satellite, a ground station may send a reconstruction program to a main control unit in the satellite in a data uploading manner, and the main control unit controls the satellite control unit to load the reconstruction program, thereby implementing in-orbit reconstruction.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 2 is a schematic structural diagram of a first in-orbit digital baseband platform according to an embodiment of the present disclosure, and as shown in fig. 2, the first in-orbit digital baseband platform according to the present disclosure includes: a main control unit 201, a plurality of satellite control units 202, at least one first non-volatile memory unit 203, at least one second non-volatile memory unit 204.
The first nonvolatile storage unit 203 is used to store an original program for controlling the operation of the satellite control unit 202. The satellite control unit 202 is used to perform satellite on-orbit tasks. The main control unit 201 is configured to receive a reconstruction program for an original program sent by the ground station, write the reconstruction program into the second non-volatile storage unit 204, and control the satellite control unit 202 to restart and load the reconstruction program stored in the second non-volatile storage unit 204.
The satellite control unit 202 executes the satellite in-orbit task by loading an original program, and is generally implemented by running a software program on hardware such as an FPGA chip. As the size of software running on a satellite increases, the number of satellite control units 202 may be multiple. And when the software running on the satellite fails or needs to be upgraded in the running process, sending a reconstruction program to the satellite in-orbit digital baseband platform through the ground station. In the satellite on-orbit digital baseband platform provided by the application, the original program is stored through the first nonvolatile storage unit 203, and the reconstruction program transmitted by the ground station is stored through the second nonvolatile storage unit 204.
The reconstruction program may be a program repaired after an error occurs in the original program, or an upgrade program added with new functions compared with the functions of the original program.
First nonvolatile memory cell 203 and second nonvolatile memory cell 204 are each a nonvolatile memory device, such as a Nor Flash (Nor Flash) chip.
The first nonvolatile storage unit 203 stores the original program run by the satellite control unit 202, so as to ensure that when the satellite control unit 202 cannot normally load the reconfiguration program, the satellite control unit 202 can run the original program again to normally work, and the running reliability of the satellite control unit 202 is improved.
The original program of each satellite control unit 202 can be stored in multiple copies in the first nonvolatile storage unit 203, so that when an error occurs in a certain original program and the satellite control unit 202 is abnormal in operation, the satellite control unit 202 can be kept operating normally through the backup program. The storage space of the first nonvolatile storage unit 203 may be divided into a plurality of storage areas according to the size of the original program of the satellite control unit 202.
The second nonvolatile storage unit 204 is used to store a rebuilt program, such as a modified program of an original program or an upgrade program of the original program. Similarly, a plurality of reconstruction programs may be stored for each satellite control unit 202, and different storage areas may be divided in the second nonvolatile storage unit 204 according to the size of the reconstruction program.
The number of the satellite control units 202 is one or more, and accordingly, the storage space required for the original program and the reconstructed program run by the satellite control units 202 is different. Therefore, the number of the first nonvolatile memory unit 203 and the second nonvolatile memory unit 204 may be set to one or more accordingly, and may be increased according to the increase of the number of the satellite control units 202.
The master control unit 201 may control and monitor the state of the satellite control unit 202, the first non-volatile memory unit 203 and the second non-volatile memory unit 204. The main control unit 201 may also be implemented by various types of chips, such as a field programmable gate array FPGA chip. The ground station may send the reconfiguration program to the satellite in-orbit digital baseband platform by way of, for example, data uploading, and the main control unit 201 writes the reconfiguration program into the second nonvolatile storage unit 204.
It should be noted that, since the number of pins of the main control unit 201 connected to the satellite control device 202, the first nonvolatile memory unit 203, and the second nonvolatile memory unit 204 is limited, when the number of the satellite control unit 202, the first nonvolatile memory unit 203, and the second nonvolatile memory unit 204 is increased to a certain extent, the number of the main control unit 201 is also increased accordingly.
In the process of in-orbit operation of the satellite, when the satellite control unit 202 needs to perform reconstruction, the ground station sends a reconstruction program to the main control unit 201, the main control unit 201 stores the reconstruction program into the second nonvolatile storage unit 204, and controls the satellite control unit 202 to restart so that the satellite control unit 202 does not operate the original program any more, but loads the reconstruction program, thereby completing in-orbit reconstruction.
The embodiment of the application provides a satellite in-orbit digital baseband platform which comprises a main control unit, a satellite control unit, a first nonvolatile storage unit for storing an original program operated by the satellite control unit and a second nonvolatile storage unit for storing a reconstruction program. And when the ground station sends the reconstruction program, the main control unit receives the reconstruction program and writes the reconstruction program into the second nonvolatile storage unit. In order to load the reconstruction program, the main control unit controls the satellite control unit to restart and load the reconstruction program, so that the on-orbit reconstruction of the satellite control unit is realized.
Based on the above embodiments, a specific embodiment is provided below to describe the satellite in-orbit digital baseband platform in detail.
Fig. 3 is a schematic structural diagram of a satellite in-orbit digital baseband platform provided in this embodiment, in the satellite in-orbit digital baseband platform provided in this embodiment, a main control unit 201 is a main control FPGA chip, a satellite control unit 202 is a V7FPGA chip, a data loading pin of the main control FPGA chip is shared among a plurality of V7FPGA chips, and the main control FPGA chip loads each V7FPGA chip through a chip select pin.
In the embodiment of the present application, the main control unit 201 is 1 FPGA chip, and the satellite control unit 202 is 5V 7FPGA chips, as shown in fig. 3.
And the main control FPGA chip receives the reconstruction program sent by the ground station and verifies the reconstruction program. If the verification is successful, the rebuild program is written to the second non-volatile memory unit 204. And the main control FPGA chip controls the V7FPGA chip to restart, so that the V7FPGA chip can load a reconstruction program. The master control FPGA chip can also monitor the working state of the V7FPGA chip.
In an implementation scenario, if the verification fails, an indication message for retransmitting the reconfiguration program is sent to the ground station. And after receiving the indication information of the re-sending reconstruction program, the ground station sends the reconstruction program to the main control FPGA chip again.
When reconstructing the V7FPGA chip, all the V7FPGA chips may be reconstructed, or a specific V7FPGA chip may be reconstructed. The main control FPGA chip can select a specific V7FPGA chip to operate through a chip selection pin.
The satellite in-orbit digital baseband platform provided by the embodiment of the application further comprises a first nonvolatile storage unit 203 and a second nonvolatile storage unit 204. As shown in fig. 3, the first nonvolatile memory unit 203 and the second nonvolatile memory unit 204 are nor flash memory chips. In fig. 3, the nor flash memory chip 1 and the nor flash memory chip 2 serve as a first nonvolatile memory unit 203, and the nor flash memory chip 3 and the nor flash memory chip 4 serve as a second nonvolatile memory unit 204.
The master control FPGA chip and the NOR gate flash memory chips 1-4 share a data line, an address line and a control line, and chip selection pins and busy state pins of the master control FPGA chip are respectively connected with IO ports of different master control FPGA chips for distinguishing. The data line connecting the main control FPGA chip and the NOR gate flash memory chips 1-4 is used for transmitting data, namely an original program and a reconstruction program. Because the address line can transmit the address information of the NOR gate flash memory chip, the main control FPGA chip can select a specific NOR gate flash memory chip through the address line. And the control line is used for controlling the NOR gate flash memory chip by the main control FPGA chip.
In order to ensure that the original program can be rerun for normal work when the loading reconstruction program of the V7FPGA chip is abnormal, the original program needs to be stored. The nor gate flash memory chip 1 and the nor gate flash memory chip 2 are used as a first nonvolatile storage unit 203 for storing an original program operated by the V7FPGA chip. In order to improve the running reliability of the V7FPGA chip, the original program can be stored in three parts, and the V7FPGA chip is used for carrying out two-out-of-three judgment during reading and loading, namely when the three original programs are the same, the V7FPGA chip can run any original program. When two original programs in the three original programs are the same, and one original program is different from the other two original programs, the V7FPGA chip operates any original program in the two same original programs.
In an implementation scene, the original program operated by each V7FPGA chip is stored in three parts, and the total number of the original programs operated by 5V 7FPGA chips is 15 parts. According to the size of the original program, the nor flash memory chip 1 and the nor flash memory chip 2 can be equally divided into 9 areas, namely 8 areas with the capacity of 28MB and 1 area with the capacity of 32 MB.
The nor gate flash memory chip 3 and the nor gate flash memory chip 4 are a second nonvolatile storage unit 204, and are used for storing a reconfiguration program of the V7FPGA chip.
In an implementation scenario, the nor flash memory chip 3 and the nor flash memory chip 4 may be divided into 9 regions according to the size of the original program and the size of the storage space of the nor flash memory chip, and the reconfiguration program of each V7FPGA chip stores three parts. The nor gate flash memory chips 1-4 store program states as shown in table 1:
TABLE 1 NOR gate flash memory chips 1-4 store program distribution
It should be noted that the number of nor flash memory chips 1-2 and nor flash memory chips 3-4 is related to the size of the original program and the number of V7FPGA chips. If the original program is larger, or the number of the V7FPGA chips is increased, the number of the NOR gate flash memory chips 1-2 and the number of the NOR gate flash memory chips 3-4 are also increased correspondingly so as to store the original program and the reconstruction program of the V7FPGA chips.
And after the ground station sends the reconstruction program to the main control FPGA chip, the main control FPGA chip receives the reconstruction program and checks the reconstruction program. And if the verification fails, sending an instruction for retransmitting the reconstruction program to the ground station. And if the reconstruction program is verified successfully, writing the reconstruction program into the NOR gate flash memory chip 3 or the NOR gate flash memory chip 4. And the main control FPGA chip controls the V7FPGA chip to restart, so that the V7FPGA chip loads a reconstruction program. And if the V7FPGA chip works normally, finishing the reconstruction work of the V7FPGA chip.
The embodiment of the application provides a satellite on-orbit digital baseband platform, which comprises a main control FPGA chip, 5V 7FPGA chips and 4 NOR gate flash memory chips, wherein the NOR gate flash memory chips 1-2 serve as a first nonvolatile storage unit to store an original program of the V7FPGA chip in operation, and the NOR gate flash memory chips 3-4 serve as a second nonvolatile storage unit to store a reconstruction program of the V7FPGA chip. And the main control FPGA chip receives the reconstruction program sent by the ground station and verifies the reconstruction program. And if the verification is successful, the main control FPGA chip writes the reconstruction program into a specific interval in the NOT gate flash memory chips 3-4. And after the reconstruction program is stored, the main control FPGA chip restarts the V7FPGA chip so that the V7FPGA chip loads the reconstruction program. And if the V7FPGA chip works normally, the reconstruction of the V7FPGA chip is realized. If the V7FPGA chip can not load the reconstruction program normally, the main control FPGA chip controls the V7FPGA chip to operate the original program again for normal work, and the reliability of the on-orbit operation of the V7FPGA chip is further improved.
Based on the above embodiments, an embodiment is provided below to describe the working process of the satellite in-orbit digital baseband platform in detail.
Fig. 4 is a flowchart of a method for implementing in-orbit reconstruction of a satellite in-orbit digital baseband platform according to an embodiment of the present application, where an execution subject of the method is a main control unit in the satellite in-orbit digital baseband platform, and the method may include:
s401: and receiving a reconstruction program sent by the ground station for the original program.
The original program is a program that the satellite control unit 202 is running. The rebuild program may be a modified program of the original program or an upgraded program of the original program.
Because the reconfiguration program is large, when the ground station transmits the reconfiguration program, the reconfiguration program may be divided into a plurality of data packets, and then the data packets are transmitted to the main control unit 201 by the data uplink injection method according to the appointed length. The main control unit 201 may be a main control FPGA chip.
It should be noted that, before the ground station sends the reconfiguration program, the reconfiguration program is tested for multiple times, so as to reduce the probability of reconfiguration program error, and ensure that the satellite control unit 202 can load the reconfiguration program. The satellite control unit 202 may be a V7FPGA chip, and performs an in-orbit task of a satellite. The number of the satellite control units 202 may be one or more.
S402: the reconstruction program written in the second nonvolatile memory cell is verified. If the verification fails, S403 is executed, and if the verification succeeds, S404-S405 are executed.
The second nonvolatile memory unit 204 may be a nor flash memory chip that stores the reconfiguration program loaded by the satellite control unit 202.
To ensure that the reconstruction program written to the second non-volatile memory unit 204 is correct, the reconstruction program needs to be checked before writing. Optionally, the reconstruction program may be checked by a Cyclic Redundancy Check (CRC).
When the reconstruction program is transmitted in the form of a plurality of data packets, it is necessary to check each data packet. After the current data packet is successfully verified, the next data packet can be transmitted.
S403: and sending an instruction message for retransmitting the reconstruction program to the ground station.
If the reconfiguration program fails to verify, it indicates that there may be an error in the reconfiguration program, and therefore the ground station is required to retransmit the reconfiguration program in order to ensure the proper operation of the satellite control unit 202.
In an implementation scenario, if the current data packet fails to be verified, only the information for retransmitting the data packet may be sent to the ground station, and the data packet successfully verified before the data packet does not need to be retransmitted.
It will be appreciated that during the priming of the reconstruction program, the transmission of the reconstruction program may be interrupted. Due to the fact that the high orbit satellite transit time is long, large-scale program injection can be completed. And the transit time of the low-orbit satellite is short, and all reconstruction programs cannot be injected at one time, so that the injection of the reconstruction programs can be performed only in the low-orbit satellite entry event.
S404: and writing the reconstruction program into the second nonvolatile storage unit, controlling the satellite control unit to restart and loading the reconstruction program stored in the second nonvolatile storage unit.
The storage space of the second nonvolatile memory unit 204 may be divided according to the size of the original program. The main control unit 201 may store the reconfiguration program of the satellite control unit 202 into a specific memory space. In one implementation scenario, the main control unit 201 and the second nonvolatile memory unit 204 share data lines, address lines, and control lines. The main control unit 201 may select a specific second nonvolatile memory unit 204 through an address line and control it through a control line. The data line is then used to transmit the reconstruction program.
When the reconfiguration program is loaded, the main control unit 201 may restart the satellite control unit 202 so that the satellite control unit 202 does not run the original program any more, call the corresponding reconfiguration program stored in the second nonvolatile storage unit 204, and control the satellite control unit 202 to load the reconfiguration program.
S405: and judging whether the satellite control unit works normally. If the satellite control unit works normally, S406 is executed, and if the satellite control unit works abnormally, S407 is executed.
After the satellite control unit 202 loads the reconfiguration program, the main control unit 201 needs to monitor the operating states of the plurality of satellite control units 202. If the satellite control unit 202 can normally load the reconfiguration program, it indicates that the satellite control unit 202 is operating normally. If the satellite control unit 202 cannot normally load the reconfiguration program, it indicates that the satellite control unit 202 is operating abnormally.
S406: and sending reconstruction success information to the ground station.
When the main control unit 201 monitors that the satellite control unit 202 works normally, the reconstruction program can be loaded normally, and the main control unit 201 sends reconstruction success information to the ground station, which indicates that the on-orbit reconstruction work is completed.
S407: and judging whether the restarting frequency of the satellite control unit reaches a threshold value or not, and controlling the satellite control unit to work according to whether the restarting frequency reaches the threshold value or not. If the threshold is reached, S408 is performed. If the threshold is not reached, S404-S407 are performed.
In an implementation scenario, the satellite control unit 202 may be affected by the external space environment, so that the reconstruction program is not normally loaded after the satellite control unit 202 is restarted once. In order to reduce the influence of other factors, a restart time threshold of the satellite control unit 202 is set in the main control unit 201, and the satellite control unit 202 is restarted for multiple times.
In an implementation scenario, if the number of restarts does not reach the threshold, the satellite control unit 202 is controlled to continue restarting until the satellite control unit 202 works normally.
S408: and rewriting the original program into the second nonvolatile storage unit, and controlling the satellite control unit to load the original program.
In order to ensure the safety and reliability of the in-orbit operation of the satellite, when the error occurs in the reconfiguration program and causes the abnormal operation of the satellite control unit 202, the main control unit 201 may control to rewrite the original program into the second nonvolatile storage unit 204, so that the satellite control unit 202 can load the original program to perform the normal operation.
Optionally, in the design of the loading logic of the main control unit 201, it is configured that after the main control unit 201 receives a reset instruction or power-off and power-on operations, the main control unit 201 controls all the satellite control units 202 to load the original programs.
The embodiment of the application provides a satellite on-orbit digital baseband platform operation method. And after the reconstruction program is written, the main control unit restarts the satellite control unit to enable the satellite control unit to carry out the reconstruction program. If the satellite control unit works normally, the reconstruction program can be loaded normally by the satellite control unit, and the reconstruction work is finished. When the satellite control unit still works abnormally after being restarted for multiple times, the main control unit writes the original program into the second nonvolatile storage unit to control the satellite control unit to operate the original program, so that the reconstruction of the operating program of the satellite control unit is realized, and the operating reliability of the satellite control unit is improved. Meanwhile, when the satellite control unit loads the reconstruction program to be abnormal, the main control unit can control the satellite control unit to operate the original program again, and the operation reliability of the satellite control unit is further improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A satellite in-orbit digital baseband platform, comprising: the satellite navigation system comprises a main control unit, a plurality of satellite control units, at least one first nonvolatile storage unit and at least one second nonvolatile storage unit;
the first nonvolatile storage unit is used for storing an original program for controlling the operation of the satellite control unit;
the satellite control unit is used for executing the satellite on-orbit task;
the main control unit is used for receiving a reconstruction program for the original program sent by the ground station, writing the reconstruction program into the second nonvolatile storage unit, and controlling the satellite control unit to restart and load the reconstruction program stored in the second nonvolatile storage unit.
2. The platform of claim 1, wherein the master unit is further configured to: and verifying the reconstruction program written into the second nonvolatile storage unit, and if the verification is successful, controlling the satellite control unit to load the reconstruction program.
3. The platform of claim 2, wherein the master unit is further configured to:
and if the verification fails, sending an indication message for resending the reconstruction program to the ground station.
4. The platform according to any one of claims 1 to 3, wherein the master control unit is specifically configured to:
judging whether the satellite control unit works normally or not;
and if the satellite control unit works normally, sending reconstruction success information to the ground station.
5. The platform of claim 4, wherein the master unit is further configured to:
if the satellite control unit works abnormally, judging whether the restarting frequency of the satellite control unit reaches a threshold value;
and controlling the satellite control unit to work according to whether the restart times reach a threshold value.
6. The platform of claim 5, wherein the master unit is further configured to:
and if the restarting frequency does not reach the threshold value, controlling the satellite control unit to continue restarting until the satellite control unit works normally.
7. The platform of claim 6, wherein the master unit is further configured to:
and if the restart times reach a threshold value, rewriting the original program into the second nonvolatile storage unit, and controlling the satellite control unit to load the original program.
8. The platform according to any one of claims 1 to 3, wherein the main control unit is a main control Field Programmable Gate Array (FPGA) chip, the satellite control unit is a V7FPGA chip, a data loading pin of the main control FPGA chip is shared among a plurality of the V7FPGA chips, and the main control FPGA chip loads each of the V7FPGA chips through a chip selection pin.
9. The platform of claim 8, wherein the first non-volatile storage unit and the second non-volatile storage unit are NOR gate flash memory chips.
10. The platform of claim 9, wherein the master FPGA chip shares data, address, and control lines with the nor flash memory chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111679269.3A CN114313314A (en) | 2021-12-31 | 2021-12-31 | Satellite in-orbit digital baseband platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111679269.3A CN114313314A (en) | 2021-12-31 | 2021-12-31 | Satellite in-orbit digital baseband platform |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114313314A true CN114313314A (en) | 2022-04-12 |
Family
ID=81022856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111679269.3A Pending CN114313314A (en) | 2021-12-31 | 2021-12-31 | Satellite in-orbit digital baseband platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114313314A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040078103A1 (en) * | 2002-01-11 | 2004-04-22 | Marshall Joseph R. | Reconfigurable digital processing system for space |
| CN101630306A (en) * | 2009-08-14 | 2010-01-20 | 西北工业大学 | Dynamic reconfigurable device and method for carrying out dynamic reconfiguration thereby |
| CN109491707A (en) * | 2018-10-26 | 2019-03-19 | 西安空间无线电技术研究所 | A kind of in-orbit reconstruct of DSP program and maintaining method |
| CN109783434A (en) * | 2018-10-25 | 2019-05-21 | 西安空间无线电技术研究所 | The highly reliable in-orbit reconfiguration system of spaceborne single machine multi-disc SRAM type FPGA of low-cost and method |
| US20190196927A1 (en) * | 2017-12-26 | 2019-06-27 | Thales | Programmable electronic computer in an avionics environment for implementing at least one critical function and associated electronic device, method and computer program |
| CN111611201A (en) * | 2020-06-24 | 2020-09-01 | 中国人民解放军国防科技大学 | Refresh self-adaptive continuous high-leanable-rail FPGA reconstruction system and method |
| CN112666856A (en) * | 2020-12-09 | 2021-04-16 | 浙江吉利控股集团有限公司 | Satellite load subsystem |
| CN113572529A (en) * | 2021-06-18 | 2021-10-29 | 北京极光星通科技有限公司 | Satellite-borne laser communication terminal software reconstruction method and system |
| CN113849456A (en) * | 2021-10-18 | 2021-12-28 | 中国科学院长春光学精密机械与物理研究所 | Spaceborne FPGA reconstruction method |
-
2021
- 2021-12-31 CN CN202111679269.3A patent/CN114313314A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040078103A1 (en) * | 2002-01-11 | 2004-04-22 | Marshall Joseph R. | Reconfigurable digital processing system for space |
| CN101630306A (en) * | 2009-08-14 | 2010-01-20 | 西北工业大学 | Dynamic reconfigurable device and method for carrying out dynamic reconfiguration thereby |
| US20190196927A1 (en) * | 2017-12-26 | 2019-06-27 | Thales | Programmable electronic computer in an avionics environment for implementing at least one critical function and associated electronic device, method and computer program |
| CN109783434A (en) * | 2018-10-25 | 2019-05-21 | 西安空间无线电技术研究所 | The highly reliable in-orbit reconfiguration system of spaceborne single machine multi-disc SRAM type FPGA of low-cost and method |
| CN109491707A (en) * | 2018-10-26 | 2019-03-19 | 西安空间无线电技术研究所 | A kind of in-orbit reconstruct of DSP program and maintaining method |
| CN111611201A (en) * | 2020-06-24 | 2020-09-01 | 中国人民解放军国防科技大学 | Refresh self-adaptive continuous high-leanable-rail FPGA reconstruction system and method |
| CN112666856A (en) * | 2020-12-09 | 2021-04-16 | 浙江吉利控股集团有限公司 | Satellite load subsystem |
| CN113572529A (en) * | 2021-06-18 | 2021-10-29 | 北京极光星通科技有限公司 | Satellite-borne laser communication terminal software reconstruction method and system |
| CN113849456A (en) * | 2021-10-18 | 2021-12-28 | 中国科学院长春光学精密机械与物理研究所 | Spaceborne FPGA reconstruction method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111611201B (en) | Refresh self-adaptive continuous high-leanable-rail FPGA reconstruction system and method | |
| CN108052355B (en) | Satellite-borne load unit software on-orbit weight composing method | |
| CN107957972B (en) | FPGA-based on-orbit reconstruction system and method | |
| US7200845B2 (en) | System and method for high availability firmware load | |
| US8479045B2 (en) | Controller for disk array device, data transfer device, and method of power recovery process | |
| CN1333358C (en) | In-circuit configuration architecture with configuration on initialization function | |
| US11392368B2 (en) | Electronic control system for updating circuit | |
| CN108415718B (en) | BootLoader design method applied to on-line updating of satellite-borne software | |
| CN110489376B (en) | On-orbit reconstruction frame system and reconstruction method for whole satellite hardware | |
| US20030106052A1 (en) | System and method for high availability firmware load | |
| CN112732334A (en) | High-continuity navigation satellite software reconstruction method | |
| CN114860650A (en) | Multi-chip SRAM type FPGA on-orbit configuration management device | |
| CN102541690A (en) | Intelligent card and method for recovering data | |
| CN112306726B (en) | Single-particle-upset-resistant system and method | |
| CN113835923A (en) | Reset system, data processing system and related equipment | |
| CN100421099C (en) | In-circuit configuration architecture for embedded configurable logic array | |
| CN1333357C (en) | In-circuit configuration architecture with non-volatile configuration store | |
| CN113238985A (en) | FPGA (field programmable Gate array) on-orbit reconstruction control system and method | |
| CN114313314A (en) | Satellite in-orbit digital baseband platform | |
| CN111680000B (en) | Configuration system and method of field programmable gate array | |
| US7747911B1 (en) | Self verification of non-volatile memory | |
| CN113467990B (en) | Deep space exploration important data backup and recovery method and system | |
| CN116185510A (en) | Partition switch starting method, array server and computer readable storage medium | |
| CN111930393B (en) | On-orbit programming system, method and circuit for satellite-borne software | |
| US9026762B2 (en) | Semiconductor system including a controller having reduced number of memory buffers for transmitting data to a plurality of memory chips |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220412 |