CN114303160A

CN114303160A - Video interpolation using one or more neural networks

Info

Publication number: CN114303160A
Application number: CN202080061061.2A
Authority: CN
Inventors: F·里达; 孙德庆; A·邓达; M·休伊比; 刘贵林; K·施; A·陶; J·考茨; B·卡坦扎罗
Original assignee: Nvidia Corp
Current assignee: Nvidia Corp
Priority date: 2019-09-03
Filing date: 2020-08-19
Publication date: 2022-04-08
Also published as: DE112020003165T5; WO2021045904A1; US20210067735A1; GB2600359A

Abstract

The present invention relates to devices, systems, and techniques for enhancing video. In at least one embodiment, a second video having a higher frame rate, higher resolution, or a reduced number of missing or corrupted video frames is created from a first video using one or more neural networks.

Description

Video interpolation using one or more neural networks

Technical Field

At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training a neural network in accordance with various novel techniques described herein.

Background

As video content is being consumed in an ever-increasing variety of ways, on a variety of devices, and from a variety of sources, there may be instances of video content that are not optimal for a particular use or application. For example, the video may be at a lower frame rate or resolution desired for a particular viewing device. It is also possible that one or more dropped frames occur, or that there is an error in one or more data frames.

Drawings

Various embodiments according to the present disclosure will be described below with reference to the accompanying drawings, in which:

FIGS. 1A, 1B, and 1C illustrate video streaming according to at least one embodiment;

FIG. 2 illustrates the use of video frames for training a neural network in accordance with at least one embodiment;

FIG. 3 illustrates the use of video frames for fine-tuning a neural network trained for different domains in accordance with at least one embodiment;

FIG. 4 illustrates an input and inference video frame in accordance with at least one embodiment;

5A, 5B, and 5C illustrate portions of a process for training and reasoning using one or more neural networks in accordance with at least one embodiment;

FIG. 6 illustrates a system for training and reasoning using one or more neural networks in accordance with at least one embodiment;

FIG. 7 illustrates a system for training one or more neural networks in accordance with at least one embodiment;

FIG. 8 illustrates a structure of a neural network in accordance with at least one embodiment;

FIG. 9A illustrates inference and/or training logic in accordance with at least one embodiment;

FIG. 9B illustrates inference and/or training logic in accordance with at least one embodiment;

FIG. 10 illustrates an example data center system in accordance with at least one embodiment;

FIG. 11 illustrates a computer system in accordance with at least one embodiment;

FIG. 12 illustrates a computer system in accordance with at least one embodiment;

FIG. 13 illustrates a computer system in accordance with at least one embodiment;

FIG. 14 illustrates a computer system in accordance with at least one embodiment;

FIG. 15A illustrates a computer system in accordance with at least one embodiment;

FIG. 15B illustrates a computer system in accordance with at least one embodiment;

FIG. 15C illustrates a computer system in accordance with at least one embodiment;

FIG. 15D illustrates a computer system in accordance with at least one embodiment;

15E and 15F illustrate a shared programming model in accordance with at least one embodiment;

FIG. 16 illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

17A-17B illustrate an exemplary integrated circuit and associated graphics processor, according to at least one embodiment;

18A-18B illustrate additional exemplary graphics processor logic, in accordance with at least one embodiment;

FIG. 19 illustrates a computer system in accordance with at least one embodiment;

FIG. 20A illustrates a parallel processor in accordance with at least one embodiment;

FIG. 20B illustrates a partition unit in accordance with at least one embodiment;

FIG. 20C illustrates a processing cluster in accordance with at least one embodiment;

FIG. 20D illustrates a graphics multiprocessor in accordance with at least one embodiment;

FIG. 21 illustrates a multiple Graphics Processing Unit (GPU) system in accordance with at least one embodiment;

FIG. 22 illustrates a graphics processor in accordance with at least one embodiment;

FIG. 23 illustrates a microarchitecture of a processor in accordance with at least one embodiment;

FIG. 24 illustrates a deep learning application processor in accordance with at least one embodiment;

FIG. 25 illustrates an example neuromorphic processor in accordance with at least one embodiment;

FIGS. 26 and 27 illustrate at least a portion of a graphics processor according to at least one embodiment;

FIG. 28 illustrates at least a portion of a graphics processor core in accordance with at least one embodiment;

29A-29B illustrate at least portions of a graphics processor core in accordance with at least one embodiment;

FIG. 30 illustrates a parallel processing unit ("PPU") according to at least one embodiment;

FIG. 31 illustrates a general purpose processing cluster ("GPC") according to at least one embodiment;

FIG. 32 illustrates a memory partition unit of a parallel processing unit ("PPU") in accordance with at least one embodiment; and

FIG. 33 illustrates a streaming multiprocessor in accordance with at least one embodiment.

Detailed Description

In at least one embodiment, the sequence of video frames 100 may be received on a video stream as shown in FIG. 1A. In at least one embodiment, successive video frames may include changes from earlier video frames. In at least one embodiment, the frame rate at which the video is captured or created can determine not only the frequency at which the video refreshes the image, but also how much change occurs between frames. In at least one embodiment, it may be desirable to improve the frame rate or number of frames per second in this video stream or related video files or clips. In at least one embodiment, increasing the frame rate may improve the viewer's experience of the video stream or may improve the perceived quality of the video stream. In at least one embodiment, one or more of the video frames may be dropped from the video stream due to errors, as shown in video stream sequence 120 of FIG. 1B. In at least one embodiment, both of the cases of fig. 1A and 1B may benefit from the addition of video frames to improve the frame rate of the video or to replace one or more dropped frames. In at least one embodiment, such a method may result in a video stream sequence 140 as shown in FIG. 1C, where any dropped frames are replaced and the overall frame rate is increased. In at least one embodiment, it may be desirable to correct either, both, or neither, but to increase the resolution of the video stream.

In at least one embodiment, image interpolation may be used to enhance video, which may be in the form of streaming, broadcast, file, or other such formats. In at least one embodiment, machine learning can be used to perform the interpolation. In at least one embodiment, the neural network may be trained using unsupervised training in order to avoid the need for large amounts of high resolution or high frame rate video data for training. In at least one embodiment, a periodic consistency constraint may be applied during training of the network in order to provide ground truth data that is simulated for the purpose of training the network.

In at least one embodiment, as shown in FIG. 2, an image frame 200 may be received or interpolated. In at least one embodiment, a set of frame triplets from a video stream or file may be used to train a neural network. In at least one embodiment, a frame triplet may include three adjacent frames in a sequence of a video stream over time. In at least one embodiment, as shown in FIG. 2, a set of three

video frames

202, 204, 206 are used to generate interpolated video frames. In at least one embodiment, the

frames

202 and 204 are provided as input training data and used to generate interpolated video frames 208 corresponding to points in time between those

frames

202 and 204. In at least one embodiment, frames 204 and 206 are used to generate another interpolated video frame 210 corresponding to a point in time between

frames

204 and 206. In at least one embodiment, these interpolated

frames

208, 210 may be used as input frames to generate interpolated versions of the frame 204 at corresponding points in time in the video file. In at least one embodiment, this interpolated version of the frame 204 may be compared to the received input frame 204 and to the differences analyzed to calculate the loss according to the determined loss function. In at least one embodiment, parameters of the network are adjusted or updated in an attempt to minimize the loss value. In at least one embodiment, multiple deliveries or periods may occur for a given frame triplet, and many or all of the triplets for a given video stream or file may be used for training until at least a convergence or end criterion is met. In at least one embodiment, the input frames 202, 204, 206 and interpolated

frames

208, 210 may then be used to generate a higher frame rate video stream 212. In at least one embodiment, a pair of input frames 204, 206 may be used to generate a plurality of interpolated frames 210 therebetween, and any or all of those interpolated frames may be used to generate an interpolated version of at least one of the input images 204.

In at least one embodiment, such a network, once trained, can be used to synthesize high frame rate video by interpolation. In at least one embodiment, unsupervised techniques may be used to synthesize high frame rate video directly from low frame rate video using periodic consistency. In at least one embodiment, one or more machine learning models are optimized to minimize the difference between the center frame of a frame triplet and its periodic reconstruction, as may be obtained by interpolating values back from interpolated intermediate frames. In at least one embodiment, consumer-grade smartphones and digital cameras can record video at high frame rates (e.g., 240 frames per second), but due to costs associated with high power consumption, greater storage requirements, and reduced video resolution, conventional events may not be recorded at high frame rates. In at least one embodiment, the trained network can be used to generate arbitrarily high Frames Per Second (FPS) video (e.g., 60 or 90FPS) from any of these lower FPS videos (e.g., 30 FPS). In at least one embodiment, generating one or more intermediate frames from two consecutive frames may increase the total number of frames in the video, which may enable people to visualize events with slow motion and better understand what is represented. In at least one embodiment, interpolation techniques can be used to provide a high refresh rate or smooth viewing experience.

In at least one embodiment, a set of unsupervised learning techniques can be used to learn video frame interpolation by enforcing models to satisfy a temporal periodic consistency constraint without requiring paired training data. In at least one embodiment, for a given triplet of consecutive frames, two intermediate frames between two consecutive frames may be generated and used to generate back their intermediate frames. In at least one embodiment, the generated frame should match the original input intermediate frame included in the video with acceptable loss.

In at least one embodiment, the periodic consistency constraint encourages that the transformation predicted by the model be reversible and can be used to regularize model behavior when direct supervision is not available. In at least one embodiment, in the context of video interpolation, the period consistency constraint provides reconstruction of the original input frames by interpolating between predicted intermediate frames at appropriate timestamps. In at least one embodiment, the intermediate frames can be predicted at any time stamp between the outer frames. In at least one embodiment, a training method that is completely unsupervised, just as the target intermediate frames are not used for supervision, and the model can learn to generate a high frame rate interpolation sequence from any lower frame rate sequence.

In at least one embodiment, the model can be trained toMany intermediate frames are arbitrarily interpolated from a pair of input frames in an unsupervised manner, using unpaired intermediate ground truth frames. In at least one embodiment, a pair of input frames I is given₀And I₁Intermediate frame

Can be generated as:

wherein t ∈ (0, 1) represents time,

representing a video frame interpolation model for learning without supervision. In at least one embodiment, one or more deep Convolutional Neural Network (CNN) implementations are used

In at least one embodiment, CNNs are chosen because they are capable of modeling highly nonlinear mappings, are easy to implement, and have proven robust to various visual tasks, including image classification, segmentation, and video interpolation.

In at least one embodiment of the present invention,

may be optimized to maintain periodic consistency over time. In at least one embodiment, I₀、I₁And 1₂Is a triplet of consecutive input frames. In at least one embodiment, a time-domain periodic consistency constraint is specified such that the constraint is directed to the (I) in₀，I₁) And (I)₁，I₂) Intermediate frames generated at time t in between, then interpolation results

The generated intermediate frame at the time (1-t) in between matches the originalIntermediate input frame I₁. In at least one embodiment, the method of using is given mathematically

Reconstructed cycle framework:

in at least one embodiment, the optimization

So that

And I₁The reconstruction error between is minimized, as can be given by:

in at least one embodiment, the triplet of input frames can be directly utilized. In at least one embodiment, a system may be used

(I₀，1₂T ═ 0.5) and I₁Without periodic consistency. In at least one embodiment, such targets that model interpolation over a large time step, if used without periodic consistency, may result in significantly worse accuracy. In at least one embodiment, the optimization is performed over time

To satisfy the temporal periodic consistency (CC) constraint is efficient and can arbitrarily generate many realistic and temporally smooth intermediate frames.

In at least one embodiment, a pseudo-supervised loss term is introduced that may force interpolated frames to be consistent with predictions of a pre-trained interpolation model. In at least one embodiment, the pseudo-supervised loss term used with periodic consistency can effectively adapt a pre-trained model to a new target domain. In at least one embodiment, such an approach can significantly improve the pre-trained model on the new target domain without additional data and in a completely unsupervised manner.

In at least one embodiment, a video stream may be received that includes three sets of video frames 302, 304, 306 as shown in scenario 300 of FIG. 3. In at least one embodiment, the input frames can be provided to a machine learning model trained for another domain using an out-of-domain data set. In at least one embodiment, this trained model may be sufficient to produce enhanced video in different domains, but may be fine-tuned for performance in a particular domain. In at least one embodiment, the trained model may lack ground truth frames for the target domain. In at least one embodiment, unsupervised fine-tuning techniques utilizing these pre-trained models can be utilized. In at least one embodiment, model refinement is performed on target video without additional data by optimizing to jointly satisfy the periodic consistency and minimize the difference between the generated intermediate frames and the corresponding predictions from this pre-trained model. In at least one embodiment, during the trimming or further training process, the input frames 302 may be fed to a training network to generate interpolated frames 308. In at least one embodiment, this will correspond to a frame generated using frame 302 at inference time. In at least one embodiment, the frame 304 may also be used to generate a version of the interpolated frame 308. In at least one embodiment, the interpolated frame 308 may correspond to any time between the times of the

frames

302 and 304, as may be randomly selected or determined by the selection process. In at least one embodiment, the versions of frame 308 interpolated from

frames

302 and 304 are compared to determine a missing value. In at least one embodiment, the parameters of the model may be adjusted to attempt to minimize the loss value. In at least one embodiment, a similar method is used to compare versions of one or more interpolated frames 310 generated from

adjacent frames

304 and 306. In at least one embodiment, this fine-tuning model can be used to infer interpolated frames that can be interspersed with corresponding input frames to generate the higher frame rate video 312, or frames without frame dropping as previously discussed. In at least one embodiment, such a method may also be used to infer higher resolution video frames (e.g., HD or 4K from SD), which may be used to generate a higher resolution video stream 314 based on a lower resolution input video stream.

In at least one embodiment, such a method may be used to reason about video frames based on one or more input frames. In at least one embodiment, as shown in FIG. 4, frames of an input video stream 400 may be used to generate a higher frame rate stream. In at least one embodiment, the output stream video 420 may include interpolated frames 422 between each pair of input frames. In at least one embodiment, the interpolated frame 442 may be at any location in time between adjacent input frames in the output stream 440. In at least one embodiment, multiple interpolated

frames

462, 464, 466 may be located between adjacent input frames as shown in the output stream 460.

In at least one embodiment, the techniques may make the unsupervised fine tuning process robust. In at least one embodiment, out-of-domain training videos may be rarely accessed, and available target domain videos may lack ground truth intermediate frames. In at least one embodiment, optimization can be performed in a target video

To jointly satisfy the periodic consistency and learn an approximately known pre-trained interpolation model, denoted as

In at least one embodiment, this modified target is mathematically given by:

wherein

Is a periodically reconstructed frame, given as discussed above

And

and is

Is updated by an optimization process

And (4) parameters.

In at least one embodiment, intermediate frames are concealed by constraining fidelity

And

to be similar to the known frame interpolation model

For approximation of

Can help regularize it

To generate realistic hidden intermediate frames

And

in at least one embodiment, as optimization progresses and

study ofPicking up the interpolation concept, it is possible to limit the contribution of regularized pseudo-supervised (PS) losses and make the optimization more guided by periodic consistency. In at least one embodiment, such a replacement loss term, as may be derived from the estimated intermediate frames, may be generated by exposing the training process to

Many variations of (a) make the training process converge faster or make the optimization process robust. In at least one embodiment of the present invention,

can be selected to be equivalent to

But is pre-trained supervised on disjoint datasets with ground truth high frame rate video and is denoted as

In at least one embodiment, the final goal may be given by:

where λ rc and λ rp are the weights lost for CC and PS.

In at least one embodiment, optimizing this equation by relying only on PS losses and not on periodic consistency would teach

Is expressed as in the best mode

In at least one embodiment, appropriately weighting the periodic consistency and PS loss can achieve frame interpolation results that are superior to those obtained by learning using CC or PS loss alone. In at least one embodiment, a system may be usedStream-based CNN implementation for video interpolation

Such as a super slow motion model that is capable of synthesizing an arbitrary number of high quality and temporally stable intermediate frames. In at least one embodiment, the technique is not limited to this particular interpolation model.

In at least one embodiment, the input frames (I) are derived from a pair of input frames₀，I₁) Generating one or more intermediate frames

In at least one embodiment, the flow-based model estimates from any time t to 0, F_t→₀And from t to 1, F_t→₁Approximately bi-directional optical flow. In at least one embodiment, the model then generates frames by linearly blending the input frames after they are warped by the respective estimated optical flows, as can be given by:

where T is the bilinear sampling of the input frame using optical flow, and α weights the contribution of each term. In at least one embodiment, the blending weight α models both global properties of temporal consistency and local or pixel-by-pixel occlusion or de-occlusion reasoning. In at least one embodiment, to maintain temporal consistency, when t is close to 0, I ₀Must be paired with

Contributing more. In at least one embodiment, when t is close to 1, I₁To pair

Contributing more.

In at least one embodiment, in order to cleanly blend the two images, the important property of video frame interpolation is exploited such that not all pixels at time t are visible in both input frames. In at least one embodiment, the value α can be decomposed to model both temporal consistency and occlusion or de-occlusion, as given below:

wherein, V_t←0And V_t←0Is a visibility graph, and Z ═ 1-t) V_t←0+tV_t←1Is a normalization factor. In at least one embodiment, V_t←0(p)∈[0,1]Representing the visibility of pixel p at time t (0 means completely occluded or invisible at t). In at least one embodiment, an intermediate bi-directional optical flow (F) may be estimated_t→₀,F_t→₁) And a corresponding visibility map (V)_t←0,V_t←1)。

In at least one embodiment of the present invention,

can be trained to generate any number of intermediate frames

Without using corresponding ground truth intermediate frames

Wherein N and t_iE (0,1) is the frame count and time, respectively. In at least one embodiment, optimization can be performed

Reconstructing frames with minimized periodicity

And I₁Error between, and minimizing inter-predicted frames

And

with corresponding estimated or pseudo ground truth frames

And

the error between.

In at least one embodiment, in the optimization process, frames are periodically reconstructed

Frames that can be generated through any number of intermediates

To obtain the final product. In at least one embodiment, the training frame { I } may be selected from₀，I₁，I₂The single triplet of points calculates multiple reconstruction errors. In at least one embodiment, very little reconstruction error per triplet set may help stabilize training and produce realistic intermediate frames. In at least one embodiment, at random time t_iE (0,1) calculates one reconstruction error per triplet. In at least one embodiment, the training loss function is given by:

wherein,

given by:

the goodness of the periodically reconstructed frame is modeled, and

the proximity of the concealment intermediate frames to our dummy intermediate frames is modeled.

The high-level features of the VGG-16 model pre-trained on ImageNet are defined as

The perceptual loss of norm is modeled and given as:

Ψ represents the conv4_3 feature of the VGG-16 model.

In at least one embodiment, the third loss

Is the distortion loss that makes the optical flow prediction realistic and can be given by:

in at least one embodiment, a smoothness constraint may be enforced to encourage neighboring flows to have similar flow values, and may be given by:

￡_S＝║ΔF_t→_t+1║₁,+║ΔF_t→_1+t║₁,+

║ΔF₀→₁║₁,+║ΔF₁→₀║₁,+

║ΔF₁→₂║₁,+║ΔF₂→₁║₁

Wherein, F_t→_t+1And F_t+1→_tIs predicted in the middle

And

forward and backward optical flow between frames. In at least one embodiment, the losses may be linearly combined using experimentally selected weights: lambda [ alpha ]_rc＝0.8,λ_rp＝0.8,λ_p＝0.05,λ_w＝0.4,andλ_s＝1。

In at least one embodiment, the process 500 shown in FIG. 5A may be used to train a model to interpolate video frames for purposes such as enhancing video data. In at least one embodiment, a video file or stream 502 is received or otherwise obtained. In at least one embodiment, frames from the video are provided as input training data to a training system for training a neural network. In at least one embodiment, three consecutive video frames are utilized to generate two interpolated video frames 504 between those video frames. In at least one embodiment, the trained model may use any suitable interpolation model (e.g., for linear or non-linear interpolation) to generate interpolated frames. In at least one embodiment, the pair of interpolated frames can be passed to the model as additional input and utilized to generate an interpolated version 506 of the intermediate video frame of this video triplet being analyzed. In at least one embodiment, the input version and the interpolated version of this intermediate frame are compared to determine a loss value 508 from the determined loss function. In at least one embodiment, one or more network parameters may be adjusted in an attempt to minimize the loss 510. A decision 512 can be made as to whether the final criteria have been met. In at least one embodiment, the final criteria may include the model determined to converge or the maximum number of frames being processed. In at least one embodiment, if more frames are to be analyzed and the final criteria are not met, the process may continue with another frame triplet. In at least one embodiment, if the final criteria have been met, a trained model may be provided for inferring a higher quality video 514 that includes at least some interpolated frames, e.g., may have a higher resolution, a higher frame rate, or a lesser number of dropped or missing frames than the original input video.

In at least one embodiment, the process 530 shown in FIG. 5B can be used to further train or refine the model to interpolate video frames in a different domain than that used for training for purposes such as enhancing video data. In at least one embodiment, a video file or stream is received or otherwise obtained 532. In at least one embodiment, frames from the video are provided as input training data to a training system for refining the trained neural network. In at least one embodiment, interpolated video frames 534 are generated at points in time between successive video frames using the successive frames. In at least one embodiment, the interpolated video frames are compared to determine a loss value 536 according to the determined loss function. In at least one embodiment, one or more network parameters may be adjusted to attempt to minimize the loss 538. A decision 540 can be made as to whether the final criteria have been met. In at least one embodiment, if more frames are to be analyzed and the final criteria have not been met, this process may continue with another set of video frames. In at least one embodiment, final criteria are met, and then a trained model may be provided for inferring an enhanced video stream or file 542 that includes at least some interpolated frames, e.g., may have a higher resolution, a higher frame rate, or a lesser number of dropped or missing frames than the original input video.

In at least one embodiment, the process 560 shown in FIG. 5C can be used to reason about video frames at inference time for purposes such as enhancing video data. In at least one embodiment, a video file or stream may be received to the trained model 562. In at least one embodiment, the trained model can be used to interpolate the video frames 564 inferentially using the input frames from the video. In at least one embodiment, these interpolated video frames can be utilized to generate an enhanced video stream or file 566.

Neural network training and development

An increasing number of industries and applications utilize machine learning. In at least one embodiment, Deep Neural Networks (DNNs) developed on processors have been used in a variety of use cases, from self-driving to faster drug development, from automatic image analysis of security systems to intelligent real-time language translation in video chat applications. In at least one embodiment, deep learning is a technique that is able to model the neural learning process of the human brain, learn continuously, become increasingly more intelligent, and deliver more accurate results faster over time. Adults initially teach children to correctly recognize and classify various shapes, and ultimately are able to recognize shapes without any guidance. Similarly, in at least one embodiment, a deep learning or neural learning system designed to accomplish similar tasks would need to be trained to become more intelligent and more efficient in identifying base objects, occluded objects, and the like, while also assigning context to those objects.

In at least one embodiment, neurons in the human brain look at various inputs received, importance levels are assigned to each of these inputs, and outputs are passed to other neurons for action. Artificial neurons or perceptrons are the most basic model of neural networks. In at least one embodiment, the perceptron may receive one or more inputs representing various features of the object that the perceptron is trained to recognize and classify, and assign a particular weight to each of these features based on their importance in defining the shape of the object.

A Deep Neural Network (DNN) model includes multiple layers of many connected perceptrons (e.g., nodes) that can be trained with large amounts of input data to quickly solve complex problems with high accuracy. In one example, the first layer of the DNN model decomposes the input image of the car into different sections and looks for basic patterns such as lines and angles. The second layer assembles the line to look for advanced patterns such as wheels, windshields and mirrors. The next layer identifies the type of vehicle and the last few layers generate indicia for the input image, identifying a model of a particular automobile brand. Once the DNN is trained, it can be deployed and used to identify and classify objects or patterns in a process called inference. Examples of reasoning (the process by which DNN extracts useful information from a given input) include recognizing handwritten numbers on cheque checks deposited in ATMs, recognizing images of friends in photographs, delivering movie recommendations, recognizing and classifying different types of cars, pedestrians, and road hazards in unmanned cars, or translating human speech in near real time.

During training, data flows through the DNN in the forward propagation phase until a prediction is generated indicating the label corresponding to the input. If the neural network does not correctly label the input, then the errors between the correct label and the predicted label are analyzed and the weights are adjusted for each feature during the back propagation phase until the DNN correctly labels the input and other inputs in the training dataset. Training complex neural networks requires a significant amount of parallel computational performance, including supported floating-point multiplications and additions. Inference is a delay-sensitive process that is less computationally intensive than training, in which a trained neural network is applied to new inputs that it has not seen before to classify images, translate speech, and infer new information.

Neural networks rely heavily on matrix mathematical operations, and complex multi-layer networks require a large amount of floating point performance and bandwidth to compromise efficiency and speed. With thousands of processing cores, optimized matrix mathematics, and providing tens to hundreds of TFLOPS capabilities, a computing platform can provide the capabilities needed for deep neural network-based artificial intelligence and machine learning applications.

FIG. 6 illustrates components of a system 600 that can be used to train and utilize machine learning in at least one embodiment. As discussed below, the various components may be provided by various combinations of computing devices and resources or a single computing system, which may be under the control of a single entity or multiple entities. Further, aspects may be triggered, initiated, or requested by different entities. In at least one embodiment, training of the neural network may be guided by a provider associated with provider environment 606, while in at least one embodiment, a client or other user accessing the provider environment through client device 602 or other such resource may require training. In at least one embodiment, the training data (or data to be analyzed by the trained neural network) may be provided by a provider, user, or third-party content provider 624. In at least one embodiment, the client device 602 may be a vehicle or object that navigates on behalf of a user, for example, which may submit requests and/or receive instructions to assist in navigating the device.

In at least one embodiment, the request can be submitted to the provider environment 606 across at least one network 604. In at least one embodiment, the client device may be any suitable electronic and/or computing device that enables a user to generate and send such requests, such as may include desktop computers, notebook computers, computer servers, smart phones, tablet computers, game consoles (portable or otherwise), computer processors, computing logic, and set-top boxes. The one or more networks 604 may include any suitable network for sending requests or other such data, and may include, for example, the internet, an intranet, an ethernet, a cellular network, a Local Area Network (LAN), a network of direct wireless connections between nodes, and so forth.

In at least one embodiment, the request may be received to an interface layer 608, which in this example may forward the data to a training and reasoning manager 610. The manager may be a system or service that includes hardware and software for managing data or content related to requests and services. In at least one embodiment, the manager can receive a request to train a neural network and can provide data for the request of the training manager 612. In at least one embodiment, training manager 612 can select an appropriate model or network to use, and can also train the model using relevant training data if not specified by the request. In at least one embodiment, the training data may be a batch of data stored to the training data repository 614, received from the client device 602, or obtained from the third party provider 624. In at least one embodiment, the training manager 612 may be responsible for training data, for example, by using a LARC-based approach as discussed herein. The network may be any suitable network, such as a Recurrent Neural Network (RNN) or a Convolutional Neural Network (CNN). Once the network is trained and successfully evaluated, the trained network may be stored to a model repository 616, e.g., the model repository 616 may store different models or networks for users, applications, services, or the like. In at least one embodiment, there may be multiple models for a single application or entity, as may be utilized based on multiple different factors.

In at least one embodiment, at a subsequent point in time, a request may be received from the client device 602 (or another such device), requesting that the content (e.g., path determination) or data be at least partially determined or influenced by the trained neural network. The request may include, for example, processing input data using a neural network to obtain one or more inferences or other output values, classifications, or predictions. In at least one embodiment, input data may be received into the interface layer 608 and directed to the inference module 618, although different systems or services may also be used. In at least one embodiment, if not already stored locally to inference module 618, inference module 618 can obtain a suitable trained network, such as a trained Deep Neural Network (DNN) as discussed herein, from model repository 616. Inference module 618 can provide data as input to a trained network, which can then generate one or more inferences as output. This may include, for example, classification of instances of the input data. In at least one embodiment, the inference can then be transmitted to the client device 602 for display or other communication to the user. In at least one embodiment, the user's context data can also be stored to a user context data repository 622, which can include data about the user that is useful as input to the network when generating inferences or to determine data to return to the user after obtaining an instance. In at least one embodiment, the relevant data may include at least some input or inference data, and may also be stored to the local database 620 for use in processing future requests. In at least one embodiment, a user may use an account or other information to access resources or functionality of the provider environment. In at least one embodiment, user data can also be collected and used to further train the model, if licensed and available, to provide more accurate reasoning for future requests. In at least one embodiment, the request may be received by the client device 602 executing a user interface of the machine learning application 626 and the results displayed through the same interface. The client device may include resources, such as a processor 628 and memory 630, for generating requests and processing results or responses, and at least one data storage element 632 for storing data for the machine learning application 626.

In at least one embodiment, processor 628 (or a processor of training manager 612 or inference module 618) will be a Central Processing Unit (CPU). However, as mentioned, resources in such environments may utilize the GPU to process at least certain types of requested data. With thousands of cores, GPUs are designed to handle a large number of parallel workloads and therefore become popular in deep learning for training neural networks and generating predictions. While using GPUs for offline building has enabled larger and more complex models to be trained faster, generating predictions offline means that either the features cannot be input at the time of the request or predictions must be generated for the permutations of all features and stored in a look-up table to service real-time requests. If the deep learning framework supports CPU mode, and the model is small and simple enough to perform feed forward on the CPU with reasonable latency, then the service on the CPU instance can host the model. In this case, training may be done offline on the GPU, and reasoning may be done in real-time on the CPU. If the CPU method is not feasible, the service may run on the GPU instance. However, because a GPU has different performance and cost characteristics than a CPU, running a service that offloads the runtime algorithm to the GPU may require it to be designed differently than a CPU-based service.

In at least one embodiment, video data may be provided by the client device 602 for enhancement in the provider environment 606. In at least one embodiment, the video data may be processed for enhancement on the client device 602. In at least one embodiment, the video data may come from a third party content provider 624 and be enhanced by the third party provider 624, provider environment 606, or client device 602.

FIG. 7 illustrates a system 700 for classifying or generating inferences about data in at least one embodiment. In at least one embodiment, both supervised and unsupervised training may be used in at least one embodiment discussed herein. In at least one embodiment, a set of training data 702 (e.g., classified or labeled data) is provided as input to serve as training data. In at least one embodiment, the training data may include instances of at least one class of objects for the neural network to be trained, as well as information identifying the class of objects. In at least one embodiment, the training data may include a set of images, wherein each image includes a representation of a class of objects, wherein each image further includes or is associated with a label, metadata, classification, or other piece of information identifying the class of objects represented in the respective image. Various other types of data may also be used as training data, and may include text data, audio data, video data, and the like. In at least one embodiment, training data 702 is provided as training input to training manager 704. In at least one embodiment, the training manager 704 may be a system or service comprising hardware and software, such as one or more computing devices executing a training application for training a neural network (or other model or algorithm, etc.). In at least one embodiment, the training manager 704 receives instructions or requests indicating a type of model to use for training. In at least one embodiment, the model may be any suitable statistical model, network, or algorithm that may be used for these purposes, such as may include artificial neural networks, deep learning algorithms, learning classifiers, bayesian networks, and the like. In at least one embodiment, training manager 704 can select an initial model or other untrained model from a suitable repository 706 and train the model with training data 702, generate a trained model 708 (e.g., a trained deep neural network) that can be used to classify similar types of data, or generate other such inferences. In at least one embodiment where training data is not used, an appropriate initial model may still be selected for training for the input data of each training manager 704.

In at least one embodiment, the model may be trained in several different ways, as may depend to some extent on the type of model selected. In at least one embodiment, a set of training data may be provided to a machine learning algorithm, where a model is a model artifact created by a training process. In at least one embodiment, each instance of training data contains a correct answer (e.g., classification), which may be referred to as a target or target attribute. In at least one embodiment, the learning algorithm finds patterns in the training data, maps the input data attributes to targets, an answer to predict, and outputs a machine learning model that captures these patterns. In at least one embodiment, a machine learning model may then be used to obtain a prediction of new data for unspecified targets.

In at least one embodiment, the training manager 704 can be selected from a set of machine learning models, including binary classification, multi-class classification, and regression models. In at least one embodiment, a class of models to be used may depend, at least to some extent, on the type of object to be predicted. In at least one embodiment, a machine learning model for binary classification problems predicts a binary outcome, such as one of two possible classes. In at least one embodiment, a learning algorithm such as logistic regression may be used to train the binary classification model. In at least one embodiment, a machine learning model for a multi-class classification problem allows predictions to be generated for multiple classes, such as predicting one of more than two outcomes. Polynomial logistic regression can be used to train multi-class models. Machine learning models for regression problems predict values. Linear regression can be used to train the regression model.

In at least one embodiment, to train a machine learning model according to one embodiment, the training manager must determine the input training data sources, as well as other information (such as the names of the data attributes containing the targets to be predicted, the required data transformation instructions, and the training parameters that control the learning algorithm). In at least one embodiment, during the training process, the training manager 704 can automatically select an appropriate learning algorithm based on the type of target specified in the training data source. In at least one embodiment, the machine learning algorithm may accept parameters for controlling certain characteristics of the training process and the machine learning model produced thereby. These are referred to herein as training parameters. In at least one embodiment, if no training parameters are specified, the training manager may utilize a default value known to work well over a large number of machine learning tasks. Examples of training parameters for which values may be specified include a maximum model size, a maximum number of passes for the training data, a shuffle type, a regularization type, a learning rate, and a regularization amount. A default setting may be specified with the option of adjusting the values to fine tune the performance.

In at least one embodiment, the maximum model size is the total size of the patterns created during the model training process, in bytes. In at least one embodiment, a model having a specified size, such as a 100MB model, may be created by default. If the training manager cannot determine enough patterns to fill a model size, a smaller model may be created. If the training manager finds more patterns than fit in a specified size, a maximum cutoff can be enforced by tailoring the patterns that have the least impact on the quality of the learning model. Selecting the model size provides control over the trade-off between the prediction quality and the cost of use of the model. In at least one embodiment, a smaller model may cause the training manager to remove many patterns to fit within the maximum size limit, thereby affecting the quality of the prediction. In at least one embodiment, a larger model may take more time to query for real-time predictions. In at least one embodiment, a larger input data set does not necessarily result in a larger model because the model stores patterns rather than input data. In at least one embodiment, if the patterns are few and simple, the resulting model will be small. Input data with a large number of original attributes (input columns) or derived features (output of data transformations) may have more patterns found and stored in a training process.

In at least one embodiment, training manager 704 may make multiple deliveries (passes) or iterations of training data in an attempt to discover patterns. In at least one embodiment, there may be a default number of deliveries, such as ten deliveries, while in at least one embodiment, a maximum number of deliveries may be set, such as up to one hundred deliveries. In at least one embodiment, there may not be a maximum set, or there may be a convergence criterion or other set of factors that would trigger the training process to end. In at least one embodiment, the training manager 704 can monitor the quality of the pattern (e.g., model convergence) during training and can automatically stop training when no more data points or patterns need to be found. In at least one embodiment, a dataset with only a few observations may require more delivered data to achieve a sufficiently high model quality. A larger data set may contain many similar data points, which may reduce the need for mass delivery. One potential impact of selecting more data delivery data is that model training can take longer and cost in terms of resources and system utilization.

In at least one embodiment, the training data is shuffled prior to training or between delivery of training. In at least one embodiment, the shuffle is a random or pseudo-random shuffle to generate a true random ordering, although there may be some restrictions in place to ensure that certain types of data are not grouped, or if such a grouping exists, the shuffled data may be reshuffled, and so on. In at least one embodiment, the shuffle changes the order or arrangement in which the data is used for training so that the training algorithm does not encounter packets of similar types of data, or does not encounter a single type of data for too many consecutive observations. In at least one embodiment, a model may be trained to predict an object. In at least one embodiment, the data may be classified by object type prior to upload. In at least one embodiment, the algorithm may then process the data alphabetically by object type, first encountering only data of a certain object type. In at least one embodiment, the model will begin learning patterns for objects of that type. In at least one embodiment, the model will then only encounter data of the second object type and will attempt to adjust the model to fit that object type, which may degrade the pattern that fits the first object type. Such abrupt switching from object type to object type may result in a model that does not need to learn how to accurately predict object types. In at least one embodiment, shuffling may be performed in at least one embodiment before the training data set is partitioned into training and evaluation subsets to facilitate the use of a relatively uniform data type distribution in both stages. In at least one embodiment, the training manager 704 may automatically shuffle the data using, for example, a pseudorandom shuffling technique.

In at least one embodiment, when creating a machine learning model, training manager 704 can enable a user to specify settings or apply customization options in at least one embodiment. In at least one embodiment, a user may specify one or more evaluation settings indicating a portion of the input data to be retained for evaluating a prediction quality of the machine learning model. In at least one embodiment, the user may specify a policy for indicating which attributes and attribute transformations are available for model training. In at least one embodiment, the user may also specify different training parameters for controlling certain characteristics of the training process and the resulting model.

In at least one embodiment, once the training manager has determined that training of the model is complete, such as by using at least one final criterion discussed herein, the trained model 708 can be used by the classifier 714 to classify (or otherwise generate inferences from) the validation data 712. In at least one embodiment, this involves a logical transition between the training mode of the model and the inference mode of the model. However, in at least one embodiment, the trained model 708 will be delivered first to the evaluator 710, which 710 may comprise an application, process, or service executing on at least one computing resource (e.g., a CPU or GPU of at least one server) for evaluating the quality (or another such aspect) of the trained model. In at least one embodiment, the model is evaluated to determine whether the model provides at least a minimum acceptable or threshold level of performance in predicting targets on new and future data. If not, the training manager 704 may continue to train the model. In at least one embodiment, since future data instances typically have unknown target values, it may be desirable to check the machine-learned accuracy metrics on data for which the target answer is known, and use this evaluation as a proxy for the prediction accuracy of the future data.

In at least one embodiment, the model is evaluated using a subset of the training data 702 provided for training. The subset may be determined using a shuffling and splitting method as discussed above. In at least one embodiment, this subset of evaluation data will be marked as a target and thus may serve as a source for evaluating ground truth (groudtuth). It is not useful to evaluate the prediction accuracy of a machine learning model using the same data used for training, as a positive evaluation may be made to remember the model of the training data rather than the model summarized from it. In at least one embodiment, once training has been completed, the subset of assessment data is processed using the trained model 708, and the assessor 710 can determine the accuracy of the model by comparing the ground truth data to the corresponding output (or prediction/observation) of the model. In at least one embodiment, the evaluator 710 may, in at least one embodiment, provide a summary or performance metric indicating how well the predicted values and the actual values match. In at least one embodiment, if the trained model does not meet at least a minimum performance criterion, or other such accuracy threshold, the training manager 704 may be instructed to perform further training, or in some examples, to attempt to train a new or different model. In at least one embodiment, if the trained model 708 satisfies the correlation criteria, the trained model may be provided for use by the classifier 714.

In at least one embodiment, when creating and training a machine learning model, it may be desirable in at least one embodiment to specify model settings or training parameters in order to produce a model that is capable of making accurate predictions. In at least one embodiment, the parameters include the number of deliveries to be performed (forward and/or backward), the regularization or refinement, the model size, and the type of shuffling. In at least one embodiment, selecting the model parameter settings that yield the best predictive performance on the evaluation data may result in an overfitting of the model. In at least one embodiment, overfitting occurs when the model has memorized patterns that occurred in training and evaluating the data sources, but fails to summarize the patterns in the data. Overfitting often occurs when the training data includes all the data used in the evaluation. In at least one embodiment, a model that has been over-fit may perform well during evaluation, but may not make accurate predictions of new or other validation data. In at least one embodiment, to avoid selecting an overfitting model as the best model, the training manager may retain additional data to verify the performance of the model. For example, a training data set may be divided into 60% for training and 40% for evaluation or validation, which may be divided into two or more phases. In at least one embodiment, after selecting model parameters that work well for the evaluation data, resulting in convergence on a subset of the validation data, such as half of the validation data, a second validation may be performed with the remainder of the validation data to ensure performance of the model. If the model meets expectations on the validation data, the model is not overfitting data. In at least one embodiment, a test set or hold set may be used to test the parameters. In at least one embodiment, a second verification or testing step is used to help select the appropriate model parameters to prevent overfitting. However, more data is retained from the training process for validation, making less data available for training. This can be problematic for smaller data sets, as there may not be enough data for training. In at least one embodiment, one approach in this case is to perform cross-validation, as described elsewhere herein.

In at least one embodiment, there are a number of metrics or insights that can be used to review and evaluate the prediction accuracy of a given model. In at least one embodiment, the assessment results include a prediction accuracy metric to report the overall success of the model, and a visualization to help explore model accuracy beyond the prediction accuracy metric. The results may also provide the ability to review the impact of setting a score threshold, such as for binary classification, and may generate alerts to criteria to check the validity of the assessment. The choice of metrics and visualization may depend at least in part on the type of model being evaluated.

In at least one embodiment, once satisfactorily trained and evaluated, the trained machine learning model can be used to build or support a machine learning application. In one embodiment, building a machine learning application is an iterative process involving a sequence of steps. In at least one embodiment, a core machine learning question can be framed according to what is observed and the answer that the model is to predict. In at least one embodiment, the data may then be collected, cleaned, and prepared to make the data suitable for consumption by a machine learning model training algorithm. The data can be visualized and analyzed to run a sanity check to verify the quality of the data and understand the data. It is possible that the raw data (e.g., input variables) and answer data (e.g., targets) are not represented in a manner that can be used to train a highly predictive model. Thus, it may be desirable to construct more predictive input representations or features from the original variables. The resulting features may be fed into a learning algorithm to build the model and evaluate the quality of the model from data maintained from building the model. The model may then be used to generate a prediction of the target answer for the new data instance.

In at least one embodiment, in the system 700 shown in FIG. 7, the evaluated trained models 710 are provided to or made available to a classifier 714, where the classifier 714 is able to process validation data using the trained models. In at least one embodiment, this may include, for example, data received from users or third parties that are not classified, such as query images that are seeking information about the content represented in those images. In at least one embodiment, the validation data can be processed by the classifier using the trained model, and the resulting results 716 (e.g., classification or prediction) can be sent back to the corresponding source or otherwise processed or stored. In at least one embodiment, where such use is enabled, these now classified data instances may be stored to a training data repository, which may be used to further train the trained model 708 by a training manager. In at least one embodiment, the models will be trained continuously as new data appears, but in at least one embodiment, the models will be retrained periodically, such as once a day or once a week, depending on factors such as the size of the data set or the complexity of the models.

In at least one embodiment, the classifier 714 may include suitable hardware and software for processing the validation data 712 using the trained model. In at least one embodiment, the classifier will include one or more computer servers, each having one or more Graphics Processing Units (GPUs) capable of processing data. In at least one embodiment, the configuration and design of the GPUs may make them more suitable for processing machine learning data than CPUs or other such components. In at least one embodiment, the trained model may be loaded into GPU memory and the received data instance provided to the GPU for processing. GPUs may have a much larger number of cores than CPUs, and GPU cores may also have a smaller degree of complexity. In at least one embodiment, a given GPU may be capable of processing thousands of data instances simultaneously through different hardware threads. In at least one embodiment, the GPU may also be configured to maximize floating point throughput, which may provide significant additional processing advantages for large data sets.

In at least one embodiment, even when GPUs, accelerators, and other such hardware are used to accelerate tasks such as training models or classifying data using such models, such tasks may require significant time, resource allocation, and cost. In at least one embodiment, if the machine learning model is to be trained using 700 deliveries, and the data set includes 1,000,000 data instances to be used for training, then all million instances need to be processed in each delivery. Different portions of the architecture may also be supported by different types of devices. In at least one embodiment, the training may be performed using a set of servers at a logically centralized location, as may be provided as a service, while the classification of raw data may be performed by such a service or on a client device, among other such options. These devices may also be owned, operated or controlled by the same entity or multiple entities.

In at least one embodiment, the example neural network 800 shown in fig. 8 may be trained or otherwise used in at least one embodiment. In at least one embodiment, the statistical model is an Artificial Neural Network (ANN) that includes multiple layers of nodes, including input layer 802, output layer 806, and multiple layers of intermediate nodes 804, often referred to as "hidden" layers, because internal layers and nodes are typically not visible or accessible in the neural network. In at least one embodiment, although only a few intermediate layers are shown for purposes of illustration, it should be understood that there is no limitation on the number of intermediate layers that can be utilized, and any limitation on the layers is often a factor in the resources or time required to process using the model. In at least one embodiment, additional types of models, networks, algorithms, or processes may also be used, and other numbers or options of nodes and layers, as well as other such options, may be included. In at least one embodiment, the validation data can be processed by the layers of the network to produce a set of inference or reasoning scores, which can then be fed to the loss function 808.

In at least one embodiment, all nodes of a given tier are interconnected to all nodes of an adjacent tier. In at least one embodiment, the nodes of the middle tier will then each be connected to nodes of two adjacent tiers. In at least one embodiment, in some models, nodes are also referred to as neurons or connected units, and connections between nodes are referred to as edges. Each node may perform the received input function, such as by using a designated function. In at least one embodiment, the nodes and edges may obtain different weights during training, and the individual layers of nodes may perform certain types of transformations on received input, where those transformations may also be learned or adjusted during training. In at least one embodiment, the learning may be supervised or unsupervised learning, as may depend at least in part on the type of information contained in the training dataset. In at least one embodiment, different types of neural networks may be utilized, such as may include a Convolutional Neural Network (CNN) that includes a plurality of convolutional layers and a set of aggregation layers, and has proven beneficial for applications such as image recognition. CNNs may also be easier to train than other networks because of the relatively small number of parameters to determine.

In at least one embodiment, such a complex machine learning model may be trained using different tuning parameters. The selection of parameters, fitting of models and evaluation of models are part of the model tuning process, commonly referred to as hyper-parametric optimization. In at least one embodiment, such tuning may involve introspection of the underlying model or data. In a training or production setting, a robust workflow is important to avoid overfitting of hyper-parameters, as discussed elsewhere herein. Cross-validation and the addition of gaussian noise to the training data sets are techniques that can be used to avoid overfitting of either data set. For hyper-parametric optimization, it may be desirable to keep the training and validation sets fixed. In at least one embodiment, the hyper-parameters may be tuned in certain categories, such as may include data pre-processing (such as converting words into vectors), CNN architecture definitions (e.g., filter size, number of filters), random gradient descent (SGD) parameters (e.g., learning rate), and regularization or refinement (e.g., exit probability), among other such options.

In at least one embodiment, instances of a dataset may be embedded into a lower dimensional space of a particular size during preprocessing. In at least one embodiment, the size of this space is the parameter to be tuned. In at least one embodiment, the architecture of the CNN includes a number of tunable parameters. The filter size parameter may represent an interpretation of information corresponding to the size of the instance to be analyzed. In computational linguistics, this is referred to as n-gram size. The example CNN uses three different filter sizes, which represent potentially different n-gram sizes. Several filters per filter size may correspond to the depth of one filter. Each filter attempts to learn something different from the structure of the instance, such as a sentence structure for the text data. In convolutional layers, the activation function may be a corrective linear unit, the pooling type being set to maximum pooling. The results can then be concatenated into a single-dimensional vector and the last layer fully concatenated onto the two-dimensional output. This corresponds to the binary classification to which the optimization function can be applied. One such function is the implementation of a gradient descent Root Mean Square (RMS) propagation method, where example hyper-parameters may include learning rate, batch size, maximum gradient normal, and time period. With neural networks, regularization can be an extremely important consideration. In at least one embodiment, the input data may be relatively sparse. The main hyperparameter in this case may be a drop at the penultimate level, which represents the proportion of nodes that will not "trigger" at each training period. The example training process may suggest different hyper-parameter configurations based on previously configured performance feedback. The model may be trained, evaluated, and performance reported on a specified validation set with the proposed configuration. This process can be repeated, for example, to balance exploration (learn more about different configurations of knowledge) and development (take advantage of prior knowledge to achieve better results).

Since training CNNs can be parallelized and can leverage GPU-enabled computing resources, multiple optimization strategies can be tried for different scenarios. Complex scenarios allow tuning the model architecture and preprocessing and stochastic gradient descent parameters. This expands the model configuration space. In the basic scenario, only the preprocessing and random gradient descent parameters are tuned. In a complex scenario there may be a greater number of configuration parameters than in a basic scenario. Tuning in the joint space can be performed by iterating the model through an optimization loop using a linear or exponential number of steps. The cost of such a tuning process can be significantly less than tuning processes such as random search and grid search without any significant performance penalty.

In at least one embodiment, back propagation can be used to compute gradients used to determine weights for the neural network. Back propagation is a form of differentiation and can be used by gradient descent optimization algorithms to adjust the weights applied to individual nodes or neurons, as described above. The weight may be determined using the gradient of the correlation loss function. Back propagation may utilize the derivative of a loss function to the output produced by the statistical model. As previously described, each node may have an associated activation function to define the output of the respective node. Various activation functions may be suitably used, such as may include Radial Basis Functions (RBF) and sigmoid functions, which may be used by various Support Vector Machines (SVM) for transformation of data. The activation function of the middle tier of nodes is referred to herein as the inner product kernel. These functions may include, for example, identity functions, ladder functions, sigmoid functions, ramp functions, and the like. The activation function may be linear or non-linear, among other such options.

In at least one embodiment, the untrained neural network is trained using a training data set. In at least one embodiment, the training frame is a PyTorch frame, Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit/CNTK, MXNet, Chainer, Keras, Deechiming4j, or other training frame. In at least one embodiment, the training framework trains the untrained neural network and enables it to be trained using the processing resources described herein to generate a trained neural network. In at least one embodiment, the weights may be selected randomly or through pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

In at least one embodiment, an untrained neural network is trained using supervised learning, wherein the training data set includes inputs paired with expected outputs of the inputs, or wherein the training data set includes inputs having known outputs, and the outputs of the neural network are scored manually. In at least one embodiment, an untrained neural network is trained in a supervised manner, processing inputs from a training data set, and comparing the resulting outputs to a set of expected or expected outputs. In at least one embodiment, the error is then propagated back through the untrained neural network. In at least one embodiment, the training framework adjusts the weights that control the untrained neural network. In at least one embodiment, the training framework includes tools for monitoring how well an untrained neural network converges to a model, such as a trained neural network, that is adapted to generate correct answers, such as results, from known input data (e.g., new data). In at least one embodiment, the training framework iteratively trains the untrained neural network while adjusting the weights to refine the output of the untrained neural network using a loss function and an adjustment algorithm, such as a random gradient descent. In at least one embodiment, the training framework trains the untrained neural network until the untrained neural network reaches a desired accuracy. In at least one embodiment, the trained neural network may then be deployed to implement any number of machine learning operations.

In at least one embodiment, the untrained neural network is trained using unsupervised learning, wherein the untrained neural network attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training data set will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network may learn the groupings within the training data set and may determine how the individual inputs correlate to the untrained data set. In at least one embodiment, unsupervised training can be used to generate a self-organizing map, which is a type of neural network that is trained to perform operations useful for dimensionality reduction of new data. In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which allows for the identification of data points in the new data set that deviate from the normal pattern of the new data set.

In at least one embodiment, semi-supervised learning may be used, which is a technique that includes a mixture of labeled and unlabeled data in a training data set. In at least one embodiment, the training framework can be used to perform incremental learning, such as learning techniques through transitions. In at least one embodiment, incremental learning enables a trained neural network to adapt to new data without forgetting to instill knowledge within the network during initial training.

Inference and training logic

FIG. 9A illustrates inference and/or training logic 915 for performing inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B.

In at least one embodiment, the inference and/or training logic 915 may include, but is not limited to: code and/or data storage 901 to forward store and/or output weights and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 915 may include or be coupled to code and/or data storage 901 for storing graphics code or other software for controlling timing and/or order in which weights and/or other parameter information are to be loaded to configure logic, including integer and/or floating point units (collectively Arithmetic Logic Units (ALUs)). In at least one embodiment, weight or other parameter information is loaded into the processor ALU based on the architecture of the neural network to which the code corresponds, such as graphics code. In at least one embodiment, the code and/or data storage 901 stores weight parameters and/or input/output data for each layer of a neural network in connection with which one or more embodiments are trained or used in connection with training and/or reasoning in the forward propagation of input/output data and/or weight parameters in connection with using aspects of one or more embodiments. In at least one embodiment, any portion of the code and/or data storage 901 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, any portion of the code and/or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and/or data store 901 can be a cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, whether the code and/or data store 901 is internal or external to the processor, for example, or comprised of DRAM, SRAM, flash memory, or some other type of storage, may depend on the available memory space on-chip and off-chip, the latency requirements that training and/or reasoning functions are being performed, the batch size of the data used in reasoning and/or training for the neural network, or some combination of these factors.

In at least one embodiment, the inference and/or training logic 915 may include, but is not limited to, a code and/or data store 905 for storing and/or outputting weights and/or input/output data backwards corresponding to neurons or layers of a neural network for which inference is trained and/or used in aspects of one or more embodiments. In at least one embodiment, during training and/or reasoning using aspects of one or more embodiments, the code and/or data store 905 stores the weight parameters and/or input/output data for each layer of the neural network that is trained or used with one or more embodiments during backward propagation of the input/output data and/or weight parameters. In at least one embodiment, the training logic 915 may include or be coupled to a code and/or data store 905 for storing graphics code or other software to control timing and/or order, wherein weight and/or other parameter information is loaded to configure logic including integer and/or floating point units (collectively Arithmetic Logic Units (ALUs)). In at least one embodiment, code, such as graphical code, loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and/or data store 905 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache, or system memory. In at least one embodiment, any portion of the code and/or data storage 905 may be on or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and/or data store 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the code and/or data store 905 is a choice of whether internal or external to the processor, e.g., made up of DRAM, SRAM, flash, or some other type of storage, and may depend on the storage available on-chip and off-chip, the latency requirements of the training and/or reasoning functions being performed, the batch size of the data used in the derivation and/or training of the neural network, or some combination of these factors.

In at least one embodiment, the code and/or data store 901 and the code and/or data store 905 can be separate storage structures. In at least one embodiment, the code and/or data store 901 and the code and/or data store 905 can be the same storage structure. In at least one embodiment, the code and/or data store 901 and the code and/or data store 905 can be partially identical storage structures and partially separate storage structures. In at least one embodiment, any portion of the code and/or

data storage

901 and 905 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, the inference and/or training logic 915 may include, but is not limited to, one or more arithmetic logic units ("ALUs") 910, including integer and/or floating point units, that perform logical and/or mathematical operations based at least in part on or as directed by training and/or inference code (e.g., graphical code), the results of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation storage 920 that are a function of input/output and/or weight parameter data stored in code and/or data store 901 and/or code and/or data store 905. In at least one embodiment, in response to executing instructions or other code, the activations stored in the activation store 920 are generated according to linear algebra and/or matrix-based mathematical operations performed by the one or more ALUs 910, wherein weight values stored in the code and/or data store 905 and/or the code and/or data store 901 are used as operands, along with other values, such as bias values, gradient information, momentum values, or other parameters or hyper-parameters, any or all of which may be stored in the code and/or data store 905 or the code and/or data store 901 or other on-chip or off-chip storage.

In at least one embodiment, the one or more ALUs 910 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, the one or more ALUs 910 may be external to the processors or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, the ALUs 910 may be included within the execution unit of the processor or otherwise included within an ALU bank (bank) accessible by the execution unit of the processor, either within the same processor or distributed between different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, the code and/or data store 901, the code and/or data store 905, and the activation store 920 can be on the same processor or other hardware logic device or circuit, while in another embodiment they can be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation storage 920 may be included with other on-chip or off-chip data stores, including the L1, L2, or L3 caches of the processors or system memory. Further, the inference and/or training code may be stored with other code accessible to a processor or other hardware logic or circuitry, and may be extracted and/or processed using the extraction, decoding, scheduling, execution, retirement, and/or other logic circuitry of the processor.

In at least one embodiment, the activation store 920 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 920 may be wholly or partially withinInternal or external to one or more processors or other logic circuits. In at least one embodiment, the selection of whether activation storage 920 is internal or external to the processor, e.g., or comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip and off-chip, the latency requirements of the training and/or reasoning functions being performed, the batch size of the data used in the derivation and/or training of the neural network, or some combination of these factors. In at least one embodiment, the inference and/or training logic 915 shown in FIG. 9A can be used in conjunction with an application specific integrated circuit ("ASIC"), such as from Google

Processing unit from Graphcore^TMOr from the Intel corporation

(e.g., "Lake Crest") processor. In at least one embodiment, the inference and/or training logic 915 shown in fig. 9A may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware, such as a field programmable gate array ("FPGA").

FIG. 9B illustrates inference and/or training logic 915 in accordance with at least one embodiment. In at least one embodiment, the inference and/or training logic 915 may include, but is not limited to, hardware logic, wherein computing resources are dedicated or otherwise used exclusively in conjunction with weight values or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, the inference and/or training logic 915 shown in FIG. 9B can be used in conjunction with an Application Specific Integrated Circuit (ASIC), such as from Google

Processing units, Inference Processing Units (IPUs) from Graphcore (TM) or from Intel corporation

(e.g., "Lake Crest") processor. In at least one embodiment, the inference and/or training logic 915 shown in fig. 9B may be used in conjunction with Central Processing Unit (CPU) hardware, Graphics Processing Unit (GPU) hardware, or other hardware such as a Field Programmable Gate Array (FPGA). In at least one embodiment, the inference and/or training logic 915 includes, but is not limited to, a code and/or data store 901 and a code and/or data store 905 that can be used to store code (e.g., graphical code), weight values, and/or other information, including bias values, gradient information, momentum values, and/or other parameter or hyper-parameter information. In at least one embodiment illustrated in FIG. 9B, each of the code and/or data store 901 and the code and/or data store 905 is associated with a dedicated computing resource, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, each of the computing hardware 902 and the computing hardware 906 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, on information stored in the code and/or data store 901 and the code and/or data store 905, the results of performing the mathematical functions being stored in the activation store 920.

In at least one embodiment, each of the code and/or

data store

901 and 905 and the

corresponding computing hardware

902 and 906, respectively, correspond to a different layer of the neural network, such that activation resulting from one "store/compute pair 901/902" of the code and/or data store 901 and computing hardware 902 is provided as input to the "store/compute pair 905/906" of the code and/or data store 905 and computing hardware 906 to reflect the conceptual organization of the neural network. In at least one embodiment, each of the storage/computation pairs 901/902 and 905/906 may correspond to more than one neural network layer. In at least one embodiment, additional storage/computation pairs (not shown) subsequent to or in parallel with storage computation pairs 901/902 and 905/906 may be included in inference and/or training logic 915.

Data center

FIG. 10 illustrates an example data center 1000 that can employ at least one embodiment. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

In at least one embodiment, as shown in fig. 10, the data center infrastructure layer 1010 can include a resource coordinator 1012, packet computing resources 1014, and node computing resources ("node c.r.") 1016(1) -1016(N), where "N" represents any positive integer. In at least one embodiment, nodes c.r.1016(1) -1016(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, Field Programmable Gate Arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read only memories), storage devices (e.g., solid state disks or disk drives), network input/output ("NW I/O") devices, network switches, virtual machines ("VMs"), power supply modules, and cooling modules, etc. In at least one embodiment, one or more of the nodes c.r.1016(1) -1016(N) may be a server having one or more of the above-described computing resources.

In at least one embodiment, the grouped computing resources 1014 may comprise a single group of nodes c.r. housed within one or more racks (not shown), or a number of racks housed within a data center at various geographic locations (also not shown). Individual groupings of node c.r. within the grouped computing resources 1014 may include computing, network, memory, or storage resources that may be configured or allocated as a group to support one or more workloads. In at least one embodiment, several nodes c.r. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches, in any combination.

In at least one embodiment, the resource coordinator 1012 may configure or otherwise control one or more nodes c.r.1016(1) -1016(N) and/or grouped computing resources 1014. In at least one embodiment, the resource coordinator 1012 may include a software design infrastructure ("SDI") management entity for the data center 1000. In at least one embodiment, the resource coordinator may comprise hardware, software, or some combination thereof.

In at least one embodiment, as shown in FIG. 10, framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, framework layer 1020 can include a framework that supports software 1032 of software layer 1030 and/or one or more applications 1042 of application layer 1040. In at least one embodiment, software 1032 or application 1042 may comprise a Web-based service software or application, respectively, such as Services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020 can be, but is not limited to, a free and open source software web application framework, such as an Apache Spark that can utilize distributed file system 1028 for large-scale data processing (e.g., "big data")^TM(hereinafter referred to as "Spark"). In at least one embodiment, job scheduler 1032 may include a Spark driver to facilitate scheduling workloads supported by various tiers of data center 1000. In at least one embodiment, the configuration manager 1024 may be capable of configuring different layers, such as a software layer 1030 and a framework layer 1020 including Spark and a distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, resource manager 1026 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 1028 and job scheduler 1022. In at least one embodiment, the clustered or grouped computing resources may comprise grouped computing resources 1014 on the data center infrastructure layer 1010. In at least one embodiment, the resource manager 1026 may coordinate with the resource coordinator 1012 to manage these mapped or allocated computing resources.

In at least one embodiment, the software 1032 included in the software layer 1030 may include software used by at least a portion of the nodes c.r.1016(1) -1016(N), the grouped computing resources 1014, and/or the distributed file system 1028 of the framework layer 1020. The one or more types of software may include, but are not limited to, Internet web searching software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, one or more application programs 1042 included in the application layer 1040 can include one or more types of application programs used by at least a portion of the nodes c.r.1016(1) -1016(N), the packet computing resources 1014, and/or the distributed file system 1028 of the framework layer 1020. The one or more types of applications can include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or reasoning software, machine learning framework software (e.g., PyTorch, tensrfow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

In at least one embodiment, any of configuration manager 1024, resource manager 1026, and resource coordinator 1012 may implement any number and type of self-modifying actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying action may mitigate a data center operator of the data center 1000 from making configuration decisions that may not be good and may avoid underutilization and/or poorly performing portions of the data center.

In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train or use one or more machine learning models to predict or infer information in accordance with one or more embodiments described herein. For example, in at least one embodiment, the machine learning model may be trained by computing weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1000. In at least one embodiment, using the weight parameters calculated through one or more training techniques described herein, the information can be inferred or predicted using the trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1000.

In at least one embodiment, the data center may use a CPU, Application Specific Integrated Circuit (ASIC), GPU, FPGA, or other hardware to perform training and/or reasoning using the above resources. Further, one or more of the software and/or hardware resources described above may be configured as a service to allow a user to train or perform information reasoning, such as image recognition, voice recognition, or other artificial intelligence services.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in connection with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be employed in system fig. 10 to infer or predict operations based, at least in part, on the use of neural network training operations, neural network functions and/or architectures, or weight parameters computed using neural network cases as described herein.

In at least one embodiment, these components may be used to generate enhanced video using one or more neural networks, such as for generating higher frame rate video from frames of lower frame rate video.

Computer system

FIG. 11 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system on a chip (SOC), or some combination thereof, formed with a processor that may include execution units to execute instructions, according to at least one embodiment. In at least one embodiment, in accordance with the present disclosure, such as the embodiments described herein, the computer system 1100 may include, but is not limited to, a component, such as a processor 1102, whose execution unit includes logic to execute an algorithm for process data. In at least one embodiment, the computer system 1100 may include a processor, such as that available from Intel Corporation of Santa Clara, Calif

Processor family, Xeon^TM、

XScale^TMAnd/or StrongARM^TM，

Core^TMOr

Nervana^TMA microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash, although other operating systems (e.g., UNIX and Linux), embedded software, and/or graphical user interfaces may also be used.

Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions in accordance with at least one embodiment.

In at least one embodiment, the computer system 1100 may include, but is not limited to, a processor 1102, which processor 1102 may include, but is not limited to, one or more execution units 1108 to perform machine learning model training and/or reasoning in accordance with the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 may be a multi-processor system. In at least one embodiment, the processor 1102 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110, and the processor bus 1110 may transmit data signals between the processor 1102 and other components in the computer system 1100.

In at least one embodiment, the processor 1102 may include, but is not limited to, a level 1 ("L1") internal cache ("cache") 1104. In at least one embodiment, the processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 1102. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and instruction pointer registers.

In at least one embodiment, an execution unit 1108, including but not limited to logic to perform integer and floating point operations, is also located in the processor 1102. In at least one embodiment, the processor 1102 may also include microcode ("ucode") read only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic to process packaged instruction set 1109. In at least one embodiment, the encapsulated data in the general purpose processor 1102 can be used to perform operations used by many multimedia applications by including the encapsulated instruction set 1109 in the instruction set of the general purpose processor 1102 and the associated circuitry to execute the instructions. In one or more embodiments, many multimedia applications may be accelerated and more efficiently executed by performing operations on encapsulated data using the full width of the processor's data bus, which may not require transferring smaller units of data over the processor's data bus to perform one or more operations of one data element at a time.

In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 1100 can include, but is not limited to, memory 1120. In at least one embodiment, the memory 1120 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, the memory 1120 may store instructions 1119 and/or data 1121 represented by data signals that may be executed by the processor 1102.

In at least one embodiment, a system logic chip may be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 1116, and the processor 1102 may communicate with the MCH 1116 via a processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high bandwidth memory path 1118 to the memory 1120 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may enable data signals between the processor 1102, the memory 1120, and other components in the computer system 1100, and bridge the data signals between the processor bus 1110, the memory 1120, and the system I/O1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to memory 1120 via a high bandwidth memory path 1118, and the Graphics/video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (AGP) interconnect 1114.

In at least one embodiment, the computer system 1100 may couple the MCH 1116 to an I/O controller hub ("ICH") 1130 using the system I/O1122 as a proprietary hub interface bus. In at least one embodiment, the ICH 1130 may provide direct connectivity to certain I/O devices through a local I/O bus. In at least one embodiment, the local I/O bus may include, but is not limited to, a high speed I/O bus for connecting peripheral devices to the memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub ("Flash BIOS") 1128, a wireless transceiver 1126, a data store 1124, a conventional I/O controller 1123 containing user input and a keyboard interface, a serial expansion port 1127 (e.g., Universal Serial Bus (USB)), and a network controller 1134. Data storage 1124 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

In at least one embodiment, fig. 11 shows a system including interconnected hardware devices or "chips," while in other embodiments, fig. 11 may show an exemplary system on a chip ("SoC"). In at least one embodiment, the devices may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using a compute express link (CXL) interconnect.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in connection with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in the system of fig. 11 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

Fig. 12 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a telephone, an embedded computer, or any other suitable electronic device.

In at least one embodiment, system 1200 can include, but is not limited to, a processor 1210 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a Low Pin Count (LPC) bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (

versions

1, 2, 3), or a universal asynchronous receiver/transmitter ("UART") bus. In at least one embodiment, fig. 12 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, fig. 12 may illustrate an exemplary system on a chip ("SoC"). In at least one embodiment, the devices shown in figure 12 may be interconnected with a proprietary interconnect line, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of fig. 12 are interconnected using computational fast link (CXL) interconnect lines.

In at least one embodiment, fig. 12 may include a display 1224, a touchscreen 1225, a touch pad 1230, a near field communication unit ("NFC") 1245, a sensor hub 1240, a thermal sensor 1246, an express chipset ("EC") 1235, a trusted platform module ("TPM") 1238, a BIOS/firmware/Flash memory ("BIOS, FW Flash") 1222, a DSP1260, a drive 1220 (e.g., a solid state disk ("SSD") or a hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 1250, a bluetooth unit 1252, a wireless wide area network unit ("WWAN") 1256, a Global Positioning System (GPS)1255, a camera ("USB 3.0 camera") 1254 (e.g., a USB 3.0 camera), and/or a low power consumption double data rate ("LPDDR") memory unit ("LPDDR 3") 1215 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

In at least one embodiment, other components may be communicatively coupled to the processor 1210 via the components described above. In at least one embodiment, an accelerometer 1241, an ambient light sensor ("ALS") 1242, a compass 1243, and a gyroscope 1244 can be communicatively coupled to the sensor hub 1240. In at least one embodiment, thermal sensors 1239, fan 1237, keyboard 1246, and touch pad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, a speaker 1263, an earphone 1264, and a microphone ("mic") 1265 can be communicatively coupled to an audio unit ("audio codec and class-D amplifier") 1262, which in turn can be communicatively coupled to the DSP 1260. In at least one embodiment, audio unit 1264 may include, for example, but not limited to, an audio coder/decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250 and bluetooth unit 1252 and WWAN unit 1256 may be implemented as Next Generation Form Factor (NGFF).

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in connection with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in system fig. 12 to infer or predict operations based, at least in part, on weight parameters computed using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

Fig. 13 illustrates a computer system 1300 in accordance with at least one embodiment. In at least one embodiment, computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit ("CPU") 1302, the central processing unit ("CPU") 1302 being connected to a communication bus 1310 implemented using any suitable protocol, such as PCI ("peripheral component interconnect"), peripheral component interconnect Express ("PCI-Express"), AGP ("accelerated graphics port"), hypertransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1300 includes, but is not limited to, a main memory 1304 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1304 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1322 provides an interface to other computing devices and networks, for receiving data from computer system 1300 and transmitting data to other systems.

In at least one embodiment, computer system 1300, in at least one embodiment, includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is received from an input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in connection with fig. 9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in system fig. 13 to perform inference or predictive operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

FIG. 14 illustrates a computer system 1400 in accordance with at least one embodiment. In at least one embodiment, computer system 1400 includes, but is not limited to, a computer 1410 and a USB disk 1420. In at least one embodiment, the computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

In at least one embodiment, USB disk 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing cores 1430 may include, but are not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1430 includes an application specific integrated circuit ("ASIC") optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1430 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1430 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

In at least one embodiment, the USB interface 1440 may be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0Type-C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0Type-A connector. In at least one embodiment, USB interface logic 1450 may include any number and type of logic to enable processing unit 1430 to connect with a device (e.g., computer 1410) via USB connector 1440.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in connection with fig. 9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in system diagram 14 to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

FIG. 15A illustrates an exemplary architecture in which multiple GPUs 1510-1513 are communicatively coupled to multiple multi-core processors 1505-1506 via high-speed links 1540-1543 (e.g., bus/point-to-point interconnect, etc.). In at least one embodiment, high speed link 1540 1543 supports communication throughputs of 4GB/s, 30GB/s, 80GB/s or higher. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

Further, in one embodiment, two or more GPUs 1510-. Similarly, two or more multi-core processors 1505-1506 may be connected by a high-speed link 1528, which may be a symmetric multi-processor (SMP) bus operating at 20GB/s, 30GB/s, 120GB/s, or higher. Alternatively, all communications between the various system components shown in fig. 15A may be accomplished using the same protocol/link (e.g., over a common interconnect fabric).

In one embodiment, each multi-core processor 1505-. Memory interconnects 1526-. By way of example and not limitation, processor memory 1501-1502 and GPU memory 1520-1523 may be volatile memory, such as Dynamic Random Access Memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM), and/or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portions of processor memory 1501-1502 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

As described below, although the various processors 1505-1506 and GPUs 1510-1513 may be physically coupled to particular memories 1501-1502, 1520-1523, respectively, a unified memory architecture may be implemented in which virtual system address spaces (also referred to as "effective address" spaces) are distributed among the various physical memories. For example, the

processor memories

1501 and 1502 may each include 64GB of system memory address space, and the

GPU memories

1520 and 1523 may each include 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

FIG. 15B illustrates additional details for the interconnection between the multicore processor 1507 and graphics acceleration module 1546 according to an example embodiment. Graphics acceleration module 1546 may include one or more GPU chips integrated on a linecard coupled to processor 1507 via high-speed link 1540. Alternatively, graphics acceleration module 1546 may be integrated on the same package or chip as processor 1507.

In at least one embodiment, the illustrated processor 1507 includes a plurality of cores 1560A-1560D, each having a translation look-aside buffer 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components not shown for executing instructions and processing data. Caches 1562A-1562D may include level 1(L1) and level 2(L2) caches. Further, one or more shared caches 1556 may be included in caches 1562A-1562D and shared by groups of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1507 and graphics acceleration module 1546 are coupled to the system memory 1514, which may include the processor memory 1501-1502 of FIG. 15A.

Coherency is maintained for data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 via inter-core communications over a coherency bus 1564. For example, each cache may have cache coherency logic/circuitry associated with it to communicate over coherency bus 1564 in response to detecting a read or write to a particular cache line. In one implementation, a cache snoop protocol is implemented over coherency bus 1564 to snoop (snoop) cache accesses.

In one embodiment, proxy circuit 1525 communicatively couples graphics acceleration module 1546 to coherency bus 1564, allowing graphics acceleration module 1546 to participate in a cache coherency protocol as a peer of cores 1560A-1560D. In particular, interface 1535 provides a connection to proxy circuit 1525 through a high-speed link 1540 (e.g., PCIe bus, NVlink, etc.), and interface 1537 connects graphics acceleration module 1546 to link 1540.

In one implementation, accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services on behalf of multiple

graphics processing engines

1531, 1532, N of the graphics acceleration module. In at least one embodiment, the

graphics processing engines

1531, 1532, N may each include a separate Graphics Processing Unit (GPU). Optionally,

graphics processing engines

1531, 1532, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1546 may be a GPU with multiple graphics processing engines 1531-1532, N, or the graphics processing engines 1531-1532, N may be individual GPUs integrated on a general purpose package, line card, or chip.

In one embodiment, accelerator integrated circuit 1536 includes a Memory Management Unit (MMU)1539 to perform various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes memory access protocols for accessing system memory 1514. The MMU 1539 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual/valid to physical/real address translations. In one implementation, the cache 1538 stores commands and data for efficient access by the

graphics processing engine

1531 and 1532, N. In one embodiment, the data stored in cache 1538 and graphics memory 1533-1534, M is coherent with core caches 1562A-1562D, 1556 and system memory 1514. As described above, this task may be accomplished via proxy circuitry 1525 on behalf of caches 1538 and graphics memories 1533-1534, M (e.g., sending updates to caches 1538 regarding modification/access of cache lines on processor caches 1562A-1562D, 1556, and receiving updates from caches 1538).

A set of registers 1545 store context data for threads executed by the graphics processing engine 1531-1532, N, and context management circuitry 1548 manages thread contexts. For example, the context management circuitry 1548 may perform save and restore operations to save and restore the context of the respective thread during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread may be executed by the graphics processing engine). For example, context management circuitry 1548 may store the current register value to a designated region in memory (e.g., identified by a context pointer) upon a context switch. The register values may then be restored when the context is returned. In one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

In one implementation, MMU 1539 translates virtual/effective addresses from graphics processing engine 1531 to real/physical addresses in system memory 1514. One embodiment of accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and/or other accelerator devices. The graphics accelerator module 1546 may be dedicated to a single application executing on the processor 1507, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of graphics processing engine 1531-1532, N are shared with multiple applications or Virtual Machines (VMs). In at least one embodiment, resources may be subdivided into "slices" that are assigned to different VMs and/or applications based on processing requirements and priorities associated with the VMs and/or applications.

In at least one embodiment, accelerator integrated circuit 1536 executes as a bridge to the system of graphics acceleration module 1546 and provides address translation and system memory cache services. In addition, accelerator integrated circuit 1536 may provide a virtualization facility for the host processor to manage virtualization, interrupts, and memory management of

graphics processing engine

1531 and 1532, N.

Since the hardware resources of graphics processing engine 1531-1532, N are explicitly mapped to the real address space seen by host processor 1507, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1536 is to physically separate the graphics processing engines 1531-1532, N so that they appear to the system as independent units.

In at least one embodiment, one or more graphics memories 1533-1534, M are coupled to each graphics processing engine 1531-1532, N, respectively. The graphics memory 1533-1534, M stores instructions and data that are processed by each graphics processing engine 1531-1532, N. Graphics memory 1533-1534, M may be a volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and/or may be a non-volatile memory such as 3D XPoint or Nano-Ram.

In one embodiment, to reduce data traffic on link 1540, biasing techniques are used to ensure that the data stored in graphics memory 1533-1534, M is the data most frequently used by graphics processing engines 1531-1532, N, and preferably not used (at least infrequently used) by cores 1560A-1560D. Similarly, the biasing mechanism attempts to maintain the data required by the cores (and preferably not the graphics processing engines 1531-1532, N) in the cores' caches 1562A-1562D, 1556 and system memory 1514.

Fig. 15C shows another example embodiment where accelerator integrated circuit 1536 is integrated within processor 1507. In at least this embodiment, graphics processing engines 1531-1532, N communicate directly with accelerator integrated circuit 1536 over high speed link 1540 via interface 1537 and interface 1535 (again, any form of bus or interface protocol may be utilized). Accelerator integrated circuit 1536 may perform the same operations as described with respect to fig. 15B. But may have higher throughput due to its close proximity to coherency bus 1564 and caches 1562A-1562D, 1556. At least one embodiment supports different programming models, including a dedicated process programming model (no graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1536 and a programming model controlled by graphics acceleration module 1546.

In at least one embodiment, the graphics processing engines 1531-1532, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can aggregate (channel) other application requests to the graphics processing engine 1531-1532, N, thereby providing virtualization within VMs/partitions.

In at least one embodiment, graphics processing engines 1531-1532, N may be shared by multiple VM/application partitions. In at least one embodiment, the shared model may use a hypervisor to virtualize the graphics processing engines 1531-1532, N to allow access by each operating system. For a single partition system without a hypervisor, the operating system has graphics processing engines 1531-1532, N. In at least one embodiment, the operating system may virtualize 1532, N the graphics processing engine 1531 to provide access to each process or application.

In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engine 1531-1532, N uses the process handle to select a process element. In at least one embodiment, the process elements are stored in system memory 1514 and may be addressed using effective to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process (i.e., invoking system software to add a process element to the linked list of process elements) when its context is registered with the graphics processing engine 1531-1532, N. In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the linked list of process elements.

Fig. 15D illustrates an exemplary accelerator integration slice 1590. As used herein, a "slice" includes a designated portion of the processing resources of accelerator integrated circuit 1536. The application is an effective address space 1582 in system memory 1514, which stores process elements 1583. In one embodiment, the process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on the processor 1507. The process element 1583 contains the process state of the corresponding application 1580. The Work Descriptor (WD)1584 included in the process element 1583 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, WD 1584 is a pointer to a queue of job requests in the application's address space 1582.

The graphics acceleration module 1546 and/or the respective graphics processing engines 1531-1532, N may be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting a process state and sending WD 1584 to graphics acceleration module 1546 to begin a job in a virtualized environment may be included.

In at least one embodiment, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 1546 or the individual graphics processing engine 1531. Because graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuits for the owned partitions, and when graphics acceleration module 1546 is dispatched, the operating system initializes accelerator integrated circuits 1536 for the owned processes.

In operation, the WD fetch unit 1591 in the accelerator integration slice 1590 fetches the next WD 1584, which includes an indication of the work to be done by one or more graphics processing engines of the graphics acceleration module 1546. Data from WD 1584 may be stored in registers 1545 and used by MMU 1539, interrupt management circuitry 1547, and/or context management circuitry 1548, as shown. For example, one embodiment of MMU 1539 includes segment/page roaming circuitry for accessing segment/page tables 1586 within OS virtual address space 1585. Interrupt management circuitry 1547 may process interrupt events 1592 received from graphics acceleration module 1546. When performing graphics operations, effective addresses 1593 generated by graphics processing engine 1531-1532, N are translated to real addresses by MMU 1539.

In one embodiment, registers 1545 are duplicated for each graphics processing engine 1531-1532, N and/or graphics acceleration module 1546, and the same set of registers 1545 can be initialized by a hypervisor or operating system. Each of these replicated registers may be included in accelerator integration slice 1590. Exemplary registers that may be initialized by the hypervisor are shown in table 1.

TABLE 1 hypervisor initialized registers

Exemplary registers that may be initialized by the operating system are shown in table 2.

TABLE 2 registers for operating System initialization

1	Process and thread identification
		2	Effective Address (EA) context save/restore pointer
3	Virtual Address (VA) accelerator utilization record pointer
		4	Virtual Address (VA) storage segment table pointer
5	Authority masking
		6	Work descriptor

In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and/or graphics processing engine 1531-1532, N. It contains all the information needed by the graphics processing engine 1531-1532, N to complete the work, or it may be a pointer to a memory location where the application has set up the command queue for the work to be completed.

FIG. 15E illustrates additional details of one exemplary embodiment of a sharing model. This embodiment includes a hypervisor real address space 1598 in which a process element list 1599 is stored. The hypervisor real address space 1598 may be accessed via the hypervisor 1596, which hypervisor 1596 virtualizes the graphics acceleration module engine for the operating system 1595.

In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use graphics acceleration module 1546. There are two programming models in which graphics acceleration module 1546 is shared by multiple processes and partitions, time-slice sharing, and graphics-oriented sharing.

In this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. For graphics acceleration module 1546 to support virtualization through hypervisor 1596, graphics acceleration module 1546 may follow the following specifications, 1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or graphics acceleration module 1546 must provide a context save and restore mechanism, 2) graphics acceleration module 1546 ensures that the application's job requests are completed within a specified amount of time, including any translation errors, or graphics acceleration module 1546 provides the ability to preempt job processing, 3) when operating in a directed sharing programming model, fairness between graphics acceleration module 1546 processes must be ensured.

In at least one embodiment, the application 1580 is required to make operating system 1595 system calls using the graphics acceleration module 1546 type, the job descriptor (WD), the privilege mask register (AMR) value, and the context save/restore area pointer (CSRP). In at least one embodiment, graphics acceleration module 1546 type describes a target acceleration function for system calls. In at least one embodiment, the graphics acceleration module type may be a system specific value. In at least one embodiment, WD is specially formatted for graphics acceleration module 1546 and may take the form of graphics acceleration module 1546 commands, effective address pointers to user-defined structures, effective address pointers to command queues, or any other data structure describing the work to be done by graphics acceleration module 1546. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the values passed to the operating system are similar to the application setting AMR. If the implementation of accelerator integrated circuit 1536 and graphics acceleration module 1546 does not support a User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing AMR in the hypervisor call. The hypervisor 1596 may selectively apply the current permission mask override register (AMOR) value before placing AMR into the process element 1583. In at least one embodiment, CSRP is one of the registers 1545 that contains the effective addresses of regions in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. This pointer is optional if there is no need to save state between jobs or when a job is preempted. In at least one embodiment, the context save/restore area may be a fixed system memory.

Upon receiving the system call, the operating system 1595 may verify that the application 1580 has registered and been granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 uses the information shown in table 3 to invoke the hypervisor 1596.

TABLE 3 operating System to hypervisor Call parameters

Until a hypervisor call is received, the hypervisor 1596 verifies that the operating system 1595 is registered and granted permission to use the graphics acceleration module 1546. The hypervisor 1596 then places the process element 1583 into a linked list of process elements of the corresponding graphics acceleration module 1546 type. The process elements may include the information shown in table 4.

Table 4-Process element information

In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1590 registers 1545.

As shown in FIG. 15F, in at least one embodiment, unified memory is used that is addressable via a common virtual memory address space for accessing

physical processor memory

1501 and 1502 and

GPU memory

1520 and 1523. In this implementation, the operations performed on GPUs 1510-1513 utilize the same virtual/effective memory address space to access processor memory 1501-1502 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual/effective address space is allocated to processor memory 1501, a second portion is allocated to second processor memory 1502, a third portion is allocated to GPU memory 1520, and so on. In at least one embodiment, the entire virtual/effective memory space (sometimes referred to as the effective address space) is thus distributed in each of the

processor memory

1501 and 1502 and the

GPU memory

1520 and 1523, allowing any processor or GPU to access that memory using virtual addresses mapped to any physical memory.

In one embodiment, bias/coherency management circuits 1594A-1594E within one or more MMUs 1539A-1539E ensure cache coherency between one or more host processors (e.g., 1505) and the caches of GPU 1510-1513 and implement biasing techniques that indicate the physical memory in which certain types of data should be stored. Although multiple instances of the bias/coherency management circuits 1594A-1594E are shown in FIG. 15F, the bias/coherency circuits may be implemented within the MMU of the one or more host processors 1505 and/or within the accelerator integrated circuit 1536.

One embodiment allows the GPU

additional memory

1520 and 1523 to be mapped as part of the system memory and accessed using Shared Virtual Memory (SVM) techniques, but without suffering performance drawbacks associated with full system cache coherency. In at least one embodiment, the ability to access the GPU

additional memory

1520 and 1523 as system memory without the heavy cache coherency overhead provides an advantageous operating environment for GPU offloading. This arrangement allows the software of host processor 1505 to set operands and access computational results without the overhead of traditional I/O DMA data copying. Such traditional copies include driver calls, interrupts, and memory mapped I/o (mmio) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU

additional memory

1520 and 1523 without cache coherency overhead may be critical to the execution time of the offloaded computations. For example, with a large amount of streaming write memory traffic, the cache coherency overhead can significantly reduce the effective write bandwidth seen by GPU 1510. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computations may play a role in determining the effectiveness of GPU offload.

In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, an offset table may be used, which may be a page granularity structure (i.e., controlled at the granularity of memory pages) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the offset tables may be implemented in stolen memory ranges of one or more GPU

additional memories

1520 and 1523, with or without an offset cache (e.g., a frequently/recently used entry for caching offset tables) in

GPU

1510 and 1513. Alternatively, the entire bias table may be maintained within the GPU.

In at least one embodiment, the offset table entry associated with each access to the GPU

additional memory

1520 and 1523 is accessed prior to actually accessing the GPU memory, resulting in the following operations. First, local requests from the

GPUs

1510 and 1513 to find their pages in GPU offsets are forwarded directly to the corresponding

GPU memories

1520 and 1523. Local requests from the GPU to find their pages in the host bias are forwarded to processor 1505 (e.g., over the high speed link described above). In one embodiment, a request from processor 1505 to find the requested page in the host processor offset completes a request similar to a normal memory read. Alternatively, the request to point to the GPU offset page may be forwarded to GPU 1510-1513. In at least one embodiment, if the GPU is not currently using the page, the GPU may then migrate the page to the host processor offset. In at least one embodiment, the bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or in limited cases by a purely hardware-based mechanism.

One mechanism for changing the bias state employs an API call (e.g., OpenCL) that subsequently calls the GPU's device driver, which then sends a message (or enqueues a command descriptor) to the GPU, directs the GPU to change the bias state, and in some migrations, performs a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migration from host processor 1505 bias to GPU bias, but not for the reverse migration.

In one embodiment, cache coherency is maintained by temporarily rendering GPU offset pages that host processor 1505 cannot cache. To access these pages, processor 1505 may request access from GPU 1510, and GPU 1510 may or may not immediately grant access. Thus, to reduce communication between processor 1505 and GPU 1510, it is beneficial to ensure that the GPU offset pages are pages required by the GPU rather than pages required by host processor 1505, and vice versa.

Inference and/or training logic 915 is employed to perform one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B.

Fig. 16 illustrates an example integrated circuit and associated graphics processor that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

Fig. 16 is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be fabricated using one or more IP cores in accordance with at least one embodiment. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, andan image processor 1615 and/or a video processor 1620 may additionally be included, either of which may be a modular IP core. In at least one embodiment, integrated circuit 1600 includes peripheral or bus logic including USB controller 1625, UART controller 1630, SPI/SDIO controller 1635, and I ²S/I²C controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by flash subsystem 1660, including flash memory and a flash controller. In at least one embodiment, a memory interface may be provided via memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in integrated circuit 1600 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

17A-17B illustrate an example integrated circuit and associated graphics processor that can be fabricated using one or more IP cores, in accordance with various embodiments described herein. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

17A-17B are block diagrams illustrating exemplary graphics processors for use within a SoC according to embodiments described herein. Fig. 17A illustrates an example graphics processor 1710 of a system on a chip integrated circuit, which can be fabricated using one or more IP cores, according to at least one embodiment. Fig. 17B illustrates a further exemplary graphics processor 1740 of a system on a chip integrated circuit, which may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1710 of FIG. 17A is a low power graphics processor core. In at least one embodiment, graphics processor 1740 of FIG. 17B is a higher performance graphics processor core. In at least one embodiment, each

graphics processor

1710, 1740 can be a variation of graphics processor 1610 of fig. 16.

In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D through 1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 may execute different shader programs via separate logic, such that vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, vertex processor 1705 performs the vertex processing stages of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, one or more of the fragment processors 1715A-1715N generate a frame buffer for display on a display device using the primitives and vertex data generated by the vertex processor 1705. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGLAPI, which may be used to perform operations similar to the pixel shader programs provided in the Direct 3 DAPI.

In at least one embodiment, graphics processor 1710 additionally includes one or more Memory Management Units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual to physical address mapping for graphics processor 1710, including for vertex processor 1705 and/or fragment processors 1715A-1715N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more of MMUs 1720A-1720B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1605, image processors 1615, and/or video processors 1620 of fig. 16, such that each

processor

1605 and 1620 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to connect with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

In at least one embodiment, graphics processor 1740 includes one or more MMUs 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B of graphics processor 1710 of FIG. 17A. In at least one embodiment, graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F through 1755N-1, and 1755N) that provide a unified shader core architecture in which a single core or type or core may execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, the plurality of shader cores may vary. In at least one embodiment, graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1755A-1755N and a blocking unit 1758 to accelerate block operations based on tile rendering in which rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize the use of internal caches.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in integrated circuit fig. 17A and/or 17B to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases as described herein.

18A-18B illustrate additional exemplary graphics processor logic, according to embodiments described herein. In at least one embodiment, FIG. 18A illustrates a graphics core 1800 that may be included within graphics processor 1610 of FIG. 16, and in at least one embodiment, may be a unified shader core 1755A-1755N as shown in FIG. 17B. Fig. 18B illustrates a highly parallel general purpose graphics processing unit 1830 suitable for deployment on a multi-chip module in at least one embodiment.

In at least one embodiment, graphics core 1800 includes shared instruction cache 1802, texture unit 1818, and cache/shared memory 1817, which are common to the execution resources within graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions per core, and the graphics processor may include multiple instances of the graphics core 1800. The slices 1801A-1801N may include support logic including a local instruction cache 1804A-1804N, a thread scheduler 1806A-1806N, a thread dispatcher 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, the slices 1801A-1801N may include a set of additional functional units (AFU 1812A-1812N), floating point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double precision floating point units (DPFPU 1815A-1815N), and matrix processing units (MPU 1817A-1817N).

In at least one embodiment, the FPUs 1814A-1814N may perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1815A-1815N perform double-precision (64-bit) floating-point operation-point operations. In at least one embodiment, the ALUs 1816A-1816N may perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision, and may be configured as mixed precision operations. In at least one embodiment, the MPUs 1817A-1817N may also be configured for mixed precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N may perform various matrix operations to accelerate the machine learning application framework, including generic matrix-to-matrix multiplication (GEMM) to enable support for acceleration. In at least one embodiment, AFUs 1812A-1812N can perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided herein in connection with fig. 9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics core 1800 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

FIG. 18B illustrates, in at least one embodiment, a general purpose processing unit (GPGPU)1830 that can be configured to enable highly parallel computing operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1830 may be directly linked to other instances of the GPGPU 1830 to create multiple GPU clusters to increase training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 to enable connection with a host processor. In at least one embodiment, host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor specific communication interface or communication structure. In at least one embodiment, the GPGPU 1830 receives commands from a host processor and uses the global scheduler 1834 to assign execution threads associated with those commands to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share cache memory 1838. In at least one embodiment, the cache memory 1838 may be used as a higher level cache for cache memory within the compute clusters 1836A-1836H.

In at least one embodiment, GPGPU 1830 includes memories 1844A-1844B, which memories 1844A-1844B are coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memories 1844A-1844B may include various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), which includes Graphics Double Data Rate (GDDR) memory.

In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as graphics core 1800 of FIG. 18A, which may include various types of integer and floating point logic that may perform compute operations on various ranges of computer precision, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each compute cluster 1836A-1836H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

In at least one embodiment, multiple instances of GPGPU 1830 may be configured to function as a compute cluster. In at least one embodiment, the communication used by compute clusters 1836A-1836H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1830 communicate through the host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I/O hub 1839 that couples the GPGPU 1830 with a GPU link 1840 to enable direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGP 1830. In at least one embodiment, GPU link 1840 is coupled with a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1830 are located in a single data processing system and communicate through network devices accessible through the host interface 1832. In at least one embodiment, GPU link 1840 may be configured to enable connection to a host processor in addition to, or instead of, host interface 1832.

In at least one embodiment, the GPGPU 1830 may be configured to train a neural network. In at least one embodiment, a GPGPU 1830 may be used within the inference platform. In at least one embodiment, where the GPGPU 1830 is used for reasoning, the GPGPU 1830 may include fewer compute clusters 1836A-1836H relative to when the neural network is trained using the GPGPU. In at least one embodiment, the memory technology associated with memories 1844A-1844B may differ between inference and training configurations, with higher bandwidth memory technologies dedicated to training configurations. In at least one embodiment, the inference configuration of the GPGPU may support inference specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot-product instructions that can be used during the inference operations of the deployed neural network.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in GPGPU 1830 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

FIG. 19 illustrates a block diagram of a computer system 1900 in accordance with at least one embodiment. In at least one embodiment, the computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904, the system memory 1904 communicating via an interconnection path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within the chipset component or may be integrated within the one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled with the I/O subsystem 1911 by a communication link 1906. In one embodiment, the I/O subsystem 1911 includes an I/O hub 1907 that may enable the computer system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I/O hub 1907 may cause a display controller, which may be included in the one or more processors 1902, to provide output to one or more display devices 1910A. In at least one embodiment, the one or more display devices 1910A coupled with the I/O hub 1907 may include local, internal, or embedded display devices.

In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to a memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any of a number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1912 form a compute-centric parallel or vector processing system that may include a large number of processing cores and/or processing clusters, such as Multiple Integrated Core (MIC) processors. In at least one embodiment, the one or more parallel processors 1912 form a graphics processing subsystem that can output pixels to one of the one or more display devices 1910A coupled via the I/O hub 1907. In at least one embodiment, the one or more parallel processors 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B.

In at least one embodiment, a system memory unit 1914 may be connected to the I/O hub 1907 to provide a storage mechanism for the computer system 1900. In at least one embodiment, the I/O switch 1916 may be used to provide an interface mechanism to enable connections between the I/O hub 1907 and other components, such as a network adapter 1918 and/or a wireless network adapter 1919, which may be integrated into the platform, as well as various other devices that may be added via one or more additional devices 1920. In at least one embodiment, the network adapter 1918 can be an ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more of Wi-Fi, bluetooth, Near Field Communication (NFC), or other network devices including one or more radios.

In at least one embodiment, computer system 1900 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I/O hub 1907. In at least one embodiment, the communication paths interconnecting the various components in FIG. 19, such as the NV-Link high speed interconnect or interconnect protocol, may be implemented using any suitable protocol, such as a PCI (peripheral component interconnect) -based protocol (e.g., PCI-Express) or other bus or point-to-point communication interfaces and/or protocols.

In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a Graphics Processing Unit (GPU). In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general purpose processing. In at least one embodiment, components of computer system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more of the parallel processor 1912, the memory hub 1905, the processor 1902, and the I/O hub 1907 may be integrated into a system on a chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 1900 may be integrated into a single package to form a System In Package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1900 may be integrated into a multi-chip module (MCM) that may be interconnected with other multi-chip modules into a modular computer system.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in connection with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be employed in the system 1900 of fig. 19 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

Processor with a memory having a plurality of memory cells

FIG. 20A illustrates a parallel processor 2000 in accordance with at least one embodiment. In at least one embodiment, the various components of parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). In at least one embodiment, the illustrated parallel processor 2000 is a variation of one or more of the parallel processors 1912 illustrated in FIG. 19 in accordance with the illustrative embodiments.

In at least one embodiment, parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I/O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, the I/O unit 2004 can be directly connected to other devices. In at least one embodiment, the I/O unit 2004 connects with other devices using a hub or switch interface (e.g., memory hub 1905). In at least one embodiment, the connection between the memory hub 1905 and the I/O unit 2004 forms a communication link 1913. In at least one embodiment, the I/O unit 2004 is connected with a host interface 2006 and a memory crossbar 2016 where the host interface 2006 receives commands for performing processing operations and the memory crossbar 2016 receives commands for performing memory operations.

In at least one embodiment, when the host interface 2006 receives command buffers via the I/O unit 2004, the host interface 2006 can direct work operations to execute those commands to the front end 2008. In at least one embodiment, front end 2008 is coupled with a scheduler 2010, scheduler 2010 configured to assign commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in an active state before tasks are assigned to processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2010 may be configured to perform complex scheduling and work allocation operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2012. In at least one embodiment, the host software may certify a workload for scheduling on the processing array 2012 through one of a plurality of graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on processing array 2012 by scheduler 2010 logic within the microcontroller that includes scheduler 2010.

In at least one embodiment, processing cluster array 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing cluster array 2012 may execute a number of concurrent threads. In at least one embodiment, scheduler 2010 may assign jobs to clusters 2014A-2014N of processing cluster array 2012 using various scheduling and/or job assignment algorithms, which may vary depending on the workload generated by each program or computing type. In at least one embodiment, scheduling may be dynamically handled by scheduler 2010, or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 may be allocated for processing different types of programs or for performing different types of computations.

In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic to perform processing tasks including filtering of video and/or audio data, performing modeling operations including physical operations and performing data transformations.

In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the performance of such graphics processing operations including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2012 may be configured to execute shader programs related to graphics processing such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2002 may transfer data from system memory for processing via I/O unit 2004. In at least one embodiment, during processing, the transferred data may be stored to an on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory during processing.

In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into approximately equal sized tasks to better allocate graphics processing operations to the multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2014A-2014N may be stored in a buffer to allow the intermediate data to be transferred between clusters 2014A-2014N for further processing.

In at least one embodiment, processing cluster array 2012 may receive processing tasks to be executed via scheduler 2010, which scheduler 2010 receives commands defining processing tasks from front end 2008. In at least one embodiment, a processing task may include an index of data to be processed, e.g., surface (patch) data, raw data, vertex data, and/or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to obtain an index corresponding to a task or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to an active state prior to launching a workload specified by an incoming command buffer (e.g., batch-buffer, push buffer, etc.).

In at least one embodiment, each of the one or more instances of parallel processing unit 2002 can be coupled with a parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar 2016, which memory crossbar 2016 may receive memory requests from the processing cluster array 2012 and the I/O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 may include a plurality of partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N) that may each be coupled to a portion (e.g., a memory unit) of parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to equal the number of memory units such that a first partition unit 2020A has a corresponding first memory unit 2024A, a second partition unit 2020B has a corresponding memory unit 2024B, and an Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not equal the number of memory devices.

In at least one embodiment, memory units 2024A-2024N may include various types of memory devices including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In at least one embodiment, memory units 2024A-2024N may also include 3D stacked memory, including but not limited to High Bandwidth Memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

In at least one embodiment, any of the clusters 2014A-2014N of the processing cluster array 2012 may process data to be written to any of the memory units 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 may be configured to transfer the output of each cluster 2014A-2014N to any partition unit 2020A-2020N or another cluster 2014A-2014N on which the clusters 2014A-2014N may perform other processing operations. In at least one embodiment, each cluster 2014A-2014N may communicate with memory interface 2018 through memory crossbar 2016 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 2016 has connections to memory interfaces 2018 to communicate with I/O unit 2004, and connections to local instances of parallel processor memory 2022 to allow processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar 2016 may use virtual lanes to separate traffic flows between the clusters 2014A-2014N and the partition units 2020A-2020N.

In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 may be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and/or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include a higher precision floating point unit relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to a desktop, laptop or handheld personal computer, server, workstation, gaming console, and/or embedded system.

Fig. 20B is a block diagram of a partition unit 2020, according to at least one embodiment. In at least one embodiment, partition unit 2020 is an example of one of partition units 2020A-2020N of FIG. 20A. In at least one embodiment, partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a raster operations unit ("ROP") 2026. The L2 cache 2021 is a read/write cache configured to perform load and store operations received from the memory crossbar 2016 and ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent writeback requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates may also be sent to a frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 interacts with one of the memory units in parallel processor memory, such as memory units 2024A-2024N of FIG. 20A (e.g., within parallel processor memory 2022).

In at least one embodiment, the ROP 2026 is a processing unit that performs raster operations, such as stencil, z-test, blending, and the like. In at least one embodiment, the ROP 2026 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a plurality of compression algorithms. The compression logic performed by the ROP 2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per tile basis.

In at least one embodiment, the ROP 2026 is included within each processing cluster (e.g., clusters 2014A-2014N of FIG. 20A) rather than within partition unit 2020. In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 2016 instead of pixel fragment data. In at least one embodiment, the processed graphics data may be displayed on a display device (such as one of one or more display devices 2210 of fig. 22), routed for further processing by processor 2202, or routed for further processing by one of the processing entities within parallel processor 2000 of fig. 20A.

Figure 20C is a block diagram of a processing cluster 2014 within a parallel processing unit in accordance with at least one embodiment. In at least one embodiment, a processing cluster is an example of one of processing clusters 2014A-2014N of FIG. 20A. In at least one embodiment, one or more processing clusters 2014 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multi-threading (SIMT) techniques are used to support parallel execution of a large number of generally simultaneous threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

In at least one embodiment, the operation of the processing cluster 2014 may be controlled by a pipeline manager 2032 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of FIG. 20A, and manages the execution of those instructions by the graphics multiprocessor 2034 and/or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an illustrative example of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within processing cluster 2014. In at least one embodiment, one or more instances of a graphics multiprocessor 2034 may be included within processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and the data crossbar 2040 may be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar 2040.

In at least one embodiment, each graphics multiprocessor 2034 within processing cluster 2014 can include the same set of function execution logic (e.g., arithmetic logic unit, load store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, wherein a new instruction may be issued before a previous instruction completes. In at least one embodiment, the function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shifting, and computation of various algebraic functions. In at least one embodiment, different operations may be performed by the same functional unit hardware, and any combination of functional units may be present.

In at least one embodiment, instructions delivered to processing clusters 2014 constitute threads. In at least one embodiment, the set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute programs on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the plurality of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during a cycle in which the thread group is being processed. In at least one embodiment, the thread group may also include more threads than multiple processing engines within the graphics multiprocessor 2034. In at least one embodiment, processing may be performed in consecutive clock cycles when the thread group includes more threads than the processing engines within the graphics multiprocessor 2034. In at least one embodiment, multiple thread groups may be executing simultaneously on the graphics multiprocessor 2034.

In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2034 may forego internal caching and use cache memory within processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access an L2 cache within partition units (e.g., partition units 2020A-2020N of FIG. 20A) that are shared among all processing clusters 2014 and that may be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 may also access an off-chip global memory, which may include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit 2002 may be used as global memory. In at least one embodiment, processing cluster 2014 includes multiple instances of graphics multiprocessor 2034, which may share common instructions and data that may be stored in L1 cache 2048.

In at least one embodiment, each processing cluster 2014 may include a memory management unit ("MMU") 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside within memory interface 2018 of fig. 20A. In at least one embodiment, the MMU 2045 includes a set of Page Table Entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address Translation Lookaside Buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034 or L1 cache or processing cluster 2014. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

In at least one embodiment, the processing clusters 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to data crossbar 2040 to provide processed tasks to another processing cluster 2014 for further processing or to store processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2016. In at least one embodiment, a PROP 2042 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 2034, direct the data to a ROP unit, which may be located with partition units described herein (e.g., partition units 2020A-2020N of FIG. 20A). In at least one embodiment, the PROP 2042 unit may perform optimizations for color mixing, organize pixel color data, and perform address translation.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics processing cluster 2014 to perform inference or predictive operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and/or architectural or neural network use cases described herein.

Fig. 20D illustrates a graphics multiprocessor 2034, in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled to the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has execution pipelines including, but not limited to, an instruction cache 2052, instruction units 2054, an address mapping unit 2056, register files 2058, one or more General Purpose Graphics Processing Unit (GPGPU) cores 2062, and one or more load/store units 2066. One or more GPGPU cores 2062 and one or more load/store units 2066 are coupled with the cache memory 2072 and the shared memory 2070 by a memory and cache interconnect 2068.

In at least one embodiment, the instruction cache 2052 receives a stream of instructions to be executed from the pipeline manager 2032. In at least one embodiment, instructions are cached in the instruction cache 2052 and dispatched for execution by the instruction unit 2054. In one embodiment, the instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles) with each thread of a thread group assigned to a different execution unit within the GPGPU core 2062. In at least one embodiment, an instruction may access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2056 may be used to translate addresses in a unified address space to different memory addresses that may be accessed by the load/store unit 2066.

In at least one embodiment, the register file 2058 provides a set of registers for the functional units of the graphics multiprocessor 2034. In at least one embodiment, the register file 2058 provides temporary storage for operands connected to the datapath of the functional units of the graphics multiprocessor 2034 (e.g., the GPGPU core 2062, the load/store unit 2066). In at least one embodiment, register file 2058 is divided among each functional unit such that a dedicated portion of register file 2058 is allocated for each functional unit. In at least one embodiment, the register file 2058 is divided between different thread bundles being executed by the graphics multiprocessor 2034.

In at least one embodiment, the GPGPU cores 2062 may each include a Floating Point Unit (FPU) and/or an integer Arithmetic Logic Unit (ALU) for executing instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be similar in architecture or may differ in architecture. The first portion of the GPGPU core 2062 includes single precision FPUs and integer ALUs, while the second portion of the GPGPU core includes double precision FPUs. In at least one embodiment, the FPU may implement the IEEE 754-. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special function logic.

In at least one embodiment, GPGPU core 2062 comprises SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 2062 may physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for a GPGPU core may be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2034 to a register file 2058 and to a shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that allows the load/store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, register file 2058 may operate at the same frequency as GPGPU core 2062, so that the latency of data transfers between GPGPU core 2062 and register file 2058 is very low. In at least one embodiment, the shared memory 2070 may be used to enable communication between threads executing on functional units within the graphics multiprocessor 2034. In at least one embodiment, cache memory 2072 may serve as, for example, a data cache to cache texture data communicated between the functional units and texture units 2036. In at least one embodiment, shared memory 2070 may also serve as a cache for program management. In at least one embodiment, threads executing on GPGPU core 2062 may programmatically store data in shared memory in addition to automatically cached data stored in cache memory 2072.

In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General Purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor/core via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core through an internal processor bus/interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands/instructions contained in a work descriptor. In at least one embodiment, the GPU then uses special-purpose circuitry/logic to efficiently process these commands/instructions.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in the graphics multiprocessor 2034 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and/or architectures or neural network use cases described herein.

FIG. 21 illustrates a multi-GPU computing system 11100 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 11100 can include a processor 11102 coupled to a plurality of General Purpose Graphics Processing Units (GPGPUs) 11106A-D via a host interface switch 11104. In at least one embodiment, host interface switch 11104 is a PCI Express switch device that couples processor 11102 to a PCI Express bus through which processor 11102 may communicate with GPGPGPUs 11106A-D. GPGPUs 11106A-D may be interconnected via a set of high speed P2P GPU-to-GPU links 11116. In at least one embodiment, GPU-to-GPU link 11116 connects to each of GPGPUs 11106A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 11116 enables direct communication between each GPGPU 11106A-D without communicating through the host interface bus 11104 to which the processor 11102 is connected. In at least one embodiment, where GPU-to-GPU traffic is directed to P2P GPU link 11116, host interface bus 11104 remains available for system memory access or communication with other instances of multi-GPU computing system 11100, e.g., via one or more network devices. While in at least one embodiment, GPGPGPUs 11106A-D are connected to processor 11102 via host interface switch 11104, in at least one embodiment, processor 11102 includes direct support for P2P GPU link 11116 and may be directly connected to GPGPUs 11106A-D.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in multi-GPU computing system 11100 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and/or architecture or neural network use cases described herein.

FIG. 22 is a block diagram of a graphics processor 2200 in accordance with at least one embodiment. In at least one embodiment, graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A-2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, including other graphics processors or one or more general purpose processor cores. In at least one embodiment, graphics processor 2200 is one of many processors integrated within a multi-core processing system.

In at least one embodiment, the graphics processor 2200 receives multiple batches of commands via the ring interconnect 2202. In at least one embodiment, the incoming commands are interpreted by a command streamer (streamer)2203 in the pipeline front end 2204. In at least one embodiment, graphics processor 2200 includes extensible execution logic to perform 3D geometry processing and media processing via graphics cores 2280A-2280N. In at least one embodiment, for 3D geometry processing commands, command streamer 2203 provides the commands to geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, command streamer 2203 provides the commands to a video front end 2234, which is coupled to a media engine 2237. In at least one embodiment, the media engine 2237 includes a Video Quality Engine (VQE)2230 for video and image post-processing, and a multi-format encode/decode (MFX)2233 engine for providing hardware accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by the at least one graphics core 2280A.

In at least one embodiment, graphics processor 2200 includes extensible thread execution resources with (healing) module cores 2280A-2280N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2250A-2250N, 2260A-2260N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2200 may have any number of graphics cores 2280A-2280N. In at least one embodiment, graphics processor 2200 includes a graphics core 2280A having at least a first sub-core 2250A and a second sub-core 2260A. In at least one embodiment, graphics processor 2200 is a low power processor with a single sub-core (e.g., 2250A). In at least one embodiment, graphics processor 2200 includes a plurality of graphics cores 2280A-2280N, each graphics core including a set of first sub-cores 2250A-2250N and a set of second sub-cores 2260A-2260N. In at least one embodiment, each of the first sub-cores 2250A-2250N includes at least a first group of execution units 2252A-2252N and media/texture samplers 2254A-2254N. In at least one embodiment, each of the second sub-cores 2260A-2260N includes at least a second set of execution units 2262A-2262N and samplers 2264A-2264N. In at least one embodiment, each child core 2250A-2250N, 2260A-2260N shares a set of shared resources 2270A-2270N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics processor 2200 to perform inference or predictive operations based at least in part on weight parameters computed using neural network training operations, neural network functions, and/or architectures or neural network use cases described herein.

Fig. 23 is a block diagram illustrating a micro-architecture for a processor 2300 that may include logic circuitry to execute instructions, according to at least one embodiment. In at least one embodiment, processor 2300 can execute instructions including x86 instructions, ARM instructions, application specific instructions for an Application Specific Integrated Circuit (ASIC), and the like. In at least one embodiment, processor 2300 may include registers for storing package data, such as a 64-bit wide MMX in a microprocessor enabled with MMX technology by Intel corporation of Santa Clara, Calif ^TMA register. In at least one embodiment, MMX registers available in integer and floating point form may be run with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher version (commonly referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, processor 2300 may execute instructions to accelerate a machineLearning or deep learning algorithms, training or reasoning.

In at least one embodiment, processor 2300 includes an in-order front end ("front end") 2301 to fetch instructions to be executed and prepare the instructions for later use in a processor pipeline. In at least one embodiment, front end 2301 may include several units. In at least one embodiment, the instruction prefetcher 2323 fetches instructions from memory and provides the instructions to the instruction decoder 2328, which in turn decodes or interprets the instructions by the instruction decoder 2328. For example, in at least one embodiment, the instruction decoder 2328 decodes the received instructions into one or more operations that the machine may perform, so-called "micro-instructions" or "micro-operations" (also referred to as "micro-operations" or "micro-instructions"). In at least one embodiment, the instruction decoder 2328 parses the instruction into an opcode and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, the trace cache 2330 may assemble decoded microinstructions into program ordered sequences or traces in the microinstruction queue 2334 for execution. In at least one embodiment, microcode ROM 2332 provides the microinstructions needed to complete an operation when complex instructions are encountered by trace cache 2330.

In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four microinstructions are needed to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, instructions may be decoded into a small number of microinstructions for processing at the instruction decoder 2328. In at least one embodiment, if multiple microinstructions are needed to complete the operation, the instructions may be stored in microcode ROM 2332. In at least one embodiment, the trace cache 2330 references entry point programmable logic arrays ("PLAs") to determine the correct micro-instruction pointers for reading micro-code sequences from the micro-code ROM 2332 to complete one or more instructions in accordance with at least one embodiment. In at least one embodiment, the front end 2301 of the machine may resume fetching micro-operations from the trace cache 2330 after the microcode ROM 2332 completes ordering the micro-operations for the instruction.

In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2303 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the stream of instructions to optimize performance as instructions descend down the pipeline and are scheduled to execute. In at least one embodiment, the out-of-order execution engine 2303 includes, but is not limited to, a dispatcher/register renamer 2340, a memory micro-instruction queue 2342, an integer/floating-point micro-instruction queue 2344, a memory scheduler 2346, a fast scheduler 2302, a slow/general floating-point scheduler ("slow/general FP scheduler") 2304, and a simple floating-point scheduler ("simple FP scheduler") 2306. In at least one embodiment, the fast scheduler 2302, the slow/general floating point scheduler 2304, and the simple floating point scheduler 2306 are also collectively referred to as "

microinstruction schedulers

2302, 2304, 2306". In at least one embodiment, allocator/register renamer 2340 allocates the machine buffers and resources required for execution of each microinstruction in sequence. In at least one embodiment, allocator/register renamer 2340 renames logical registers to entries in a register file. In at least one embodiment, the allocator/register renamer 2340 also allocates an entry for each of the microinstructions in one of two microinstruction queues, a memory microinstruction queue 2342 for memory operations and an integer/floating point microinstruction queue 2344 for non-memory operations, ahead of the memory scheduler 2346 and the

microinstruction schedulers

2302, 2304, 2306. In at least one embodiment, the

microinstruction schedulers

2302, 2304, 2306 determine when a microinstruction is ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resource microinstructions that need to be completed. The fast scheduler 2302 for at least one embodiment may schedule on each half of the main clock cycle, while the slow/general floating point scheduler 2304 and the simple floating point scheduler 2306 may schedule once per main processor clock cycle. In at least one embodiment, the

uop schedulers

2302, 2304, 2306 arbitrate among the scheduling ports to schedule uops for execution.

In at least one embodiment, the execution blocks 2311 include, but are not limited to, an integer register file/bypass network 2308, a floating point register file/bypass network ("FP register file/bypass network") 2310, address generation units ("AGUs") 2312 and 2314, fast arithmetic logic units ("fast ALUs") 2316 and 2318, slow arithmetic logic units ("slow ALUs") 2320, floating point ALUs ("FP") 2322, and floating point move units ("FP move") 2324. In at least one embodiment, integer register file/bypass network 2308 and floating point register file/bypass network 2310 are also referred to herein as "

register files

2308, 2310". In at least one embodiment, the

AGUs

2312 and 2314, the

fast ALUs

2316 and 2318, the slow ALU 2320, the floating point ALU 2322, and the floating point move unit 2324 are also referred to herein as "

execution units

2312, 2314, 2316, 2318, 2320, 2322, and 2324". In at least one embodiment, execution block 2311 may include, but is not limited to, any number (including zeros) and type of register files, bypass networks, address generation units, and execution units (in any combination).

In at least one embodiment, register

files

2308, 2310 may be disposed between

microinstruction schedulers

2302, 2304, 2306 and

execution units

2312, 2314, 2316, 2318, 2320, 2322 and 2324. In at least one embodiment, integer register file/branch network 2308 performs integer operations. In at least one embodiment, the floating point register file/branch network 2310 performs floating point operations. In at least one embodiment, each of

register files

2308, 2310 may include, but is not limited to, a bypass network that may bypass or forward just completed results that have not been written to the register file to a new dependent object. In at least one embodiment, register

files

2308, 2310 may communicate data with each other. In at least one embodiment, integer register file/bypass network 2308 may include, but is not limited to, two separate register files, one register file for the lower-order 32-bit data and a second register file for the higher-order 32-bit data. In at least one embodiment, the floating point register file/branch network 2310 may include, but is not limited to, 128 bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits in width.

In at least one embodiment, the

execution units

2312, 2314, 2316, 2318, 2320, 2322, 2324 may execute instructions. In at least one embodiment, register

files

2308, 2310 store integer and floating point data operand values that the microinstructions need to execute. In at least one embodiment, processor 2300 may include, but is not limited to, any number and combination of

execution units

2312, 2314, 2316, 2318, 2320, 2322, 2324. In at least one embodiment, the floating-point ALU 2322 and the floating-point mobile unit 2324 may perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2322 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform divide, square root, and remainder micro-operations. In at least one embodiment, instructions involving floating point values may be processed with floating point hardware. In at least one embodiment, the ALU operations may be passed to the

fast ALUs

2316, 2318. In at least one embodiment, the

fast ALUs

2316, 2318 may perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter the slow ALU 2320, as the slow ALU 2320 may include, but is not limited to, integer execution hardware for long latency type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be performed by the

AGUs

2312, 2314. In at least one embodiment, the fast ALU 2316, the fast ALU 2318, and the slow ALU 2320 may perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2316, the fast ALU 2318, and the slow ALU 2320 may be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, and so on. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating-point ALU 2322 and floating-point move unit 2324 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, the

microinstruction schedulers

2302, 2304, 2306 schedule dependent operations before the parent load completes execution. In at least one embodiment, processor 2300 may also include logic to handle memory misses because microinstructions may be speculatively scheduled and executed in processor 2300. In at least one embodiment, if a data load in the data cache misses, there may be dependent operations running in the pipeline that cause the scheduler to temporarily miss the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations may need to be replayed and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture a sequence of instructions for a text string comparison operation.

In at least one embodiment, the term "register" may refer to an on-board processor storage location that may be used as part of an instruction to identify operands. In at least one embodiment, the registers may be those that can be used from outside the processor (from the programmer's perspective). In at least one embodiment, the registers may not be limited to a particular type of circuitry. Rather, in at least one embodiment, the registers may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within a processor using a number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, a combination of dedicated and dynamically allocated physical registers, and so forth. In at least one embodiment, the integer register stores 32 bits of integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, part or all of the inference and/or training logic 915 may be incorporated into the execution block 2311 as well as other memories or registers, shown or not shown. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs shown in execution block 2311. Further, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of execution block 2311 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Fig. 24 illustrates a deep learning application processor 2400 in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2400 uses instructions that, if executed by the deep learning application processor 2400, cause the deep learning application processor 2400 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor 2400 is an Application Specific Integrated Circuit (ASIC). In at least one embodiment, the application processor 2400 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, deep learning application processor 2400 includes, but is not limited to, processing clusters 2410(1) -2410(12), inter-chip link ("ICL") 2420(1) -2420(12), inter-chip controller ("ICC") 2430(1) -2430(2), memory controller ("memstrlr") 2442(1) -2442(4), high bandwidth memory physical layer ("HBM PHY") 2444(1) -2444(4), a management controller central processing unit ("management controller CPU") 2450, a serial peripheral device interface, an inter-integrated circuit and general purpose input/output block ("SPI, I2C, GPIO"), a peripheral component interconnect Express controller and direct memory access block ("PCIe controller and DMA") 2470, and a sixteen channel peripheral component interconnect Express port ("PCI Express x 16") 2480.

In at least one embodiment, processing cluster 2410 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated by one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2410 may include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2400 can include any number and type of processing clusters 2400. In at least one embodiment, the inter-chip link 2420 is bi-directional. In at least one embodiment, the inter-chip link 2420 and the inter-chip controller 2430 enable the plurality of deep learning application processors 2400 to exchange information, including activation information resulting from execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2400 can include any number (including zero) and type of ICLs 2420 and ICC 2430.

In at least one embodiment, HBM22440 provides a total of 32GB of memory. HBM22440 (i) is associated with both memory controller 2442(i) and HBM PHY 2444 (i). In at least one embodiment, any number of HBMs 22440 may provide any type and amount of high bandwidth memory and may be associated with any number (including zero) and type of memory controllers 2442 and HBM PHYs 2444. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2460, and DMA 2470 and/or PCIe2480 may be replaced with any number and type of blocks, implementing any number and type of communication standards in any technically feasible manner.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, the deep learning application processor 2400 is configured to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2400. In at least one embodiment, the deep learning application processor 2400 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2400. In at least one embodiment, processor 2400 can be configured to perform one or more neural network use cases described herein.

Fig. 25 is a block diagram of a neuromorphic processor 2500 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2500 may receive one or more inputs from a source external to the neuromorphic processor 2500. In at least one embodiment, these inputs may be transmitted to one or more neurons 2502 within neuromorphic processor 2500. In at least one embodiment, neuron 2502 and its components can be implemented using circuitry or logic comprising one or more Arithmetic Logic Units (ALUs). In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, examples of thousands of neurons 2502, although any suitable number of neurons 2502 may be used. In at least one embodiment, each instance of neuron 2502 can include a neuron input 2504 and a neuron output 2506. In at least one embodiment, the neuron 2502 can generate an output that can be transmitted to an input of other instances of the neuron 2502. In at least one embodiment, the neuron input 2504 and the neuron output 2506 may be interconnected via a synapse 2508.

In at least one embodiment, the neurons 2502 and synapses 2508 may be interconnected such that the neuromorphic processor 2500 operates to process or analyze information received by the neuromorphic processor 2500. In at least one embodiment, the neuron 2502 can send an output pulse (or "trigger" or "peak") when an input received through the neuron input 2504 exceeds a threshold. In at least one embodiment, the neuron 2502 can sum or integrate signals received at a neuron input 2504. For example, in at least one embodiment, neuron 2502 can be implemented as a leaky integrate-and-trigger neuron, wherein if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 2502 can use a transfer function, such as a sigmoid or threshold function, to produce an output (or "trigger"). In at least one embodiment, a leaky integrate-and-trigger neuron can sum signals received at neuron input 2504 to a membrane potential, and can apply a program decay factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaky integrate-trigger neuron may trigger if multiple input signals are received at neuron input 2504 that are fast enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2502 can be implemented using circuitry or logic that receives an input, integrates the input to a membrane potential, and attenuates the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 2502 may include, but is not limited to, a comparator circuit or logic that produces an output spike at neuron output 2506 when the result of applying a transfer function to neuron input 2504 exceeds a threshold. In at least one embodiment, once neuron 2502 triggers, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 2502 can resume normal operation after a suitable period of time (or repair period).

In at least one embodiment, the neurons 2502 can be interconnected by synapses 2508. In at least one embodiment, the synapse 2508 may be operable to transmit a signal from an output of the first neuron 2502 to an input of the second neuron 2502. In at least one embodiment, the neuron 2502 can transmit information on more than one instance of synapse 2508. In at least one embodiment, one or more instances of a neuron output 2506 can be connected to an instance of a neuron input 2504 in the same neuron 2502 by an instance of a synapse 2508. In at least one embodiment, the instance of the neuron 2502 that produces an output to be transmitted on the instance of the synapse 2508 relative to that instance of the synapse 2508 may be referred to as a "pre-synaptic neuron". In at least one embodiment, an instance of a neuron 2502 receiving an input transmitted by an instance of a synapse 2508 may be referred to as a "post-synaptic neuron," with respect to the instance of the synapse 2508. In at least one embodiment, with respect to various instances of synapses 2508, a single instance of a neuron 2502 may be both a "pre-synaptic neuron" and a "post-synaptic neuron" in that an instance of the neuron 2502 may receive input from one or more instances of synapses 2508, and may also transmit output through one or more instances of synapses 2508.

In at least one embodiment, neurons 2502 can be organized into one or more layers. Each instance of a neuron 2502 can have a neuron output 2506, which neuron output 2506 can fan out to one or more neuron inputs 2504 through one or more synapses 2508. In at least one embodiment, a neuron output 2506 of a neuron 2502 in the first layer 2510 can be connected to a neuron input 2504 of a neuron 2502 in the second layer 2512. In at least one embodiment, layer 2510 can be referred to as a "feed-forward layer". In at least one embodiment, each instance of a neuron 2502 in an instance of a first layer 2510 can fan out to each instance of a neuron 2502 in a second layer 2512. In at least one embodiment, the first layer 2510 can be referred to as a "fully connected feed forward layer". In at least one embodiment, each instance of neurons 2502 in each instance of the second layer 2512 fans out to less than all instances of neurons 2502 in the third layer 2514. In at least one embodiment, the second layer 2512 can be referred to as a "sparsely connected feed forward layer". In at least one embodiment, the neurons 2502 in the second layer 2512 can fan out to neurons 2502 in a plurality of other layers, including to neurons 2502 in the (same) second layer 2512. In at least one embodiment, the second layer 2512 can be referred to as a "periodic layer". In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, any suitable combination of periodic and feedforward layers, including, but not limited to, sparsely connected feedforward layers and fully connected feedforward layers.

In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect the synapses 2508 to the neurons 2502. In at least one embodiment, the neuromorphic processor 2500 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2502 as needed, depending on the neural network topology and neuron fan-in/fan-out. For example, in at least one embodiment, the synapses 2508 may be connected to the neurons 2502 using an interconnect structure (such as a network on a chip) or by dedicated connections. In at least one embodiment, the synaptic interconnects and their components may be implemented using circuitry or logic.

FIG. 26 illustrates a processing system in accordance with at least one embodiment. In at least one embodiment, the system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2602 or processor cores 2607. In at least one embodiment, system 2600 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

In at least one embodiment, system 2600 can comprise or be incorporated into a server-based gaming platform, a gaming console including gaming and media consoles, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, system 2600 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2600 may also include a wearable device coupled with or integrated in a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

In at least one embodiment, the one or more processors 2602 each include one or more processor cores 2607 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a particular instruction set 2609. In at least one embodiment, instruction set 2609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). In at least one embodiment, the processor cores 2607 may each process a different instruction set 2609, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, processor core 2607 may also include other processing devices, such as a Digital Signal Processor (DSP).

In at least one embodiment, the processor 2602 includes a cache memory 2604. In at least one embodiment, the processor 2602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of the processor 2602. In at least one embodiment, the processor 2602 also uses an external cache (e.g., a level three (L3) cache or a level three cache (LLC)) (not shown), which may be shared among the processor cores 2607 using known cache coherency techniques. In at least one embodiment, a register file 2606 is additionally included in the processor 2602, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2606 may include general purpose registers or other registers.

In at least one embodiment, one or more processors 2602 are coupled with one or more interface buses 2610 to transmit communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, interface bus 2610 may be a processor bus in one embodiment, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface 2610 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a platform controller hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between memory devices and other components of the processing system 2600, while the Platform Controller Hub (PCH)2630 provides a connection to input/output (I/O) devices through a local I/O bus.

In at least one embodiment, memory device 2620 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or a device with suitable capabilities for use as processor memory. In at least one embodiment, the storage device 2620 may serve as system memory for the processing system 2600 to store data 2622 and instructions 2621 for use when the one or more processors 2602 execute an application or process. In at least one embodiment, the memory controller 2616 is also coupled with an optional external graphics processor 2612, which may communicate with one or more graphics processors 2608 in the processor 2602 to perform graphics and media operations. In at least one embodiment, a display device 2611 can be connected to the processor 2602. In at least one embodiment, the display device 2611 can include one or more of internal display devices, such as in a mobile electronic device or laptop device or an external display device connected through a display interface (e.g., a DisplayPort (DisplayPort), etc.). In at least one embodiment, display device 2611 may include a Head Mounted Display (HMD), such as a stereoscopic display device used in Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In at least one embodiment, platform controller hub 2630 enables peripherals to be connected to storage 2620 and processor 2602 via a high speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller 2646, a network controller 2634, firmware interfaces 2628, a wireless transceiver 2626, a touch sensor 2625, a data storage device 2624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage devices 2624 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, touch sensor 2625 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2628 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2634 may enable network connectivity to a wired network. In at least one embodiment, a high performance network controller (not shown) is coupled to interface bus 2610. In at least one embodiment, the audio controller 2646 is a multi-channel high definition audio controller. In at least one embodiment, the processing system 2600 includes an optional legacy (legacy) I/O controller 2640 for coupling legacy (e.g., personal system 2(PS/2)) devices to the system 2600. In at least one embodiment, the platform controller hub 2630 may also be connected to one or more Universal Serial Bus (USB) controllers 2642 that connect input devices, such as a keyboard and mouse 2643 combination, a camera 2644, or other USB input devices.

In at least one embodiment, the instances of the memory controller 2616 and the platform controller hub 2630 may be integrated into a discrete external graphics processor, such as external graphics processor 2612. In at least one embodiment, the platform controller hub 2630 and/or the memory controller 2616 can be external to the one or more processors 2602. For example, in at least one embodiment, the system 2600 may include an external memory controller 2616 and a platform controller hub 2630, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset in communication with the processor 2602.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, some or all of the inference and/or training logic 915 may be incorporated into the graphics processor 2600. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs that are embodied in the graphics processor 2612. Further, in at least one embodiment, the inference and/or training operations described herein may be performed using logic other than that shown in FIG. 9A or FIG. 9B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of the graphics processor 2600 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

FIG. 27 is a block diagram of a processor 2700 having one or more processor cores 2702A-2702N, an integrated memory controller 2714 and an integrated graphics processor 2708 according to at least one embodiment. In at least one embodiment, processor 2700 may contain additional cores up to and including additional core 2702N, which is represented by the dashed box. In at least one embodiment, each processor core 2702A-2702N includes one or more internal cache units 2704A-2704N. In at least one embodiment, each processor core may also access one or more shared cache units 2706.

In at least one embodiment, internal cache units 2704A-2704N and shared cache unit 2706 represent a cache memory hierarchy within processor 2700. In at least one embodiment, the cache memory units 2704A-2704N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, where the highest level of cache prior to external memory is categorized as LLC. In at least one embodiment, cache coherency logic maintains coherency between the

various cache units

2706 and 2704A-2704N.

In at least one embodiment, the processor 2700 may also include a set of one or more bus controller units 2716 and a system agent core 2710. In at least one embodiment, one or more bus controller units 2716 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2710 provides management functions for various processor components. In at least one embodiment, the system agent core 2710 includes one or more integrated memory controllers 2714 to manage access to various external memory devices (not shown).

In at least one embodiment, one or more of the processor cores 2702A-2702N include support for simultaneous multithreading. In at least one embodiment, system proxy core 2710 includes components for coordinating and operating cores 2702A-2702N during multi-threaded processing. In at least one embodiment, system proxy core 2710 may additionally include a Power Control Unit (PCU) that includes logic and components for adjusting one or more power states of processor cores 2702A-2702N and graphics processor 2708.

In at least one embodiment, processor 2700 also includes a graphics processor 2708 to perform graph processing operations. In at least one embodiment, the graphics processor 2708 is coupled to a shared cache unit 2706 and a system agent core 2710 that includes one or more integrated memory controllers 2714. In at least one embodiment, the system agent core 2710 also includes a display controller 2711 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2711 may also be a stand-alone module coupled to graphics processor 2708 via at least one interconnect, or may be integrated within graphics processor 2708.

In at least one embodiment, ring-based interconnect unit 2712 is used to couple the internal components of processor 2700. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other techniques. In at least one embodiment, graphics processor 2708 is coupled to ring interconnect 2712 via an I/O link 2713.

In at least one embodiment, I/O link 2713 represents at least one of a variety of I/O interconnects, including packaged I/O interconnects that facilitate communication between various processor components and high performance embedded memory module 2718 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2702A-2702N and the graphics processor 2708 use the embedded memory module 2718 as a shared last level cache.

In at least one embodiment, the processor cores 2702A-2702N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2702A-2702N are heterogeneous in Instruction Set Architecture (ISA), wherein one or more processor cores 2702A-2702N execute a common instruction set and one or more other processor cores 2702A-2702N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2702A-2702N are heterogeneous in terms of microarchitecture, with one or more cores having relatively higher power consumption coupled with one or more power cores having lower power consumption. In at least one embodiment, processor 2700 may be implemented on one or more chips or as an SoC integrated circuit.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, some or all of the inference and/or training logic 915 may be incorporated into the processor 2700. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs embodied in graphics processor 2612, graphics cores 2702A-2702N, or other components in FIG. 27. Further, in at least one embodiment, the inference and/or training operations described herein may be performed using logic other than that shown in FIG. 9A or FIG. 9B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of graphics processor 2700 to perform one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

Fig. 28 is a block diagram of hardware logic of graphics processor core 2800 according to at least one embodiment described herein. In at least one embodiment, graphics processor core 2800 is included within a graphics core array. In at least one embodiment, graphics processor core 2800 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2800 is an example of one graphics core slice, and a graphics processor described herein may include multiple graphics core slices based on target power and performance context. In at least one embodiment, each graphics core 2800 may include a fixed function block 2830, also referred to as a sub-slice, that includes modules of general and fixed function logic coupled with a plurality of sub-cores 2801A-2801F.

In at least one embodiment, the fixed function block 2830 includes a geometry/fixed function pipeline 2836, e.g., in lower performance and/or lower power graphics processor implementations, the geometry/fixed function pipeline 2836 may be shared by all of the sub-cores in the graphics processor 2800. In at least one embodiment, geometry and fixed function pipeline 2836 includes a 3D fixed function pipeline, a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

In at least one embodiment that is fixed, fixed function block 2830 also includes a graphics SoC interface 2837, a graphics microcontroller 2838, and a media pipeline 2839. In at least one embodiment, fixed graphics SoC interface 2837 provides an interface between graphics core 2800 and other processor cores in the integrated circuit system on a chip. In at least one embodiment, graphics microcontroller 2838 is a programmable sub-processor that may be configured to manage various functions of graphics processor 2800, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 2839 includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing multimedia data including image and video data. In at least one embodiment, media pipeline 2839 implements media operations via requests to compute or sample logic within sub-cores 2801 and 2801F.

In at least one embodiment, the SoC interface 2837 enables the graphics core 2800 to communicate with a general-purpose application processor core (e.g., CPU) and/or other components within the SoC, including memory hierarchy elements such as a shared last level cache, system RAM, and/or embedded on-chip or packaged DRAM. In at least one embodiment, SoC interface 2837 may also enable communication with fixed-function devices (e.g., camera imaging pipelines) within the SoC, and enable use and/or implementation of global memory atoms that may be shared between graphics core 2800 and CPUs internal to the SoC. In at least one embodiment, the SoC interface 2837 may also implement power management control for the graphics core 2800 and enable interfaces between the clock domains of the graphics core 2800 and other clock domains within the SoC. In at least one embodiment, SoC interface 2837 enables receiving command buffers from the command streamer and global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2839 when a media operation is to be performed or may be distributed to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2836, geometry and fixed function pipeline 2814) when a graphics processing operation is to be performed.

In at least one embodiment, graphics microcontroller 2838 may be configured to perform various scheduling and management tasks for graphics core 2800. In at least one embodiment, the graphics microcontroller 2838 may execute graphics and/or compute workload scheduling on various graphics parallel engines within Execution Unit (EU) arrays 2802A-2802F, 2804A-2804F in the sub-cores 2801A-2801F. In at least one embodiment, host software executing on a CPU core of a SoC that includes graphics core 2800 may submit a workload of one of a plurality of graphics processor paths that invokes a scheduling operation on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload to run next, submitting the workload to a command streamer, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload completes. In at least one embodiment, graphics microcontroller 2838 may also facilitate a low power or idle state of graphics core 2800, providing graphics core 2800 with the ability to save and restore registers across low power state transitions within graphics core 2800 independent of the operating system and/or graphics driver software on the system.

In at least one embodiment, graphics core 2800 may have up to N more or fewer modular sub-cores than sub-cores 2801A-2801F are shown. For each set of N sub-cores, in at least one embodiment, graphics core 2800 may also include shared function logic 2810, shared and/or cache memory 2812, geometry/fixed function pipeline 2814, and additional fixed function logic 2816 to accelerate various graphics and computing processing operations. In at least one embodiment, shared function logic 2810 may include logic units (e.g., samplers, math and/or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2800. In at least one embodiment, the shared and/or cache memory 2812 may be a last level cache of the N sub-cores 2801A-2801F within the graphics core 2800 and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, a geometric/fixed function pipeline 2814 may be included in place of the geometric/fixed function pipeline 2836 within the fixed function block 2830 and may include the same or similar logic elements.

In at least one embodiment, graphics core 2800 includes additional fixed function logic 2816, which may include various fixed function acceleration logic for use by graphics core 2800. In at least one embodiment, the additional fixed function logic 2816 includes additional geometric pipelines for use in location-only shading. In position-only shading, there are at least two geometric pipelines, while in the full geometric pipeline and the cull pipeline within the geometric/fixed function pipelines 2816, 2836, it is an additional geometric pipeline that may be included in the additional fixed function logic 2816. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline may execute different instances of the application, each instance having a separate environment. In at least one embodiment, the location-only shading may hide long culling runs of discarded triangles so that shading may be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2816 may execute a position shader in parallel with the host application and typically generate critical results faster than a full pipeline because the culling pipeline fetches and masks the position attributes of vertices without performing rasterization and rendering pixels to a frame buffer. In at least one embodiment, the culling pipeline may use the generated critical results to calculate visibility information for all triangles regardless of whether the triangles were culled. In at least one embodiment, the full pipeline (which in this case may be referred to as a replay pipeline) may consume visibility information to skip culled triangles to mask only the visible triangles that are ultimately passed to the rasterization stage.

In at least one embodiment, the additional fixed function logic 2816 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementing optimizations including for machine learning training or reasoning.

In at least one embodiment, a set of execution resources is included within each graphics sub-core 2801A-2801F that may be used to perform graphics, media, and compute operations in response to requests by a graphics pipeline, media pipeline, or shader program. In at least one embodiment, graphics sub-cores 2801A-2801F include a plurality of EU arrays 2802A-2802F, 2804A-2804F, thread dispatch and inter-thread communication (TD/IC) logic 2803A-2803F, 3D (e.g., texture) samplers 2805A-2805F, media samplers 2806A-2806F, shader processors 2807A-2807F, and Shared Local Memory (SLM) 2808A-2808F. EU arrays 2802A-2802F, 2804A-2804F each include a plurality of execution units, which are general purpose graphics processing units capable of servicing graphics, media, or computational operations, performing floating point and integer/fixed point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD/IC logic 2803A-2803F performs local thread dispatch and thread control operations for execution units within the child cores and facilitates communication between threads executing on the execution units of the child cores. In at least one embodiment, 3D samplers 2805A-2805F may read data related to textures or other 3D graphics into memory. In at least one embodiment, the 3D sampler may read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2806A-2806F may perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2801A-2801F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2801A-2801F may utilize shared local memory 2808A-2808F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, some or all of the inference and/or training logic 915 may be incorporated into the graphics processor 2810. For example, in at least one embodiment, the training and/or reasoning techniques described herein may use one or more ALUs embodied in graphics processor 2612, graphics microcontroller 2838, geometry & fixed function pipelines 2814 and 2836, or other logic in fig. 27. Further, in at least one embodiment, the inference and/or training operations described herein may be performed using logic other than that shown in FIG. 9A or FIG. 9B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of graphics processor 2800 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

29A-29B illustrate thread execution logic 2900 including an array of processing elements of a graphics processor core, according to at least one embodiment. FIG. 29A illustrates at least one embodiment in which thread execution logic 2900 is used. FIG. 29B illustrates exemplary internal details of an execution unit in accordance with at least one embodiment.

As shown in fig. 29A, in at least one embodiment, thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable execution unit array including a plurality of execution units 2908A-2908N, a sampler 2910, a data cache 2912, and a data port 2914. In at least one embodiment, the scalable execution unit array may be dynamically scaled by enabling or disabling one or more execution units (e.g., any of

execution units

2908A, 2908B, 2908C, 2908D to 2908N-1, and 2908N), for example, based on the computational requirements of the workload. In at least one embodiment, scalable execution units are interconnected by an interconnect fabric that links to each execution unit. In at least one embodiment, the thread execution logic 2900 includes one or more connections to memory (such as system memory or cache memory) through one or more of an instruction cache 2906, a data port 2914, a sampler 2910, and execution units 2908A-2908N. In at least one embodiment, each execution unit (e.g., 2907A) is an independent programmable general purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2908A-2908N is scalable to include any number of individual execution units.

In at least one embodiment, execution units 2908A-2908N are primarily configured to execute shader programs. In at least one embodiment, shader processor 2902 may process various shader programs and dispatch threads of execution associated with the shader programs via thread dispatcher 2904. In at least one embodiment, the thread dispatcher 2904 includes logic to arbitrate thread initialization celebrations from the graphics and media pipelines and to instantiate a requested thread on one or more of the execution units 2908A-2908N. For example, in at least one embodiment, a geometry pipeline may dispatch a vertex, tessellation, or geometry shader to thread execution logic for processing. In at least one embodiment, thread dispatcher 2904 may also process runtime thread generation requests from executing shader programs.

In at least one embodiment, execution units 2908A-2908N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs in graphics libraries (e.g., Direct 3D and OpenGL) require minimal translation to execute. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general purpose processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 2908A-2908N includes one or more Arithmetic Logic Units (ALUs), is capable of multiple-issue Single Instruction Multiple Data (SIMD) execution, and multi-threaded operation enables an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issue per clock to a pipeline capable of integer, single and double precision floating point operations, SIMD branch functions, logical operations, a priori operations, and other operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within execution units 2908A-2908N puts the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, the hardware resources may be dedicated to processing other threads. For example, in at least one embodiment, during a delay associated with vertex shader operations, the execution unit may perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

In at least one embodiment, each of execution units 2908A-2908N operates on an array of data elements. In at least one embodiment, the plurality of data elements are "execution size" or number of lanes of instructions. In at least one embodiment, an execution lane is a logical unit for execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the multiple channels may be independent of multiple physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 2908A-2908N support integer and floating point data types.

In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements may be stored as packed data types in registers, and the execution unit will process the various elements based on the data sizes of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (four word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

In at least one embodiment, one or more execution units may be combined into fused execution units 2909A-2909N with thread control logic (2907A-2907N) executing for a fused EU. In at least one embodiment, multiple EUs can be combined into one EU group. In at least one embodiment, the number of EUs in the fused EU group may be configured to execute separate SIMD hardware threads, and the number of EUs in the fused EU group may vary depending upon the various embodiments. In at least one embodiment, each EU can execute a variety of SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD 32. In at least one embodiment, each fused graphics execution unit 2909A-2909N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2909A includes a first EU 2908A, a second EU 2908B, and thread control logic 2907A common to the first EU 2908A and the second EU 2908B. In at least one embodiment, the thread control logic 2907A controls threads executing on the fused graphics execution unit 2909A, allowing each EU within the fused execution units 2909A-2909N to execute using a common instruction pointer register.

In at least one embodiment, one or more internal instruction caches (e.g., 2906) are included in thread execution logic 2900 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In at least one embodiment, sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler 2910 includes specialized texture or media sampling functionality to process texture or media data during sampling before providing the sampled data to the execution units.

During execution, in at least one embodiment, the graphics and media pipeline sends a thread initiation request to thread execution logic 2900 through thread spawn and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2902 is invoked to further compute output information and cause writing of the results to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, a pixel shader or fragment shader computes values for various vertex attributes to be interpolated on the rasterized object. In at least one embodiment, pixel processor logic within shader processor 2902 then executes pixel or fragment shader programs provided by an Application Program Interface (API). In at least one embodiment, to execute shader programs, shader processor 2902 dispatches threads to execution units (e.g., 2908A) via thread dispatcher 2904. In at least one embodiment, shader processor 2902 uses texture sampling logic in sampler 2910 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric segment, or discard one or more pixels for further processing.

In at least one embodiment, data port 2914 provides a memory access mechanism for thread execution logic 2900 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, the data port 2914 includes or is coupled to one or more cache memories (e.g., data cache 2912) to cache data for memory access via the data port.

As shown in FIG. 29B, in at least one embodiment, graphics execution unit 2908 may include an instruction fetch unit 2937, a general register file array (GRF)2924, an architectural register file Array (ARF)2926, a thread arbiter 2922, a dispatch unit 2930, a branch unit 2932, a set of SIMD Floating Point Units (FPUs) 2931, and in at least one embodiment, a set of dedicated SIMD integer ALUs 2935. The GRF 2924 and ARF 2926 include a set of general purpose register files and architectural register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 2908. In at least one embodiment, each thread architecture state is maintained in the ARF 2926, while data used during thread execution is stored in the GRF 2924. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in ARF 2926.

In at least one embodiment, graphics execution unit 2908 has an architecture that is a combination of Simultaneous Multithreading (SMT) and fine-grained Interleaved Multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and a number of registers per execution unit, where execution unit resources are allocated on logic for executing multiple simultaneous threads.

In at least one embodiment, graphics execution unit 2908 may collectively issue multiple instructions, each of which may be a different instruction. In at least one embodiment, the thread arbiter 2922 of a graphics execution unit thread 2908 may dispatch instructions to one of the dispatch unit 2930, the branch unit 2942, or the SIMD FPU 2934 for execution. In at least one embodiment, each execution thread may access 128 general purpose registers in the GRF 2924, where each register may store 32 bytes, which may be accessed as a SIMD 8 element vector of 32-bit data elements. In at least one embodiment, each execution unit thread may access 4KB in GRF 2924, although embodiments are not so limited and in other embodiments more or less register resources may be provided. In at least one embodiment, up to seven threads may be executed simultaneously, although the number of threads per execution unit may also vary depending on the embodiment. In at least one embodiment where seven threads may access 4KB, the GRF 2924 may store a total of 28 KB. In at least one embodiment, a flexible addressing scheme may allow registers to be addressed together to effectively create wider registers or rectangular block data structures representing strides.

In at least one embodiment, memory operations, sampler operations, and other longer latency system communications are scheduled via a "send" instruction executed by messaging transmit unit 2930. In at least one embodiment, dispatching branch instructions to dedicated branch unit 2932 facilitates SIMD divergence and eventual convergence.

In at least one embodiment, graphics execution unit 2908 includes one or more SIMD Floating Point Units (FPUs) 2934 to perform floating point operations. In at least one embodiment, one or more FPUs 2934 also support integer computations. In at least one embodiment, one or more FPUs 2934 may perform up to M32-bit floating point (or integer) operations in SIMD, or up to 2M 16-bit integer or 16-bit floating point operations in SIMD. In at least one embodiment, at least one FPU provides extended mathematical capabilities to support high throughput a priori mathematical functions and double precision 64-bit floating points. In at least one embodiment, there is also a set of 8-bit integers SIMDALUs 2935, and may be specifically optimized to perform operations related to machine learning computations.

In at least one embodiment, an array of multiple instances of graphics execution unit 2908 may be instantiated in a graphics sub-core grouping (e.g., a sub-slice). In at least one embodiment, execution unit 2908 may execute instructions across multiple execution channels. In at least one embodiment, each thread executing on graphics execution unit 2908 executes on a different channel.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, some or all of the inference and/or training logic 915 may be incorporated into the thread execution logic 2900. Further, in at least one embodiment, logic other than that shown in FIG. 9A or FIG. 9B may be used to accomplish the inference and/or training operations described herein. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure the ALUs of the execution logic 2900 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

FIG. 30 illustrates a parallel processing unit ("PPU") 3000 according to at least one embodiment. In at least one embodiment, the PPU 3000 is configured with machine-readable code that, if executed by the PPU 3000, causes the PPU 3000 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the PPU 3000 is a multithreaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simple instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instance of a set of instructions configured to be executed by the PPU 3000. In at least one embodiment, the PPU 3000 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data in order to generate two-dimensional ("2D") image data for display on a display device, such as a liquid crystal display ("LCD") device. In at least one embodiment, the PPU 3000 is used to perform computations, such as linear algebraic operations and machine learning operations. Fig. 30 shows an example parallel processor for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and any suitable processor may be employed in addition to and/or in place of it.

In at least one embodiment, the one or more PPUs 3000 are configured to accelerate high performance computing ("HPC"), data centers, and machine learning applications. In at least one embodiment, the PPU 3000 is configured to accelerate deep learning systems and applications, including the following non-limiting examples: the system comprises an automatic driving automobile platform, deep learning, high-precision voice, image, text recognition system, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecast, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language conversion, online search optimization, personalized user recommendation and the like.

In at least one embodiment, the PPU 3000 includes, but is not limited to, input/output ("I/O") units 3006, front end units 3010, scheduler units 3012, work allocation units 3014, hubs 3016, crossbars ("Xbar") 3020, one or more general purpose processing clusters ("GPCs") 3018, and one or more partition units ("memory partition units") 3022. In at least one embodiment, the PPU 3000 is connected to a host processor or other PPU 3000 via one or more high-speed GPU interconnects ("GPU interconnect") 3008. In at least one embodiment, the PPU 3000 is connected to a host processor or other peripheral device via a system bus 3002. In one embodiment, the PPU 3000 is connected to local memory including one or more memory devices ("memory") 3004. In at least one embodiment, memory device 3004 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as a high bandwidth memory ("HBM") subsystem, and multiple DRAM dies are stacked within each device.

In at least one embodiment, high-speed GPU interconnect 3008 may refer to a line-based, multi-channel communication link that a system uses for scaling and includes one or more PPUs 3000 ("CPUs") in conjunction with one or more central processing units, supporting cache coherence between the PPUs 3000 and the CPUs, as well as CPU hosting. In at least one embodiment, high-speed GPU interconnect 3008 transmits data and/or commands to other units of PPU 3000 via hub 3016, such as one or more copy engines, video encoders, video decoders, power management units, and/or other components that may not be explicitly shown in fig. 30.

In at least one embodiment, the I/O unit 3006 is configured to send and receive communications (e.g., commands, data) from a host processor (not shown in fig. 30) over the system bus 3002. In at least one embodiment, the I/O unit 3006 communicates with the host processor directly over the system bus 3002 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I/O unit 3006 may communicate with one or more other processors (e.g., one or more PPUs 3000) via a system bus 3002. In at least one embodiment, I/O unit 3006 implements a peripheral component interconnect Express ("PCIe") interface for communicating over a PCIe bus. In at least one embodiment, the I/O unit 3006 implements an interface for communicating with external devices.

In at least one embodiment, the I/O unit 3006 decodes packets received via the system bus 3002. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 3000 to perform various operations. In at least one embodiment, the I/O unit 3006 sends the decoded command to various other units of the PPU 3000 as specified by the command. In at least one embodiment, commands are sent to the front end unit 3010 and/or to other units of the hub 3016 or PPU 3000, such as one or more replication engines, video encoders, video decoders, power management units, and the like (not explicitly shown in fig. 30). In at least one embodiment, the I/O unit 3006 is configured to route communications between various logical units of the PPU 3000.

In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 3000 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffers are areas in memory accessible (e.g., read/write) by both the host processor and the PPU 3000 — the host interface unit may be configured to access buffers in system memory connected to the system bus 3002 by memory requests transmitted over the system bus 3002 via the I/O unit 3006. In at least one embodiment, the host processor writes command streams to a buffer and then sends pointers to the PPU 3000 indicating the start of the command streams, such that the front end unit 3010 receives pointers to one or more command streams and manages the one or more command streams, reads commands from the command streams and forwards the commands to various units of the PPU 3000.

In at least one embodiment, the front end unit 3010 is coupled to a scheduler unit 3012, which scheduler unit 3012 configures various GPCs 3018 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 3012 is configured to track status information related to various tasks managed by the scheduler unit 3012, where the status information may indicate to which GPCs 3018 a task is assigned, whether a task is active or inactive, priorities associated with tasks, and so forth. In at least one embodiment, the scheduler unit 3012 manages a plurality of tasks executing on one or more GPCs 3018.

In at least one embodiment, the scheduler unit 3012 is coupled to a work allocation unit 3014, which work allocation unit 3014 is configured to dispatch tasks to execute on GPCs 3018. In at least one embodiment, the work allocation unit 3014 tracks a number of scheduled tasks received from the scheduler unit 3012 and the work allocation unit 3014 manages a pending task pool and an active task pool for each GPC 3018. In at least one embodiment, the pool of pending tasks includes a plurality of time slots (e.g., 30 time slots) that contain data allocated to tasks to be processed by a particular GPC 3018; the active task pool may include multiple slots (e.g., 4 slots) for tasks that are actively processed by the GPCs 3018, such that as one of the GPCs 3018 completes execution of a task, the task will be evicted from the active task pool of the GPCs 3018, and one of the other tasks is selected from the pending task pool and scheduled to execute on the GPCs 3018. In at least one embodiment, if the active task is in an idle state on the GPC 3018, for example while waiting for a data dependency to resolve, the active task is evicted from the GPC 3018 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled to execute on the GPC 3018.

In at least one embodiment, the work distribution unit 3014 communicates with one or more GPCs 3018 via XBar 3020. In at least one embodiment, the XBar3020 is an interconnection network that couples many of the units of the PPU 3000 to other units of the PPU 3000 and may be configured to couple the work allocation unit 3014 to a particular GPC 3018. In at least one embodiment, other units of one or more PPUs 3000 may also be connected to XBar3020 through hub 3016.

In at least one embodiment, tasks are managed by the scheduler unit 3012 and allocated to one of the GPCs 3018 by the work allocation unit 3014. GPCs 3018 are configured to process tasks and generate results. In at least one embodiment, results may be consumed by other tasks in the GPC3018, routed to a different GPC3018 through the XBar3020 or stored in memory 3004. In at least one embodiment, the results may be written to memory 3004 by partition unit 3022, which implements a memory interface for writing data to memory 3004 or reading data from memory 3004. In at least one embodiment, the results may be transmitted to another PPU 3004 or CPU via a high speed GPU interconnect 3008. In at least one embodiment, the PPU 3000 includes, but is not limited to, U partition units 3022, which is equal to the number of separate and distinct memory devices 3004 coupled to the PPU 3000, described in more detail below in connection with fig. 32.

In at least one embodiment, the host processor executes a driver core that implements an Application Programming Interface (API) that enables one or more applications executing on the host processor to schedule operations to execute on the PPU 3000. In one embodiment, multiple computing applications are executed simultaneously by the PPU 3000, and the PPU 3000 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 3000, and the driver core outputs the tasks to one or more streams processed by the PPU 3000. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as thread bundles (warp). In at least one embodiment, a thread bundle includes multiple related threads (e.g., 30 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads, including instructions for performing tasks and exchanging data through shared memory, the threads and cooperative threads being described in more detail in connection with FIG. 32 in accordance with at least one embodiment.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding the inference and/or training logic 915 are provided below in conjunction with FIG. 9A and/or FIG. 9B. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 3000. In at least one embodiment, the PPU 3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 3000. In at least one embodiment, the PPU 3000 may be used to perform one or more neural network use cases described herein.

FIG. 31 illustrates a general processing cluster ("GPC") 3100 in accordance with at least one embodiment. In at least one embodiment, the GPC 3100 is the GPC 3018 of fig. 30. In at least one embodiment, each GPC 3100 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 3100 includes, but is not limited to, a pipeline manager 3102, a pre-raster operations unit ("PROP") 3104, a raster engine 3108, a work distribution crossbar ("WDX") 3116, a memory management unit ("MMU") 3118, one or more data processing clusters ("DPC") 3106, and any suitable combination of components.

In at least one embodiment, the operation of the GPC 3100 is controlled by a pipeline manager 3102. In at least one embodiment, the pipeline manager 3102 manages the configuration of one or more DPCs 3106 to process tasks allocated to a GPC 3100. In at least one embodiment, the pipeline manager 3102 configures at least one of the one or more DPCs 3106 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 3106 is configured to execute vertex shader programs on programmable streaming multiprocessor ("SM") 3114. In at least one embodiment, the pipeline manager 3102 is configured to route data packets received from the work distribution unit to the appropriate logic units within the GPC 3100, and in at least one embodiment, some data packets may be routed to fixed function hardware units in the PROP 3104 and/or raster engine 3108, while other data packets may be routed to the DPC 3106 for processing by the primitive engine 3112 or SM 3114. In at least one embodiment, the pipeline manager 3102 configures at least one of the DPCs 3106 to implement a neural network model and/or a computing pipeline.

In at least one embodiment, the PROP unit 3104 is configured to route data generated by the raster engine 3108 and the DPC 3106, in at least one embodiment, to a raster operations ("ROP") unit in the partition unit 3022, described in more detail above in connection with fig. 30. In at least one embodiment, the PROP unit 3104 is configured to perform optimizations for color mixing, organize pixel data, perform address translation, and so forth. In at least one embodiment, the raster engine 3108 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 3108 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to a coarse raster engine to generate coverage information for the base primitive (e.g., x, y coverage masks for tiles); the output of the coarse raster engine will be passed to a culling engine where fragments associated with primitives that fail the z-test will be culled and passed to a clipping engine where fragments that lie outside the viewing cone are clipped. In at least one embodiment, the clipped and culled segments are passed to a fine raster engine to generate attributes for the pixel segments based on a plane equation generated by a setup engine. In at least one embodiment, the output of the raster engine 3108 includes fragments to be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 3106).

In at least one embodiment, each DPC 3106 included in the GPC 3100 includes, but is not limited to, an M-line controller ("MPC") 3110; a primitive engine 3112; one or more SM 3114; and any suitable combination thereof. In at least one embodiment, the MPC 3110 controls the operation of the DPC 3106, routing packets received from the pipeline manager 3102 to the appropriate elements in the DPC 3106. In at least one embodiment, packets associated with the vertices are routed to primitive engine 3112, primitive engine 3112 configured to retrieve vertex attributes associated with the vertices from memory; instead, the data packets associated with the shader programs may be sent to the SM 3114.

In at least one embodiment, SM 3114 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by a plurality of threads. In at least one embodiment, the SM 3114 is multithreaded and configured to execute multiple threads (e.g., 32 threads) simultaneously from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture in which each thread in a group of threads (e.g., a thread bundle) is configured to process different sets of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, the SM 3114 implements a single instruction, multi-threaded ("SIMT") architecture in which each thread in a group of threads is configured to process different sets of data based on the same instruction, but in which the individual threads in the group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle to enable concurrency between the thread bundle and serial execution within the thread bundle as threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, so that there is equal concurrency between all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions may be converged and executed in parallel to improve efficiency. At least one embodiment of SM 3114 is described in more detail below.

In at least one embodiment, MMU 3118 provides an interface between GPC 3100 and a memory partition unit (e.g., partition unit 3022 of FIG. 30), and MMU 3118 provides translation of virtual addresses to physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 3118 provides one or more translation lookaside buffers ("TLBs") for performing translations of virtual addresses to physical addresses in memory.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in connection with FIG. 9A and/or FIG. 9B. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 3100. In at least one embodiment, the GPC 3100 is configured to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 3100. In at least one embodiment, the GPC 3100 may be configured to perform one or more of the neural network use cases described herein.

FIG. 32 illustrates a memory partition unit 3200 of a parallel processing unit ("PPU") in accordance with at least one embodiment. In at least one embodiment, memory partition unit 3200 includes, but is not limited to, a raster operations ("ROP") unit 3202; a level two ("L2") cache 3204; a memory interface 3206; and any suitable combination thereof. In at least one embodiment, a memory interface 3206 is coupled to memory. In at least one embodiment, the memory interface 3206 may implement a 32, 64, 128, 1024 bit data bus, or similar implementation for high speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 3206, one memory interface 3206 per pair of partition units 3200, where each pair of partition units 3200 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high bandwidth memory stack or a graphics double data rate version 5 synchronous dynamic random access memory ("GDDR 5 SDRAM").

In at least one embodiment, memory interface 3206 implements a high bandwidth memory second generation ("HBM 2") memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack is located on the same physical package as the PPU, providing a significant amount of power and saving area compared to conventional GDDR5SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y equals 4, and each HBM2 stack includes two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, the memory supports single error correction double error detection ("SECDED") error correction codes ("ECC") to protect data. In at least one embodiment, ECC may provide greater reliability for computing applications that are sensitive to data corruption.

In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partition unit 3200 supports unified memory to provide a single unified virtual address space for a central processing unit ("CPU") and PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of accesses by the PPU to memory located on other processors is tracked to ensure that pages of memory are moved to the physical memory of the PPU that more frequently access the pages. In at least one embodiment, the high speed GPU interconnect 3008 supports address translation services that allow the PPU to directly access the CPU's page tables and provide full access to the CPU memory through the PPU.

In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the copy engine may generate a page fault for an address that is not mapped into the page table, and memory partition unit 3200 then services the page fault, maps the address into the page table, and the copy engine then performs the transfer. In at least one embodiment, fixed (i.e., non-pageable) memory is operated for multiple replication engines among multiple processors, thereby substantially reducing available memory. In at least one embodiment, in the event of a hardware page fault, the address may be passed to the copy engine regardless of whether the memory page resides, and the copy process is transparent.

According to at least one embodiment, data from memory 3004 or other system memory of fig. 30 is fetched by memory partition unit 3200 and stored in L2 cache 3204, L2 cache 3204 is on-chip and shared among various GPCs. In at least one embodiment, each memory partition unit 3200 includes, but is not limited to, at least a portion of an L2 cache associated with a corresponding memory device. In at least one embodiment, the lower level cache is implemented in various units within the GPC. In at least one embodiment, each SM 3114 may implement a level one ("L1") cache, where the L1 cache is a private memory dedicated to a particular SM 3114, and data is retrieved from the L2 cache 3204 and stored in each L1 cache for processing in the functional units of the SM 3114. In at least one embodiment, an L2 cache 3204 is coupled to a memory interface 3206 and XBar 3020.

In at least one embodiment, the ROP unit 3202 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. In at least one embodiment, the ROP unit 3202 performs a depth test in conjunction with the raster engine 3108, receiving the depth of the sample location associated with the pixel fragment from the culling engine of the raster engine 3108. In at least one embodiment, the depths are tested for respective depths in a depth buffer of sample locations associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, the ROP unit 3202 updates the depth buffer and sends the results of the depth test to the raster engine 3108. It will be appreciated that the number of partition units 3200 may be different from the number of GPCs, and thus, each ROP unit 3202 may be coupled to each of the GPCs in at least one embodiment. In at least one embodiment, the ROP unit 3202 tracks packets received from different GPCs and determines whether results generated by the ROP unit 3202 are to be routed through XBar 3020.

Fig. 33 illustrates a streaming multiprocessor ("SM") 3300 in accordance with at least one embodiment. In at least one embodiment, SM 3300 is SM 3114 of fig. 31. In at least one embodiment, SM 3300 includes, but is not limited to, instruction cache 3302; one or more scheduler units 3304; register file 3308; one or more processing cores ("cores") 3310; one or more special function units ("SFUs") 3312; one or more load/store units ("LSUs") 3314; the interconnection network 3316; a shared memory/level one ("L1") cache 3318; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general purpose processing cluster ("GPC") of parallel processing units ("PPUs"), and each task is allocated to a particular data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is allocated to one of the SMs 3300. In at least one embodiment, the scheduler unit 3304 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks allocated to the SM 3300. In at least one embodiment, scheduler unit 3304 schedules thread blocks to execute as bundles of parallel threads, where each thread block is assigned at least one bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 3304 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperating groups to various functional units (e.g., processing cores 3310, SFUs 3312, and LSUs 3314) in each clock cycle.

In at least one embodiment, a collaboration group may refer to a programming model for organizing groups of communication threads that allows developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient parallel decompositions. In at least one embodiment, the collaborative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the application of the conventional programming model provides a single, simple construct for synchronizing the cooperative threads: a barrier (e.g., synchrads () function) across all threads of a thread block. However, in at least one embodiment, a programmer may define thread groups at less than thread block granularity and synchronize within the defined groups to achieve greater performance, design flexibility, and software reuse in the form of an aggregate group-wide functional interface. In at least one embodiment, the collaboration group enables programmers to explicitly define thread groups at sub-block (i.e., as small as a single thread) and multi-block granularity, and perform collective operations, such as synchronizing threads in the collaboration group. In at least one embodiment, the programming model supports clean composition across software boundaries so that library and utility functions can be safely synchronized in their local environment without assumptions about convergence. In at least one embodiment, the collaboration group primitives enable new patterns of collaboration parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the thread block grid.

In at least one embodiment, the scheduling unit 3306 is configured to issue instructions to one or more of the functional units, and the scheduler unit 3304 includes, but is not limited to, two scheduling units 3306 that enable two different instructions from a common thread bundle to be scheduled at each clock cycle. In at least one embodiment, each scheduler unit 3304 includes a single scheduling unit 3306 or additional scheduling units 3306.

In at least one embodiment, each SM 3300 includes, but is not limited to, a register file 3308 in at least one embodiment, the register file 3308 providing a set of registers for the functional units of SM 3300. In at least one embodiment, register file 3308 is divided between each functional unit, such that a dedicated portion of register file 3308 is allocated for each functional unit. In at least one embodiment, register file 3308 is divided among different thread bundles executed by SM 3300, and register file 3308 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 3300 includes, but is not limited to, a plurality L of processing cores 3310, where L is a positive integer. In at least one embodiment, SM 3300 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3310. In at least one embodiment, each processing core 3310 includes, but is not limited to, a full-pipeline, single-precision, double-precision, and/or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating point arithmetic logic unit implements the IEEE 754-. In at least one embodiment, the processing cores 3310 include, but are not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

In accordance with at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, the one or more tensor cores are included in the processing core 3310. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4 × 4 matrix and performs a matrix multiply and accumulate operation D ═ a × B + C, where A, B, C and D are 4 × 4 matrices.

In at least one embodiment, the matrix multiplication inputs a and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on 16-bit floating-point input data. In at least one embodiment, 16-bit floating-point multiplication uses 64 operations and results in a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA 9C + + API) exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use the tensor core from the CUDA-C + + program. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16 x 16 size matrix that spans all 32 thread bundle threads.

In at least one embodiment, each SM 3300 includes, but is not limited to, M SFUs 3312 that perform a particular function (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, SFU 3312 includes, but is not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFU 3312 includes, but is not limited to, a texture unit configured to perform texture mapping filtering operations. In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texels) and a sampled texture map from memory to produce sampled texture values for use by a shader program executed by SM 3300. In at least one embodiment, the texture map is stored in the shared memory/L1 cache 3318. In at least one embodiment, according to at least one embodiment, a texture unit uses mip-maps (e.g., texture maps with different levels of detail) to implement texture operations, such as filtering operations. In at least one embodiment, each SM 3300 includes, but is not limited to, two texture units.

In at least one embodiment, each SM 3300 includes, but is not limited to, N LSUs 3314 that implement load and store operations between shared memory/L1 cache 3318 and register file 3308. In at least one embodiment, each SM 3300 includes, but is not limited to, an interconnection network 3316 connecting each functional unit to register file 3308, and LSU 3314 connects to register file 3308 and shared memory/L1 cache 3318. In at least one embodiment, the interconnection network 3316 is a crossbar switch that may be configured to connect any functional unit to any register in register file 3308 and to connect the LSU 3314 to memory locations in register file 3308 and shared memory/L1 cache 3318.

In at least one embodiment, the shared memory/L1 cache 3318 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 3300 and the primitive engines, and between threads in the SM 3300. In at least one embodiment, the shared memory/L1 cache 3318 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 3300 to the partition unit. In at least one embodiment, the shared memory/L1 cache 3318 is used in at least one embodiment to cache reads and writes. In at least one embodiment, one or more of the shared memory/L1 cache 3318, L2 cache, and memory are backing stores.

In at least one embodiment, combining data caching and shared memory functions into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by or as a cache for programs that do not use shared memory, for example if the shared memory is configured to use half of the capacity, and texture and load/store operations may use the remaining capacity. In accordance with at least one embodiment, integration within shared memory/L1 cache 3318 enables shared memory/L1 cache 3318 to function as a high throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computing, a simpler configuration may be used compared to graphics processing. In at least one embodiment, fixed function graphics processing units are bypassed, thereby creating a simpler programming model. In at least one embodiment, in a general purpose parallel computing configuration, the work allocation unit allocates and distributes blocks of threads directly to the DPCs. In at least one embodiment, the threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, execute the program and perform computations using the SM 3300, use shared memory/L1 cache 3318 to communicate between threads, and use LSU 3314 to read and write global memory through shared memory/L1 cache 3318 and memory partition units. In at least one embodiment, when configured for general purpose parallel computing, the SM 3300 writes to the scheduler unit 3304 a command that can be used to start a new job on the DPC.

In at least one embodiment, the PPU is included in or coupled with a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head-mounted display, a handheld electronic device, or the like. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on chip ("SoC") along with one or more other devices (e.g., an additional PPU, memory, a reduced instruction set computer ("RISC") CPU, one or more memory management units ("MMUs"), digital-to-analog converters ("DACs"), etc.).

In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to connect to a PCIe slot on the desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a chipset of a motherboard.

Inference and/or training logic 915 is operable to perform inference and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in connection with FIG. 9A and/or FIG. 9B. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to SM 3300. In at least one embodiment, SM 3300 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or by SM 3300. In at least one embodiment, SM 3300 may be used to perform one or more neural network use cases described herein.

In at least one embodiment, these components may be used to generate enhanced video using one or more neural networks, such as generating higher frame rate video from frames of lower frame rate video.

In at least one embodiment, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module with increased connectivity can be used that simulates on-chip operations and is a substantial improvement over utilizing conventional central processing unit ("CPU") and bus implementations. In at least one embodiment, the various modules may also be placed separately or in various combinations of semiconductor platforms, depending on the needs of the user.

In at least one embodiment, computer programs in the form of machine-readable executable code or computer control logic algorithms are stored in main memory 1304 and/or secondary storage. According to at least one embodiment, the computer programs, if executed by one or more processors, enable system 1300 to perform various functions. In at least one embodiment, memory 1304, storage, and/or any other storage is a possible example of computer-readable media. In at least one embodiment, secondary storage may refer to any suitable storage device or system, such as a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, an optical disk drive, a digital versatile disk ("DVD") drive, a recording device, universal serial bus ("USB") flash memory, and so forth. In at least one embodiment, the architecture and/or functionality of the various previous figures is in CPU 1302; a parallel processing system 1312; an integrated circuit capable of having at least part of the capabilities of both CPUs 1302; a parallel processing system 1312; a chipset (e.g., a set of integrated circuits designed to operate and sold as a unit to perform a related function, etc.); and any suitable combination of integrated circuits.

In at least one embodiment, the architecture and/or functionality of the various previous figures is implemented in the context of a general purpose computer system, a circuit board system, a game console system dedicated for entertainment purposes, a dedicated system, or the like. In at least one embodiment, computer system 1300 may take the form of a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), personal digital assistant ("PDA"), digital camera, vehicle, head mounted display, handheld electronic device, mobile phone device, television, workstation, gaming console, embedded system, and/or any other type of logic.

In at least one embodiment, the parallel processing system 1312 includes, but is not limited to, a plurality of parallel processing units ("PPUs") 1314 and associated memory 1316. In at least one embodiment, PPU1314 connects to host processors or other peripherals via interconnect 1318 and switch 1320 or multiplexers. In at least one embodiment, the parallel processing system 1312 distributes computing tasks across the parallelizable PPU1314, e.g., as part of a distribution of computing tasks across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, memory is shared and accessed (e.g., for read and/or write access) between some or all of the PPUs 1314, although such shared memory may incur performance penalties relative to using local memory and registers resident on the PPUs 1314. In at least one embodiment, the operations of the PPU1314 are synchronized through the use of commands, such as __ synchreads (), where all threads in a block (e.g., executing across multiple PPUs 1314) reach some point of code execution before proceeding.

Other variations are within the spirit of the present disclosure. Accordingly, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure as defined by the appended claims.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (meaning "including, but not limited to,") unless otherwise noted. The term "connected" (where unmodified it refers to a physical connection) is to be construed as partially or fully contained, attached, or connected together, even if there is some intervening. Unless otherwise indicated herein, references to ranges of values herein are intended merely to serve as shorthand methods of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated or contradicted by context, use of the term "set" (e.g., "set of items") or "subset" should be interpreted as including a non-empty set of one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a respective set does not necessarily denote an appropriate subset of the corresponding set, but rather the subset and the corresponding set may be equal.

Unless explicitly stated otherwise or clearly contradicted by context, conjunctions such as phrases in the form of "at least one of a, B, and C" or "at least one of a, B, and C" are understood in context to be used generically to refer to items, clauses, etc., which may be a or B or C, or any non-empty subset of the set of a and B and C. For example, in an illustrative example of a set having three members, the conjunctive phrases "at least one of a, B, and C" and "at least one of a, B, and C" refer to any of the following sets: { a }, { B }, { C }, { a, B }, { a, C }, { B, C }, { a, B, C }. Thus, such conjunctive language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. In addition, the term "plurality" means the state of a plurality (e.g., "a plurality of items" means a plurality of items) unless otherwise stated or contradicted by context. A plurality is at least two items, but could be more if explicitly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based only on".

The operations of processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, processes such as those described herein (or variations and/or combinations thereof) are performed under control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that is executed collectively by hardware or combinations thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., propagating transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) that, when executed by one or more processors of a computer system (i.e., as a result of being executed), cause the computer system to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory computer-readable storage media of the plurality lack all of the code, but the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors, e.g., a non-transitory computer-readable storage medium stores instructions and a main central processing unit ("CPU") executes some instructions while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such computer system is configured with suitable hardware and/or software that enables the operations to be performed. Further, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes multiple devices that operate differently, such that the distributed computer system performs the operations described herein, and such that a single device does not perform all of the operations.

The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Unless specifically stated otherwise, it may be appreciated that throughout the description, terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical quantities (e.g., electronic) within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices.

In a similar manner, the term "processor" may refer to any device or portion of memory that processes electronic data from registers and/or memory and converts that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, a "processor" may be a CPU or GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to a plurality of processes to execute instructions sequentially or in parallel continuously or intermittently. The terms "system" and "method" may be used interchangeably herein, so long as the system can embody one or more methods, and the methods can be considered a system.

In this document, reference may be made to obtaining, receiving, or entering analog or digital data into a subsystem, computer system, or computer-implemented machine. Obtaining, receiving, or inputting analog and digital data may be accomplished in a variety of ways, such as by receiving data that is a parameter of a function call or a call to an application programming interface. In some implementations, the process of obtaining, receiving, or inputting analog or digital data may be accomplished by transmitting the data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting the data from the providing entity to the acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In various examples, the process of providing, outputting, transferring, sending, or rendering analog or digital data may be accomplished by transferring the data as input or output parameters of a function call, parameters of an application programming interface, or an interprocess communication mechanism.

While the above discussion sets forth example implementations of the described techniques, other architectures can be used to implement the described functionality, and are intended to fall within the scope of the present disclosure. Further, although a particular allocation of responsibilities is defined above for purposes of discussion, the various functions and responsibilities may be allocated and divided in different ways, depending on the circumstances.

Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the claimed subject matter may not necessarily be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A processor, comprising:

one or more Arithmetic Logic Units (ALUs) configured to generate higher frame rate video from lower frame rate video using one or more neural networks.

2. The processor of claim 1, wherein one or more neural networks are trained using unsupervised training with at least one periodic consistency constraint.

3. The processor of claim 2, wherein the unsupervised training comprises: generating a set of intermediate frames from the frame triples; and generating a version of an intermediate tri-tuple frame from the intermediate frame to determine a loss value to be minimized.

4. The processor of claim 1, wherein the one or more neural networks are refined using pseudo-supervised training that is not a domain used to train the one or more neural networks.

5. The processor of claim 4, wherein the pseudo-supervised training comprises: a version of an intermediate frame is generated using one or more trained neural networks, the version of the intermediate frame using each of two adjacent video frames to determine a loss value to be minimized.

6. The processor of claim 1, wherein the one or more neural networks utilize one or more image interpolation algorithms.

7. The processor of claim 1, wherein the one or more ALUs are further configured to generate an enhanced video using the one or more neural networks, the enhanced video having a higher resolution or a lower frame loss rate than input video.

8. A system, comprising:

one or more processors configured to generate higher frame rate video from lower frame rate video using one or more neural networks; and

one or more memories for storing the one or more neural networks.

9. The system of claim 8, wherein the one or more neural networks are trained using unsupervised training with at least one periodic consistency constraint.

10. The system of claim 9, wherein the periodic consistency constraint comprises: generating a set of intermediate frames from the frame triples; and generating a version of an intermediate tri-tuple frame from the intermediate frame to determine a loss value to be minimized.

11. The system of claim 8, wherein the one or more neural networks are refined using pseudo-supervised training that is not a domain used to train the one or more neural networks.

12. The system of claim 11, wherein the pseudo-supervised training comprises: a version of an intermediate frame is generated using one or more trained neural networks, the version of the intermediate frame using each of two adjacent video frames to determine a loss value to be minimized.

13. The system of claim 8, wherein the one or more neural networks utilize one or more image interpolation algorithms.

14. A machine-readable medium having a set of instructions stored thereon, which when executed by one or more processors, causes the one or more processors to at least:

higher frame rate video is generated from lower frame rate video using one or more neural networks.

15. The machine-readable medium of claim 14, wherein one or more neural networks are trained using unsupervised training with at least one periodic consistency constraint.

16. The machine-readable medium of claim 15, wherein the periodic consistency constraint comprises: generating a set of intermediate frames from the frame triples; and generating a version of an intermediate tri-tuple frame from the intermediate frame to determine a loss value to be minimized.

17. The machine-readable medium of claim 14, wherein the one or more neural networks are refined using pseudo-supervised training that is not a domain used to train the one or more neural networks.

18. The machine-readable medium of claim 17, wherein the pseudo-supervised training comprises: a version of an intermediate frame is generated using one or more trained neural networks, the version of the intermediate frame using each of two adjacent video frames to determine a loss value to be minimized.

19. The machine-readable medium of claim 14, wherein the one or more neural networks utilize one or more image interpolation algorithms.

20. A processor, comprising:

one or more Arithmetic Logic Units (ALUs) to train, at least in part, one or more neural networks to generate higher frame rate video from lower frame rate video.

21. The processor of claim 20, wherein the one or more neural networks are trained using unsupervised training with at least one periodic consistency constraint.

22. The processor of claim 21, wherein the cycle consistency constraint comprises: generating a set of intermediate frames from the frame triples; and generating a version of an intermediate tri-tuple frame from the intermediate frame to determine a loss value to be minimized.

23. The processor of claim 20, wherein the one or more neural networks are refined using pseudo-supervised training that is not a domain used to train the one or more neural networks.

24. The processor of claim 23, wherein the pseudo-supervised training comprises: a version of an intermediate frame is generated using one or more trained neural networks, the version of the intermediate frame using each of two adjacent video frames to determine a loss value to be minimized.

25. The processor of claim 20, wherein the one or more neural networks utilize one or more image interpolation algorithms.

26. A system, comprising:

one or more processors to, at least in part, compute parameters corresponding to one or more neural networks to generate higher frame rate video from lower frame rate video; and

one or more memories for storing the parameters.

27. The system of claim 26, wherein the one or more neural networks are trained using unsupervised training with at least one periodic consistency constraint.

28. The system of claim 27, wherein the periodic consistency constraint comprises: generating a set of intermediate frames from the frame triples; and generating a version of an intermediate tri-tuple frame from the intermediate frame to determine a loss value to be minimized.

29. The system of claim 26, wherein the one or more neural networks are refined using pseudo-supervised training that is not a domain used to train the one or more neural networks.

30. The system of claim 29, wherein the pseudo-supervised training comprises: a version of an intermediate frame is generated using one or more trained neural networks, the version of the intermediate frame using each of two adjacent video frames to determine a loss value to be minimized.

31. The system of claim 26, wherein the one or more neural networks utilize one or more image interpolation algorithms.

32. A machine-readable medium having a set of instructions stored thereon, which when executed by one or more processors, causes the one or more processors to at least:

causing one or more neural networks to be at least partially trained to generate higher frame rate video from lower frame rate video; and

one or more memories for storing the parameters.

33. The machine-readable medium of claim 32, wherein one or more neural networks are trained using unsupervised training with at least one periodic consistency constraint.

34. The machine-readable medium of claim 33, wherein the periodic consistency constraint comprises: generating a set of intermediate frames from the frame triples; and generating a version of an intermediate tri-tuple frame from the intermediate frame to determine a loss value to be minimized.

35. The machine-readable medium of claim 32, wherein the one or more neural networks are refined using pseudo-supervised training that is not a domain used to train the one or more neural networks.

36. The machine-readable medium of claim 35, wherein the pseudo-supervised training comprises: a version of an intermediate frame is generated using one or more trained neural networks, the version of the intermediate frame using each of two adjacent video frames to determine a loss value to be minimized.

37. The machine-readable medium of claim 32, wherein the one or more neural networks utilize one or more image interpolation algorithms.