CN114301475A

CN114301475A - Method for continuously eliminating decoding of list SCL, terminal equipment and storage medium

Info

Publication number: CN114301475A
Application number: CN202111679402.5A
Authority: CN
Inventors: 张维栋
Original assignee: Zeku Technology Beijing Corp Ltd
Current assignee: Zeku Technology Beijing Corp Ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-08

Abstract

The embodiment of the application discloses a method for continuously eliminating list SCL decoding, terminal equipment and a storage medium, which are used for saving most area resources occupying Lazy Copy and meeting the requirement of high workload frequency. The embodiment of the application is applied to terminal equipment, the terminal equipment comprises a plurality of pointer register groups, a group of multi-selector MUX (multiplexer) and a group of state registers, and the method comprises the following steps: recording a corresponding binary tree level pointer through a pointer register group corresponding to each layer of a deep binary tree, wherein the binary tree level pointer is obtained through a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

Description

Method for continuously eliminating decoding of list SCL, terminal equipment and storage medium

Technical Field

The present application relates to the field of communications, and in particular, to a method, a terminal device, and a storage medium for continuously eliminating decoding of a list SCL.

Background

In the process of decoding a consecutive Cancellation List (SCL), when the number of decoding lists becomes large and the length of a codeword becomes long, a large number of Multiplexers (MUXs) will deteriorate the timing of a decoder and introduce an increase in area. The selection of a large number of MUX logics prolongs the calculation delay, and forces the main clock frequency of the SCL decoder to be reduced, thereby directly causing bad influence on the performance of the SCL decoder.

Disclosure of Invention

The embodiment of the application provides a method for continuously eliminating list SCL decoding, terminal equipment and a storage medium, which are used for saving most area resources occupying Lazy Copy and meeting the requirement of high workload frequency.

A first aspect of the embodiments of the present application provides a method for continuously eliminating decoding of a list SCL, which is applied to a terminal device, where the terminal device includes a plurality of pointer register sets, a set of multi-selector MUXs, and a set of status registers, and the method may include: recording a corresponding binary tree level pointer through a pointer register group corresponding to each layer of a deep binary tree, wherein the binary tree level pointer is obtained through a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

A second aspect of the embodiments of the present application provides a terminal device, including a plurality of pointer register groups, a group of multi-selector MUXs, and a group of status registers, and further including:

the recording module is used for recording corresponding binary tree level pointers through a pointer register set corresponding to each layer of the deep binary tree, and the binary tree level pointers are obtained through a shifting method; recording the decoding list sequencing index after the decoding of each information node is finished through the group of state registers;

and the calculation module is used for calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

A third aspect of the embodiments of the present application provides a terminal device, including a plurality of pointer register groups, a group of multi-selector MUXs, and a group of status registers, and further including:

a memory storing executable program code;

a processor coupled with the memory;

the processor is used for recording corresponding binary tree level pointers through a pointer register set corresponding to each layer of the deep binary tree, and the binary tree level pointers are obtained through a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

A fourth aspect of embodiments of the present application provides a computer-readable storage medium, comprising instructions that, when executed on a processor, cause the processor to perform the method according to the first aspect of the present application.

In another aspect, an embodiment of the present invention discloses a computer program product, which, when running on a computer, causes the computer to execute the method of the first aspect of the present application.

In another aspect, an embodiment of the present invention discloses an application publishing platform, where the application publishing platform is configured to publish a computer program product, where when the computer program product runs on a computer, the computer is caused to execute the method according to the first aspect of the present application.

According to the technical scheme, the embodiment of the application has the following advantages:

in the embodiment of the present application, the method is applied to a terminal device, where the terminal device includes a plurality of pointer register sets, a group of multi-selector MUXs, and a group of status registers, and the method includes: recording corresponding binary tree level pointers through a pointer register set corresponding to each layer of a deep binary tree, wherein the binary tree level pointers are obtained through a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index. Compared with the prior art that each group of pointer register groups is provided with a corresponding group of MUX and the MUX of an output pointer register group interface, the output pointer register can be obtained through calculation through a group of MUXs and a group of state registers, most area resources occupying Lazy Copy can be saved, and the requirement of high workload frequency is met.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the embodiments and the drawings used in the description of the prior art, and obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to the drawings.

FIG. 1A is a diagram of Polar code decoding depth binary tree;

FIG. 1B is a diagram of a decoding list being replaced;

FIG. 1C is a schematic diagram of coding list replacement by Lazy Copy;

FIG. 1D is a schematic diagram of a conventional Lazy Copy;

FIG. 2 is a schematic diagram of an embodiment of a method for decoding a consecutive elimination list SCL in an embodiment of the present application;

FIG. 3A is a schematic diagram of easy replication of Lazy Copy in an embodiment of the present application;

FIG. 3B is a diagram illustrating a record of corresponding binary tree level pointers in an embodiment of the present application;

FIG. 3C is a diagram of a calculated output pointer register according to an embodiment of the present application;

fig. 4A is a schematic diagram of a terminal device in an embodiment of the present application;

fig. 4B is another schematic diagram of the terminal device in the embodiment of the present application;

fig. 5 is another schematic diagram of the terminal device in the embodiment of the present application;

fig. 6 is a schematic diagram of another embodiment of the terminal device in the embodiment of the present application.

Detailed Description

For a person skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. The embodiments in the present application shall fall within the protection scope of the present application.

In the following, a brief description of the terms referred to in the present application is given, as follows:

polar code (Polar code) is a forward error correction coding scheme used for signal transmission. The core of the structure is that through channel polarization (channel polarization), a method is adopted at the encoding side to enable each sub-channel to present different reliability, when the code length continuously increases, a part of channels tend to a perfect channel (without error code) with capacity close to 1, another part of channels tend to a pure noise channel with capacity close to 0, and the method of directly transmitting information on the channel with capacity close to 1 to approach the channel capacity is the only method which can be strictly proved to reach the shannon limit. On the decoding side, the polarized channel can obtain the performance similar to the maximum likelihood decoding with lower complexity by a simple successive interference cancellation decoding method.

Polar code is a linear channel coding method proposed based on the channel polarization theory, the code word is the only one type of coding method which can reach the Shannon limit found so far, and has lower coding and decoding complexity, and when the coding length is N, the complexity is O (NlogN). The theoretical basis for Polar codes is channel polarization. The channel polarization includes channel combining and channel splitting sections. When the number of combined channels tends to infinity, then a polarization phenomenon occurs: one part of the channel tends to be a noiseless channel, and the other part tends to be a full-noise channel, which is a channel polarization phenomenon. The transmission rate of the noiseless channel will reach the channel capacity i (w), while the transmission rate of the full-noise channel tends to zero. The coding strategy of Polar codes just applies the characteristics of the phenomenon, and uses a noiseless channel to transmit useful information of users, and a full-noise channel transmits appointed information or does not transmit information.

In a 5G wireless communication system, since Polar codes have excellent coding performance and a compact decoding algorithm, and can provide a more efficient data rate, energy efficiency and spectral efficiency for the system in practical terminal applications, Polar codes are selected as a coding scheme for New Radio (NR) control information and a coding scheme for broadcast information carried by a physical broadcast channel. In an actual system, most manufacturers or research organizations adopt a Sequential Cancellation List (SCL) decoding algorithm to obtain a strong error correction capability and decoding performance.

The number of decoding lists is selected according to the requirement of the error rate of the application scenario, and a specific decoding list size (e.g. L ═ 2, 4, 8, 16, etc.) is used to trade off performance and complexity, because SCL decoding is evolved and developed on the basis of Successive Cancellation (SC), where the logic of F & G function, return portion, and etc. calculation for the deep binary tree is consistent. During the SC decoding process, a number of LLR (Log likelihood Ratio) quantized values and partial and return values are generated, which are important intermediate variables during the decoding process, and a large amount of memory resources are required to buffer these intermediate variables during the decoding iteration. When the number of decoding lists in SCL is 1, SCL decoding can be equivalent to SC decoding, and then when the number of decoding lists is greater than 1, the intermediate variables of decoding iteration will be multiplied, and assuming that the number of decoding lists is 4, the storage resource of the decoder will be multiplied by 4, and these intermediate variables will be clipped and replaced. If registers are used as storage resources, the complexity of alternative design among different decoding lists is relatively small, but the area of a chip is multiplied; compared with a Static Random-Access Memory (SRAM) as a storage resource, the design complexity of the replacement between different decoding lists will be slightly increased. For the implementation of the replacement technology in the SCL, most of the design is based on the calculation and update of the ordering result of each iteration through a Multiplexer (MUX), then the ordering result is stored in a corresponding pointer register, and finally a corresponding value is selected according to the number of layers of the binary tree.

In order to optimize the area, the intermediate LLR variable of each decoding list in the SCL decoder is stored using SRAM, as shown in fig. 1A, which is a schematic diagram of decoding a deep binary tree for Polar codes. In fig. 1A, [ a0, a1, a2, …, a7] denotes LLR variables, [ u0, u1, u2, …, u7] denotes partial sum variables,

leaf nodes

0, 1, 2, 3 are information bit nodes, and 4 is a frozen bit node. When the deep binary tree is calculated to the leaf node (the node at the bottom layer of the binary tree), if the node is not the frozen bit node but the information bit node, the decoding list can be replaced and cut according to the accumulated ordering result of the path metric value of each decoding list.

Wherein, the forward left branch message is an F function: outputf ═ sign (llr (a)) sign (llr (b)) min (| llr (a), llr (b)) |;

the forward-to-right branch message is a G function: outputg (-1) u ^ LLR (a) + LLR (b);

LLR (a) is the likelihood ratio of signal a, LLR (b) is the likelihood ratio of signal b, sign (LLR (a)) is the sign of LLR (a), sign (LLR (b)) is the sign of LLR (b), min is the return value of the partial sum of the G function, which takes the minimum value, and u ^ represents the sum of the G function.

Assuming that the SCL decoder has 4 decoding lists, after decoding a certain information bit node, as shown in fig. 1B, the decoding list is a schematic diagram replaced by the decoding list. The decoding list 2 is replaced by the decoding list 0, at this time, the intermediate LLR variables stored in the decoding list 2 are replaced by the intermediate LLR variables of the decoding list 0, and because the intermediate LLR variables are stored in the SRAM, if the intermediate LLR variables are replaced by reading and writing the SRAM, a costly delay cost is paid, and the decoding performance becomes unacceptable. From the point of view of binary tree traversal calculation, the LLR input by the F & G function at each layer is calculated as the result of the previous layer, so a scheme of changing the read SRAM address by a pointer can be adopted to realize the replacement of the LLR of the intermediate variable, as shown in fig. 1C, which is a schematic diagram of realizing the replacement of the decoding list by Lazy Copy. This method of replacing LLRs by pointers is called easy Copy (Lazy Copy).

The design structure of pointer generation in SCL decoder will determine the timing and area performance of decoding list replacement, i.e. the efficiency and energy consumption of Lazy Copy will be the key of decoding list replacement, in most current designs, the pointer structure of Lazy Copy is implemented by using traditional register set in combination with MUX, there is a set of registers in middle layer of deep binary tree to hold the pointer of the layer, and each set has L (decoding list sets maximum value) registers. After decoding and sorting of a certain information bit node is completed, the pointer values in the register set are updated, and when the deep binary tree traverses to a certain middle layer to calculate the F & G function, the Lazy Copy outputs a set of pointer registers corresponding to the Lazy Copy, as shown in fig. 1D, which is a schematic diagram of the conventional Lazy Copy. For example: when the code length of the code word is 8, the number of the decoding lists is 4, 2 groups of registers in a Lazy Copy structure correspond to a first layer and a second layer of a deep binary tree, each group comprises 4 pointer registers corresponding to the number of the decoding lists, each register has 2 bits (bits) as pointers to indicate SRAM addresses for reading different decoding lists, L × log2(L) MUXs are arranged in front of each pointer register, an interface of a Lazy Copy selection output pointer register group has (n-1) × L × log2(L) MUXs, and n-1 is the number of layers of the deep binary tree. In fig. 1D, log2(L) bit indicates a bit of a register, and FF indicates a Flip-Flop (Flip Flop), which is one of the registers.

When the number of decoding lists is increased and the length of code word is increased, the large number of MUXs will deteriorate the timing of decoder and introduce the increase of area, and when the number of decoding lists is increased to 16, the code length of code word is changed to 2¹⁶In the meantime, the number of MUXs will become 16384, where the MUXs that update the pointer register group and the MUXs that output the pointer register group interface each time in fig. 1D are included, and a large number of MUX logic selections make the computation delay longer, and force the main clock frequency of the SCL decoder to decrease, which directly affects the performance of the SCL decoder badly.

In order to solve the problem that the Lazy Copy efficiency of an SCL decoder is low due to the fact that the code length and the number of decoding lists are large, the application provides a methodThe efficient replacement technology is characterized in that the replacement architecture is also formed by adopting a register set and a MUX (multiplexer), but the MUX is greatly reduced by optimization, and the word length of the same condition code is 2¹⁶In the case where the number of decoding lists is 16, the number of MUXs is reduced to 1024. It can be analyzed from the structure of fig. 1D that the conventional Lazy Copy mainly has two parts of MUXs, where the first part is a pointer register set that needs to select different levels during the traversal of the deep binary tree, and the second part is a pointer register set that is updated by a group of MUXs after the information node completes decoding each time.

In the embodiment of the application, the terminal equipment can be deployed on land, including indoor or outdoor, handheld, wearable or vehicle-mounted; can also be deployed on the water surface (such as a ship and the like); and may also be deployed in the air (e.g., airplanes, balloons, satellites, etc.).

In this embodiment, the terminal device may be a Mobile Phone (Mobile Phone), a tablet computer (Pad), a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal device in industrial control (industrial control), a wireless terminal device in self driving (self driving), a wireless terminal device in remote medical (remote medical), a wireless terminal device in smart grid (smart grid), a wireless terminal device in transportation safety (transportation safety), a wireless terminal device in city (smart city), a wireless terminal device in smart home (smart home), or the like.

By way of example and not limitation, in the embodiments of the present application, the terminal device may also be a wearable device. Wearable equipment can also be called wearable intelligent equipment, is to apply wearable technique to carry out intelligent design, develop the general term of the equipment that can wear to daily wearing, like glasses, gloves, wrist-watch, clothing and shoes etc.. A wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also realizes powerful functions through software support, data interaction and cloud interaction. The generalized wearable smart device includes full functionality, large size, and can implement full or partial functionality without relying on a smart phone, such as: smart watches or smart glasses and the like, and only focus on a certain type of application functions, and need to be used in cooperation with other devices such as smart phones, such as various smart bracelets, smart jewelry and the like for physical sign monitoring.

The following further describes the technical solution of the present application by way of an embodiment, as shown in fig. 2, which is a schematic diagram of an embodiment of a method for continuously eliminating decoding of a list SCL in the embodiment of the present application, and is applied to a terminal device, where the terminal device includes a plurality of pointer register sets, a set of multi-selector MUXs, and a set of status registers, and the method may include:

201. and recording corresponding binary tree level pointers through a pointer register group corresponding to each layer of the deep binary tree, wherein the binary tree level pointers are obtained through a shifting method.

It should be noted that the number of pointer register sets is the same as the number of levels of the deep binary tree.

Optionally, the binary tree level pointers recorded by the plurality of pointer register sets are used for pointing to the channel likelihood ratio LLR variables and the partial return sum variables.

Optionally, the number of registers in each group is L, where L is the maximum value of the set decoding list, and L is an integer greater than 0.

Optionally, there is a correspondence between level jumps of the binary tree and the number of decoding nodes.

Optionally, the recording, by the terminal device, the corresponding binary tree level pointer through the pointer register set corresponding to each level of the deep binary tree may include: and the terminal equipment records the corresponding pointer of the binary tree hierarchy by adopting a shifting method for the pointer register group corresponding to each layer of the deep binary tree.

It is understood that the pointer registers in the pointer register set are shift registers. In digital circuits, a shift register is a flip-flop based device that operates on several identical time pulses, into which data is input in parallel or in series, and then shifted one bit to the left or right in turn for each time pulse to be output at the output. The shift register is one-dimensional, and in fact, the shift register is multidimensional, namely, input and output data are columns of bits. The multidimensional shift register can be realized by connecting several shift registers with the same number of bits in parallel.

FIG. 3A is a schematic diagram of easy replication of Lazy Copy in the embodiment of the present application. In fig. 3A, the first part of the MUXs mentioned in fig. 1D is optimized using shift register technology. Analyzing the algorithm of the SCL decoder for deeply traversing the binary tree, knowing that the traversal binary tree level jump and the decoding node count have clear correspondence, the number of the node counter which is 0 from right to left determines the level of the binary tree jump.

Exemplary, for example: the code length of the code word is 8, the number of the decoding lists is 4, when the number of decoding nodes is 1, 3, 5 and 7, the binary tree jumps to the layer 1, when the number of the decoding nodes is 2 and 6, the binary tree jumps to the layer 2, and when the number of the decoding nodes is 4, the binary tree jumps to the layer 3. After the node decoding is completed, the pointer register set is shifted out to the left, and when a certain middle layer is updated from top to bottom in the binary tree, the pointer register set is shifted to the right into the initial value of the pointer register, so that the correctness of the corresponding relation of each decoding list LLR data is ensured. For example: when the binary tree calculation is passed from the second layer to the first layer, the pointer of the second layer is 0, 0, 1, 0, then the pointer moved in by the first layer will become 0, 1, 2, 3. Since the LLR values read for the input at the computation layer may be stored values in other decoding lists, the storage layer from which the computation result is output must be the level corresponding to the decoding list.

Illustratively, as shown in fig. 3B, a schematic diagram of recording corresponding binary tree hierarchy pointers in the embodiment of the present application is shown. For example: there are two groups of pointer registers, which correspond to the

middle levels

1 and 2 of the deep binary tree, each group has 4 pointer registers, and the initial value (initial pointer) of the pointer register group at the beginning of decoding is [0, 1, 2, 3 ]. After decoding is finished for the first information bit node (decoding node 0), the ordering result is [0, 1, 0, 3] (the sort result is [ 0103 ]), registers of two groups of pointers are updated to [0, 1, 0, 3] according to MUX calculation, then the binary tree jumps to the first layer, and simultaneously Lazy Copy is shifted out of the first group of pointer registers [0, 1, 0, 3] (left shift pointer to stage 1); next, a second information bit node (decoding node 1) is decoded, the ordering result is [0, 0, 1, 2] (the start result is [ 0012 ]), the register for calculating the second group of pointers according to the MUX is updated to [0, 0, 1, 0] (the second group of pointer to [ 0010 ]), the binary tree jumps to the second layer, and simultaneously the Lazy Copy moves left out of the second group of pointer registers [0, 0, 1, 0] (left shift pointer to stage 2), at this time, the binary tree calculates from the second layer to the first layer, and the Lazy Copy moves right into the initial pointer register [0, 1, 2, 3] (right shift default pointer value from stage 2 to stage 1).

202. And recording the decoding list sequencing index of each information node after decoding is finished through the group of state registers.

It can be understood that, for the second part of MUXs mentioned in fig. 1D, the MUX is optimized by introducing a set of pointer state registers, where the state registers record the decoded list sorting index after each decoding of the information node is completed, and the pointer register set still holds the binary tree level pointers corresponding to the decoded list sorting index, but does not need to be updated by the MUX every decoding, and only needs to be calculated by a set of MUXs once when outputting the pointer registers. The index of the sorted list in the present application can be understood as a sorting result.

Optionally, the method further includes: the terminal equipment acquires L decoding lists in the decoding process of the continuous elimination list SCL, wherein L is the maximum value of the number of the decoding lists, and is an integer larger than 0.

Optionally, the obtaining, by the terminal device, the L decoding lists in the decoding process of the continuous cancellation list SCL may include: the terminal equipment obtains M decoding bar lists in the process of continuously eliminating the SCL decoding; and the terminal equipment replaces and cuts the M decoding lists according to the path metric value to obtain L decoding lists, wherein M is greater than L. M are integers greater than 0, and L is the maximum value of the configured decoding list.

Optionally, the replacing and cutting the M decoding lists by the terminal device according to the path metric value to obtain L decoding lists, which may include: and the terminal equipment selects and obtains L decoding lists with the minimum path metric value from the M decoding lists.

It can be understood that the terminal device searches a plurality of lists through the Polar decoder at the same time, cuts and replaces the plurality of lists, and retains the L lists with the optimal performance, so that the performance of the Polar code can be greatly improved, and the decoding performance of the Polar code approaches to the maximum likelihood. Assuming that the maximum number of decoding lists is set to 8, that is, when the number of decoding lists exceeds 8, the decoding lists can be replaced and cut according to a Path Metric (Path Metric).

The LLR Path Metric (Path Metric) value of the decoding list is an index for judging whether the decoding list survives or not, the Path Metric is approximate to zero when the actual value is the same as the decision value, the Path Metric value is approximate to the LLR of the node when the actual value is opposite to the decision value, the Path Metric value of each list is the accumulated value of the Path Metric of each node of the decoding list, the smaller the Path Metric value is, the more reliable the decoding list is, the SCL decoder sorts according to the Path Metric value of each decoding list, and then the L best decoding lists, namely the L decoding lists with the smallest Path Metric value, are selected through the sorting result.

203. And calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

Optionally, the calculating, by the terminal device according to the binary tree level pointer and the decoding list sorting index, an output pointer register by the group of MUXs may include: and when the terminal equipment passes through the deep binary tree from the top layer to the bottom layer, calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sequencing index.

Optionally, the obtaining, by the terminal device, an output pointer register by calculation according to the binary tree level pointer and the decoding list sorting index through the group of MUXs may include: and the terminal equipment selects a pointer corresponding to each index in the decoding list sequencing indexes from the binary tree level pointers through the group of multiple selectors to obtain an output pointer register.

It is understood that the terminal device sequentially selects each index in the decoding list sorting indexes through the group of multiple selectors, points to a corresponding pointer in the binary tree level pointers, and accordingly obtains an output pointer register.

Illustratively, when the second node completes decoding, the deep binary tree jumps to the second level, where the decoding list sorting index in the status register is [0, 0, 1, 2], and the binary tree level pointer in the register from which the pointer register set is to be shifted left is [0, 1, 0, 3 ]; then, with a set of multiple selectors, selecting the 1 st pointer in the binary tree level pointers, the corresponding pointer being "0", selecting the 1 st pointer in the binary tree level pointers, the corresponding pointer being "0", selecting the 2 nd pointer in the binary tree level pointers, the corresponding pointer being "1", according to the 3 rd index "1", selecting the 2 nd pointer in the binary tree level pointers, the corresponding pointer being "1", selecting the 3 rd pointer in the binary tree level pointers, the corresponding pointer being "0", according to the 4 th index "2" in the sorted list index; then the output pointer register for Lazy Copy is computed as [0, 0, 1, 0 ].

Fig. 3C is a schematic diagram of the output pointer register calculated in the embodiment of the present application. For example: two groups of pointer registers have initial values (initial pointers) of [0, 1, 2, 3], after a first information bit node is decoded (decoding node 0), the values in the state register group are updated to [0, 1, 0, 3] (the state register update as [ 0103 ]), a group of pointer registers and state registers are shifted out from the left and calculated through a group of multi-selector MUX, and an output pointer register [0, 1, 0, 3] is obtained to the first layer (left shift pointer register with state register to [ 0103 ] to state 1) of the binary tree; when the first layer of the binary tree calculates the G function, the pointer register [0, 1, 0, 3] is moved to the right into the pointer register group; after the second information bit node is decoded (decoding node 1), updating the value in the state register group to [0, 0, 1, 2] (the state register update as [ 0012 ]), shifting out a group of pointer registers and state registers from left, calculating through a group of multi-selector MUX, and obtaining an output pointer register [0, 0, 1, 0] to a second layer (left shift register with state register to get [ 0010 ] to state 2) of the binary tree; thereafter, the second level of the binary tree performs a G function calculation to the first level, and the pointer register is shifted to the right by the register initial value [0, 1, 2, 3] (right shift default pointer value from stage 2 to stage 1).

204. And acquiring the address of the SRAM according to the output pointer register.

The terminal equipment can obtain the address of the SRAM according to the output pointer register.

205. And reading corresponding data according to the address of the SRAM.

And the terminal equipment reads corresponding data according to the address of the SRAM. I.e. the value actually pointed to by the pointer register corresponding to the current level.

It should be noted that steps 204 and 205 are optional steps.

It can be understood that, in the SCL decoder, as the code length is longer, the number of decoding lists increases, the better the decoding performance is obtained, but in order to balance resources and performance, the maximum number of decoding lists and the maximum code length are set according to the simulation result of the algorithm in the actual application scenario, different requirements are put forward for the decoding list replacement technology after the number of decoding lists and the code length are determined, for high-performance consumer electronics, that is, the required area is as small as possible, and the performance is also required to be as high as possible, when the conventional replacement technology is adopted, the SCL decoder cannot meet the requirement of high operating frequency, and a large number of MUXs occupy most area resources of Lazy Copy.

From the formula ii (x, p), q) ii (x, ii (p, q)) (formula 1), it can be seen that the designs of fig. 1D and 3A can achieve the same effect. However, in the design of fig. 3A, i.e. the efficient replacement technology in the present application, based on the current nanotechnology process, the working frequency of 1GHz will be satisfied, for example: for code length of 2¹⁶The number of decoding lists is 16 SCL decoders, and the number of MUXs is reduced to 1/16. To the left in equation 1 is shown the effect of FIG. 1D, requiring a pointer register set to be selected by the MUX each time it is updated. To the right of equation 1, which shows the effect shown in FIG. 3A, the multi-selector MUX need only select once.

In the above formula, x represents the current level of the deep binary tree, p represents the value recorded by the state register, q represents the value recorded by the pointer register set, i.e., the pointed-to LLR variable and the partial return sum variable, and ii represents the product. Namely, the value recorded by the status register is the decoding list sorting index, and the value recorded by the pointer register group is the binary tree level pointer.

The following develops the above equation 1 as follows:

wherein [ ] A]^TIndicating transpose and L a coding list. In summary, we can derive | ("pi (x, p"),q)＝∏(x，∏(p，q))。

in the embodiment of the application, a corresponding binary tree level pointer is recorded through a pointer register group corresponding to each layer of a deep binary tree, and the binary tree level pointer is obtained through a shifting method; recording the decoding list sequencing index after the decoding of each information node is finished through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index. Compared with the prior art that each group of pointer register groups is provided with a corresponding group of MUX and the MUX of an output pointer register group interface, the output pointer register can be obtained through calculation through the group of MUX and the group of status registers, so that a large part of area resources occupying Lazy Copy can be saved, and the requirement of high workload frequency is met.

As shown in fig. 4A, a schematic diagram of an apparatus for calculating a pointer register in SCL decoding in the embodiment of the present application is applied to a terminal device, where the terminal device includes a plurality of pointer register sets, a set of multi-selector MUXs, and a set of status registers, and may further include:

a recording module 401, configured to record a corresponding binary tree level pointer through a pointer register set corresponding to each layer of a deep binary tree, where the binary tree level pointer is obtained by a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers;

and a calculating module 402, configured to calculate, according to the binary tree level pointer and the decoding list sorting index, an output pointer register through the group of MUXs.

Optionally, the calculating module 402 is specifically configured to, when the deep binary tree is traversed from the top layer to the bottom layer, calculate, through the set of MUXs, to obtain an output pointer register according to the binary tree level pointer and the decoding list sorting index.

Optionally, the calculating module 402 is specifically configured to select, from the binary tree hierarchical pointers, a pointer to which each index in the decoding list sorting indexes points correspondingly through the group of multiple selectors, so as to obtain an output pointer register.

Optionally, the recording module 401 is specifically configured to record, by using a shifting method, a corresponding pointer register group of each layer of the deep binary tree, in a corresponding binary tree level pointer.

Optionally, as shown in fig. 4B, the apparatus for calculating a pointer register in SCL decoding in the embodiment of the present application is another schematic diagram. Also comprises an acquisition module 403;

an obtaining module 403, configured to obtain an address of an SRAM according to the output pointer register;

the calculating module 402 is further configured to read corresponding data according to the address of the SRAM.

Optionally, the number of registers in each group is L, where L is the maximum value of the set decoding list, and L is a positive integer.

As shown in fig. 5, which is a schematic diagram of another embodiment of the terminal device in the embodiment of the present application, the terminal device includes a plurality of pointer register sets 501, a set of multi-selector MUXs 502, and a set of status registers 503, and may further include:

a processor 504 coupled to a plurality of pointer register sets 501, a set of multi-selector MUXs 502, and a set of status registers 503;

a processor 504, configured to record a corresponding binary tree level pointer through a pointer register set corresponding to each layer of a deep binary tree, where the binary tree level pointer is obtained by a shift method; recording the decoding list sequencing index after the decoding of each information node is finished through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

Optionally, the processor 504 is specifically configured to calculate, through the set of MUXs, an output pointer register according to the binary tree level pointer and the decoding list sorting index during a traversal of the deep binary tree from the top layer to the bottom layer.

Optionally, the processor 504 is specifically configured to select, through the set of multiple selectors, a pointer corresponding to each index in the decoding list sorting indexes from the binary tree level pointers, so as to obtain an output pointer register.

Optionally, the processor 504 is specifically configured to record, by using a shift method, a corresponding pointer of the binary tree hierarchy for the pointer register set corresponding to each hierarchy of the deep binary tree.

Optionally, the processor 504 is further configured to obtain an address of a static random access memory SRAM according to the output pointer register; and reading corresponding data according to the address of the SRAM.

Fig. 6 is a schematic diagram of another embodiment of the terminal device in the embodiment of the present application. Fig. 6 is a block diagram illustrating a partial structure of a mobile phone related to a terminal device provided in an embodiment of the present invention. Referring to fig. 6, the handset includes: a plurality of pointer register sets 601, a set of multi-selector MUXs 602, a set of status registers 603, a Radio Frequency (RF) circuit 610, a memory 620, an input unit 630, a display unit 640, a sensor 650, an audio circuit 660, a wireless fidelity (Wi-Fi) module 670, a processor 680, and a power supply 690. Those skilled in the art will appreciate that the handset configuration shown in fig. 6 is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.

The following describes each component of the mobile phone in detail with reference to fig. 6:

the RF circuit 610 may be used for receiving and transmitting signals during information transmission and reception or during a call, and in particular, receives downlink information of a base station and then processes the received downlink information to the processor 680; in addition, the data for designing uplink is transmitted to the base station. In general, RF circuit 610 includes, but is not limited to, an antenna, at least one Amplifier, a transceiver, a coupler, a Low Noise Amplifier (LNA), a duplexer, and the like. In addition, the RF circuitry 610 may also communicate with networks and other devices via wireless communications. The wireless communication may use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), and the like.

The memory 620 may be used to store software programs and modules, and the processor 680 may execute various functional applications and data processing of the mobile phone by operating the software programs and modules stored in the memory 620. The memory 620 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory 620 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.

The input unit 630 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the cellular phone. Specifically, the input unit 630 may include a touch panel 631 and other input devices 632. The touch panel 631, also referred to as a touch screen, may collect touch operations of a user (e.g., operations of the user on the touch panel 631 or near the touch panel 631 by using any suitable object or accessory such as a finger or a stylus) thereon or nearby, and drive the corresponding connection device according to a preset program. Alternatively, the touch panel 631 may include two parts of a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 680, and can receive and execute commands sent by the processor 680. In addition, the touch panel 631 may be implemented using various types, such as resistive, capacitive, infrared, and surface acoustic wave. The input unit 630 may include other input devices 632 in addition to the touch panel 631. In particular, other input devices 632 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like.

The display unit 640 may be used to display information input by the user or information provided to the user and various menus of the mobile phone. The Display unit 640 may include a Display panel 641, and optionally, the Display panel 641 may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like. Further, the touch panel 631 can cover the display panel 641, and when the touch panel 631 detects a touch operation thereon or nearby, the touch operation is transmitted to the processor 680 to determine the type of the touch event, and then the processor 680 provides a corresponding visual output on the display panel 641 according to the type of the touch event. Although in fig. 6, the touch panel 631 and the display panel 641 are two independent components to implement the input and output functions of the mobile phone, in some embodiments, the touch panel 631 and the display panel 641 may be integrated to implement the input and output functions of the mobile phone.

The handset may also include at least one sensor 650, such as a light sensor, motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor that adjusts the brightness of the display panel 641 according to the brightness of ambient light, and a proximity sensor that turns off the display panel 641 and/or the backlight when the mobile phone is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor may be further configured on the mobile phone, which are not described herein again.

Audio circuit 660, speaker 661, and microphone 662 can provide an audio interface between a user and a cell phone. The audio circuit 660 may transmit the electrical signal converted from the received audio data to the speaker 661, and convert the electrical signal into an audio signal through the speaker 661 for output; on the other hand, the microphone 662 converts the collected sound signals into electrical signals, which are received by the audio circuit 660 and converted into audio data, which are processed by the audio data output processor 680 and then passed through the RF circuit 610 for transmission to, for example, another cellular phone, or output to the memory 620 for further processing.

Wi-Fi belongs to short-distance wireless transmission technology, and a mobile phone can help a user to receive and send emails, browse webpages, access streaming media and the like through a Wi-Fi module 670, and provides wireless broadband internet access for the user. Although fig. 6 shows a Wi-Fi module 670, it is understood that it does not belong to the essential constitution of the handset and can be omitted entirely as needed within the scope not changing the essence of the invention.

The processor 680 is a control center of the mobile phone, connects various parts of the entire mobile phone using various interfaces and lines, and performs various functions of the mobile phone and processes data by operating or executing software programs and/or modules stored in the memory 620 and calling data stored in the memory 620, thereby integrally monitoring the mobile phone. Optionally, processor 680 may include one or more processing units; preferably, the processor 680 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 680.

The handset also includes a power supply 690 (e.g., a battery) for powering the various components, which may preferably be logically connected to the processor 680 via a power management system, such that the power management system may be used to manage charging, discharging, and power consumption.

Although not shown, the mobile phone may further include a camera, a bluetooth module, etc., which are not described herein.

In this embodiment of the present invention, the processor 680 is configured to record a corresponding binary tree level pointer through a pointer register set corresponding to each level of a deep binary tree, where the binary tree level pointer is obtained by a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers; and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

Optionally, the processor 680 is specifically configured to calculate, through the set of MUXs, an output pointer register according to the binary tree level pointer and the decoding list sorting index during a traversal of the deep binary tree from a top layer to a bottom layer.

Optionally, the processor 680 is specifically configured to select, through the set of multiple selectors, a pointer corresponding to each index in the decoding list sorting indexes from the binary tree level pointers, so as to obtain an output pointer register.

Optionally, the processor 680 is specifically configured to record, by using a shift method, a corresponding pointer register group of each level of the deep binary tree, in a corresponding pointer register group of the binary tree.

Optionally, the processor 680 is further configured to obtain an address of the SRAM according to the output pointer register; and reading corresponding data according to the address of the SRAM.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on or transmitted from one computer-readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and in actual implementation, there may be other divisions, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a hardware form, and can also be realized in a software functional unit form.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A method for continuously eliminating decoding of a list SCL is applied to a terminal device, the terminal device comprises a plurality of pointer register groups, a group of multi-selector MUX and a group of status registers, and the method is characterized by comprising the following steps:

recording a corresponding binary tree level pointer through a pointer register group corresponding to each layer of a deep binary tree, wherein the binary tree level pointer is obtained through a shifting method;

recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers;

and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index.

2. The method of claim 1, wherein computing an output pointer register from the set of MUXs according to the binary tree level pointer and the decoded list ordering index comprises:

and calculating to obtain an output pointer register through the group of MUXs according to the binary tree level pointer and the decoding list sorting index during the traversal of the deep binary tree from the top layer to the bottom layer.

3. The method according to claim 1 or 2, wherein said calculating an output pointer register from said set of MUXs according to said binary tree level pointer and said decoded list ordering index comprises:

and selecting a pointer corresponding to each index in the decoding list sorting indexes from the binary tree level pointers through the group of multiple selectors to obtain an output pointer register.

4. The method according to claim 1 or 2, wherein the recording of the corresponding binary tree level pointer through the corresponding pointer register set of each level of the deep binary tree comprises:

and for the pointer register group corresponding to each layer of the deep binary tree, recording the corresponding binary tree level pointer by adopting a shifting method.

5. The method according to claim 1 or 2, characterized in that the method further comprises:

acquiring the address of a Static Random Access Memory (SRAM) according to the output pointer register;

and reading corresponding data according to the address of the SRAM.

6. The method of claim 1 or 2, wherein the plurality of pointer register sets record binary tree level pointers to channel likelihood ratio (LLR) variables and partial return sum variables.

7. The method according to claim 1 or 2, wherein the number of registers in each group is L, wherein L is the maximum value of the configured decoding list, and L is a positive integer.

8. A terminal device comprising a plurality of pointer register sets, a set of multi-selector MUXs, and a set of status registers, further comprising:

the recording module is used for recording corresponding binary tree level pointers through a pointer register set corresponding to each layer of the deep binary tree, and the binary tree level pointers are obtained through a shifting method; recording the decoding list sequencing index of each information node after decoding is completed through the group of state registers;

9. A terminal device comprising a plurality of pointer register sets, a set of multi-selector MUXs, and a set of status registers, further comprising:

a memory storing executable program code;

a processor coupled with the memory;

10. A computer-readable storage medium comprising instructions that, when executed on a processor, cause the processor to perform the method of any of claims 1-7.