CN114299875A - Drive circuit, drive control unit and electronic equipment - Google Patents
Drive circuit, drive control unit and electronic equipment Download PDFInfo
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- CN114299875A CN114299875A CN202111599557.8A CN202111599557A CN114299875A CN 114299875 A CN114299875 A CN 114299875A CN 202111599557 A CN202111599557 A CN 202111599557A CN 114299875 A CN114299875 A CN 114299875A
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Abstract
The embodiment of the invention relates to the technical field of display, and discloses a driving circuit, a driving control unit and electronic equipment. In the present invention, the drive circuit includes: the first node is used for being connected with a component to be driven; a first port for connection to a first power supply; a delay circuit connected between the first port and the first node; a second port for connection to a second power supply; the compensation circuit comprises a first input interface, a second input interface and a compensation voltage output interface, wherein the first input interface is connected with the second interface, the second input interface is connected with the first interface, and the compensation voltage output interface is connected with the first node. The driving circuit, the driving control unit and the electronic equipment provided by the invention can avoid the problem of abnormal display caused by the response time required by the compensation circuit, and improve the reliability of the electronic equipment.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a driving circuit, a driving control unit and electronic equipment.
Background
The output voltage of the driving circuit is unstable due to various factors, for example, in the 4power supply mode adopted by the AMOLED mobile phone, the external DVDD may be smaller than the minimum voltage value required by the RAM due to external impedance variation or DVDD voltage jitter, and the like, so that data in the RAM is lost and abnormal display is caused. In the related art, a scheme of adding a compensation circuit to a driving circuit is proposed.
The inventor finds that at least the following problems exist in the prior art: since the compensation circuit requires a response time, there is still a problem that data in the RAM is lost and an abnormality is displayed, and the reliability of the electronic device is not high.
Disclosure of Invention
An object of embodiments of the present invention is to provide a driving circuit, a driving control unit, and an electronic device, which can avoid the problem of display abnormality due to the response time required by a compensation circuit, and improve the reliability of the electronic device.
To solve the above technical problem, an embodiment of the present invention provides a driving circuit, including: the first node is used for being connected with a component to be driven; a first port for connection to a first power supply; the delay circuit is connected between the first port and the first node and is used for transmitting the voltage of the first port to the first node after delaying; a second port for connection to a second power supply; the compensation circuit comprises a first input interface, a second input interface and a compensation voltage output interface, wherein the first input interface is connected with the second port, the second input interface is connected with the first port, and the compensation voltage output interface is connected with the first node and used for starting compensation to recover the voltage of the compensation voltage output interface when the voltage of the first port is lower than or equal to a preset voltage.
An embodiment of the present invention also provides a drive control unit including: the driving circuit and the random access memory are connected with the first node.
An embodiment of the present invention also provides an electronic device, including: the driving control unit, the first power supply and the second power supply are as above, the first power supply is connected to the first port, and the second power supply is connected to the second port.
Compared with the prior art, the embodiment of the invention has the advantages that the voltage change of the first node is delayed to be lower than the voltage change of the first port by arranging the delay circuit, and when the voltage of the first port is reduced to be lower than the preset voltage, the first node can keep the original voltage value of the first port in the reaction period of the compensation circuit (from the start of the compensation circuit to the time taken by the compensation circuit to reach the preset voltage in actual output), so that the voltage on the part to be driven is always kept to be higher than the voltage value required by the part to be driven, the problem of abnormal display caused by abnormal data stored in the part to be driven is avoided, and the reliability of the electronic equipment is improved.
In addition, the compensation circuit is a voltage comparator, and the voltage value of the compensation voltage output interface is equal to the maximum value of the voltage value of the first input interface and the voltage value of the second input interface.
In addition, the output voltage of the second power supply is greater than the output voltage of the first power supply; the driving circuit further includes the voltage conversion chip, and the voltage conversion chip includes: the voltage of the output end is smaller than the voltage of the input end and smaller than the output voltage of the first power supply.
In addition, the device also comprises a charge storage device used for voltage stabilization and filtering, wherein one end of the charge storage device is connected with the first port, and the other end of the charge storage device is grounded. By providing a charge storage device, voltage stabilization and filtering can be achieved.
In addition, the delay circuit includes a first resistor and a first capacitor, the first resistor is connected between the first port and the first node, one end of the first capacitor is connected between the first resistor and the first node, and the other end of the first capacitor is grounded.
In addition, the delay circuit further comprises a second resistor and a second capacitor, the second resistor is connected between the first resistor and the first node, one end of the second capacitor is connected between the second resistor and the first node, the other end of the second capacitor is grounded, and one end of the first capacitor is connected between the first resistor and the second resistor.
In addition, the analog circuit further comprises a third power supply and a fourth power supply, wherein the output voltage of the third power supply and the output voltage of the fourth power supply are both greater than the output voltage of the second power supply, and the third power supply and the fourth power supply are both used for supplying power to the analog circuit.
In addition, the display screen is connected with the random access memory and used for displaying according to the display data stored in the random access memory.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a 3power supply mode in the related art;
FIG. 2 is a schematic diagram of a 4power supply mode in the related art;
FIG. 3 is a schematic diagram of the addition of a compensation circuit in the driver IC;
FIG. 4 is a graph showing a change in DVDD in the related art;
fig. 5 is a schematic diagram of a driving circuit provided in a first embodiment of the present invention connected to a power supply and a component to be driven;
fig. 6 is a schematic diagram of a delay circuit in the driving circuit according to the first embodiment of the present invention;
fig. 7 is a schematic diagram of voltage changes at various positions in the driving circuit according to the first embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
The AMOLED phone may employ a 3power supply mode (as shown in fig. 1) or a 4power supply mode (as shown in fig. 2). In the 3power supply mode, the external power supply only supplies 1.8V to the driving IC, and the 1.8V is divided into two paths of 1.8V and 1.2V inside the IC, but the total current is equal to the current of the 1.8 path, and assuming that the current of the 1.8 path is 150mA, the total power consumption is 150mA × 1.8V — 270mW, while in the 4power supply mode, the power consumption is approximately 1.2V x 143mA +1.8V x 7mA — 184.2mW, which can save nearly 90 mW. Therefore, to reduce power consumption, AMOLED handsets typically employ a 4power supply mode.
However, the inventor found that in the 4power supply mode, if the external trace impedance is relatively large, or the ripple of the path 1.2v (DVDD) is relatively large, the external DVDD is smaller than the minimum voltage value required by a RAM (random access memory) in the driver IC if the voltage is unstable, so that data stored in the RAM is abnormal, and a display error is caused.
Therefore, a DVDD compensation function can be added to the driver IC. As shown in fig. 3, the external DVDD is generally 1.25V, the internal DVDD is generally set to 1.1V (for reducing power consumption, the internal DVDD is generally set to the minimum voltage value required by the RAM), and if the external trace impedance is relatively large and the voltage drop is relatively large, or the external DVDD is suddenly reduced, the internal DVDD compensation is started to compensate the DVDD voltage.
It should be noted that, since the internal DVDD is from 1.8V, if the compensation is always turned on, the power consumption is relatively large, and since the IC, the internal DVDD is generally set to the minimum voltage value required by the RAM and is not set to be larger.
As shown in fig. 4, fig. 4 is a graph showing a change in DVDD in the related art.
The method comprises the following steps: indicating that DVDD suddenly begins to decrease.
Secondly, the step of: the corresponding DVDD is in the 1.1V position, indicating that the internal compensation circuit is active when DVDD is below 1.1V.
(ii) to (iii): representing the reaction time of the internal compensation circuit.
③ to fourthly: indicating the time at which the internal compensation circuit begins to function.
After the fourth time, it indicates that the internal compensation circuit has stabilized to the set 1.1V.
It can be known that when the external DVDD suddenly decreases, it takes a period of time for the internal DVDD compensation function to stabilize to the set 1.1V (the compensation has a lag problem), that is, the RAM voltage will be less than 1.1V from (ii) to (iv), and because the RAM voltage is low, there is a risk of abnormal display caused by abnormal data in the RAM, that is, there is a probabilistic abnormal display.
A first embodiment of the present invention relates to a drive circuit 100, as shown in fig. 5, including: the circuit comprises a first node B, a first port A, a delay circuit 11, a second port C and a compensation circuit 12, wherein the first node B is used for being connected with a component 10 to be driven, the first port A is used for being connected with a first power supply, the delay circuit 11 is connected between the first port A and the first node B, the second port C is used for being connected with a second power supply, the compensation circuit 12 comprises a first input interface, a second input interface and a compensation voltage output interface, the first input interface is connected with the second port C, the second input interface is connected with the first port A, and the compensation voltage output interface is connected with the first node B.
Because the first node B is used to connect to the component 10 to be driven, the delay circuit 11 is disposed between the first port a and the first node B, the second input interface of the compensation circuit 12 is connected to the first port a, and the compensation voltage output interface of the compensation circuit 12 is connected to the first node B, that is, the voltage of the first port a is delayed and then provided to the component 10 to be driven, the real-time voltage of the first port a (external DVDD) is fed back to the compensation circuit 12 in real time to monitor the change of the external DVDD in real time to trigger the voltage compensation, that is, the compensation is started by detecting the abnormality first, so that when the voltage of the first port a is reduced to the preset voltage, the circuit compensation is triggered, and in the response time of the compensation circuit 12, because the component 10 to be driven receives the voltage of the first port a after the delay, the voltage is the voltage before the first port a is reduced to the preset voltage, therefore, the voltage requirement required by the component 10 to be driven can still be met, after the time delay, the voltage (internal DVDD) of the second port C is already raised to the safety compensation value, at the moment, the internal DVDD acts to meet the voltage requirement required by the component 10 to be driven, the voltage on the component 10 to be driven is ensured to be always maintained above the voltage value required by the component 10 to be driven, the problem of abnormal display caused by abnormal data stored in the component 10 to be driven is avoided, and the reliability of the electronic device is improved.
In this embodiment, the driving circuit 100 may further include a charge storage device C1 for voltage stabilization and filtering, the charge storage device C1 is connected to the first port a at one end and to ground at the other end, wherein the charge storage device C1 may be a capacitor, and voltage stabilization and filtering can be achieved by using the capacitor.
Alternatively, the compensation circuit 12 may be a voltage comparator, and the voltage value of the compensation voltage output interface is equal to the maximum value of the voltage value of the first input interface (equal to the set value of the internal DVDD) and the voltage value of the second input interface (equal to the current value of the external DVDD).
In practical applications, the output voltage (i.e., the second voltage) of the second power supply may be greater than the output voltage (i.e., the first voltage) of the first power supply, the driving circuit 100 may further include a voltage conversion chip 13, and the voltage conversion chip 13 may include: an input end for connecting with a second power supply and an output end for connecting with a second port C, wherein the voltage of the output end is less than the voltage of the input end (equal to the output voltage of the second power supply) and less than the output voltage of the first power supply, and the first power supply is connected with the first port A. That is, the voltage of the output terminal (the voltage of the second port C) is smaller than the voltage of the input terminal (the second voltage), and the voltage of the output terminal (the voltage of the second port C) is smaller than the output voltage (the first voltage) of the first power supply.
Specifically, the second power supply provides the second voltage (equal to the voltage at the input end) to the voltage conversion chip 13, the voltage conversion chip 13 converts the second voltage into the setting voltage (i.e., the setting value of the internal DVDD, i.e., the voltage at the output end), and provides the setting voltage to the second port C, the first power supply provides the first voltage, and the actual voltage at the first port a (i.e., the current value of the external DVDD) is smaller than the first voltage due to the fact that the external trace impedance is larger or the ripple of the first power supply is larger.
Specifically, the set voltage may be set to 1.1V, the first voltage may be 1.25V, and the second voltage may be 1.8V.
Specifically, the delay circuit 11 may be a conventional RC delay circuit 11, a transistor-type delay circuit 11, or the like, and is not limited herein. In some embodiments, the delay circuit 11 may include a first resistor and a first capacitor, the first resistor is connected between the first port a and a first node B, one end of the first capacitor is connected between the first resistor and the first node B, and the other end of the first capacitor is grounded.
Optionally, the delay circuit 11 may further include a second resistor and a second capacitor, the second resistor is connected between the first resistor and the first node B, one end of the second capacitor is connected between the second resistor and the first node B, the other end of the second capacitor is grounded, and one end of the first capacitor is connected between the first resistor and the second resistor.
As shown in fig. 6, in practical applications, the delay circuit 11 may also include multiple sets of capacitors and resistors, and the switches 1 through switch (2n-2) may be set to be on or off, for example, if only R1 and C1 are used, the switches 1 through switch (n-1) are off, and the switches (n) through switch (2n-2) need to be closed; with R1 and C1, R2 and C2, and R3 and C3, switch1 and switch2 are closed, switches 3 to 3 are open, switch (n), switch (n +1) is open, and switches (n +2) to (2n-2) are closed.
Fig. 7 is a schematic diagram showing voltage changes at various positions in the driving circuit 100. The thin solid line is the voltage at point a (i.e., the first port a), the thick solid line is the voltage at point B (i.e., the first node B), and the dotted line is the actual output value (i.e., the output voltage of the compensation circuit) after the internal DVDD compensation is started.
The method comprises the following steps: the external DVDD (voltage of the first port a) is not powered down (not lowered) and the RAM is powered by 1.25V of the external DVDD.
Stage two: the external DVDD drops to 1.1V, the internal DVDD detects that the voltage at the point A drops to 1.1V, the drive IC starts the internal compensation, and the voltage of the DVDD of the RAM is still 1.25V.
Stage III: the external DVDD drops to about 1.0V, which is the response time of the driving IC, although the internal DVDD still does not start to compensate in the real sense at this time, the RAM voltage is 1.25V (since the voltage at the point a is detected to drop, but the point B after the delay does not start to power down), and thus the display is not abnormal.
Stage IV: the internal DVDD starts to compensate, the output voltage of the compensation voltage output interface of the compensation circuit 12 gradually increases from 1.0 to 1.1V, and although the output voltage of the compensation voltage output interface is smaller than the minimum voltage value (1.1V) required by the RAM of the drive IC, the voltage at the point B after passing through the delay circuit is still 1.25V or higher than 1.1V at this time, specifically, see the voltage curve at the point B in the stage (r), so that there is no problem in displaying at this time.
Stage five: the internal DVDD voltage has been compensated to 1.1V and stabilized, at this time, the external DVDD voltage drops below 1.1V no matter before or after the delay, at this time, the internal DVDD voltage has risen to the safe compensation value of 1.1V, the internal DVDD voltage starts to function, and the RAM voltage is 1.1V.
As can be seen from fig. 7, by providing the delay circuit 11, it is ensured that the voltage at the point B is maintained at 1.1V or more at the stage (within the reaction time) where the internal DVDD voltage does not act yet, and the problem of abnormal display caused by too low RAM voltage is avoided.
Compared with the prior art, the embodiment of the invention has the advantages that the delay circuit 11 is arranged, so that the voltage change of the first node B is delayed from the voltage change of the first port a, and when the voltage of the first port a is reduced to be lower than the preset voltage, the first node B can keep the original voltage value of the first port a during the reaction period of the compensation circuit 12 (from the start of the compensation circuit 12 to the time that the actual output of the compensation circuit 12 reaches the preset voltage, the time is taken), the voltage on the component 10 to be driven is always kept to be higher than the voltage value required by the component 10 to be driven, the problem of abnormal display caused by abnormal data stored in the component 10 to be driven is avoided, and the reliability of the electronic device is improved. That is, by optimizing the internal DVDD compensation circuit 12 of the DDIC (display driver IC), adding the delay circuit 11, and synchronously adjusting the internal routing, the effect that even if the external DVDD is smaller than the minimum value required by the RAM due to impedance change or voltage jitter of the DVDD, the internal DVDD compensation does not cause display abnormality for a period of response time is achieved.
A second embodiment of the present invention provides a drive control unit including: as described above, the driving circuit 100 and the random access memory are connected to the first node B. Among them, the driving control unit may be a driving IC, and further may be a DDIC (display driving IC).
It should be noted that this embodiment is an example corresponding to the first embodiment, and may be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment. In addition, the technical effects achieved in the first embodiment can be achieved in the present embodiment as well, and are not described here again in order to reduce redundancy.
A third embodiment of the present invention provides an electronic apparatus including: as described above, the driving control unit, the first power source and the second power source are connected, the first power source is connected to the first port a, and the second power source is connected to the second port C.
In practical application, the electronic device may further include a display screen, the display screen is connected to the random access memory and is configured to display according to the display data stored in the random access memory, and the display screen may be an AMOLED display screen.
Optionally, the display screen may include a plurality of pixels and a timing circuit that controls the pixels (to be turned on or off), and the electronic device may further include a third power supply and a fourth power supply, where the third power supply and the fourth power supply are configured to supply power to the plurality of pixels and the timing circuit, and an output voltage of the third power supply and an output voltage of the fourth power supply may both be greater than an output voltage of the second power supply.
That is, the electronic device adopts a 4power supply mode, the first power supply may be a digital circuit power supply DVDD, the second power supply may be an input/output port voltage IOVCC, the third power supply may be an analog circuit power supply AVDD (voltage may be 7V), and the fourth power supply may be a power supply voltage VCI (voltage may be 3V).
It is to be understood that this embodiment is an example of an electronic device corresponding to the first embodiment, and that this embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment. In addition, the technical effects achieved in the first embodiment can be achieved in the present embodiment as well, and are not described here again in order to reduce redundancy.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A driver circuit, comprising:
the first node is used for being connected with a component to be driven;
a first port for connection to a first power supply;
the delay circuit is connected between the first port and the first node and is used for transmitting the voltage of the first port to the first node after delaying;
a second port for connection to a second power supply;
the compensation circuit comprises a first input interface, a second input interface and a compensation voltage output interface, wherein the first input interface is connected with the second port, the second input interface is connected with the first port, and the compensation voltage output interface is connected with the first node and used for starting compensation to recover the voltage of the compensation voltage output interface when the voltage of the first port is lower than or equal to a preset voltage.
2. The driving circuit according to claim 1, wherein the compensation circuit is a voltage comparator, and the voltage value of the compensation voltage output interface is equal to the maximum value of the voltage value of the first input interface and the voltage value of the second input interface.
3. The drive circuit according to claim 2, wherein the output voltage of the second power supply is larger than the output voltage of the first power supply;
the driving circuit further includes the voltage conversion chip, and the voltage conversion chip includes: the voltage of the output end is smaller than the voltage of the input end and smaller than the output voltage of the first power supply.
4. The driving circuit of claim 1, further comprising a charge storage device for voltage regulation and filtering, the charge storage device being connected to the first port at one end and to ground at the other end.
5. The driving circuit of claim 1, wherein the delay circuit comprises a first resistor and a first capacitor, the first resistor is connected between the first port and the first node, one end of the first capacitor is connected between the first resistor and the first node, and the other end of the first capacitor is grounded.
6. The driving circuit of claim 5, wherein the delay circuit further comprises a second resistor and a second capacitor, the second resistor is connected between the first resistor and the first node, one end of the second capacitor is connected between the second resistor and the first node, the other end of the second capacitor is grounded, and one end of the first capacitor is connected between the first resistor and the second resistor.
7. A drive control unit, characterized by comprising: a drive circuit according to any one of claims 1 to 6, and a random access memory connected to the first node.
8. An electronic device, comprising: the drive control unit of claim 7, a first power supply connected to the first port, and a second power supply connected to the second port.
9. The electronic device of claim 8, further comprising a display screen coupled to the random access memory and configured to display according to display data stored in the random access memory.
10. The electronic device according to claim 9, wherein the display screen includes a plurality of pixels, and a timing circuit that controls the pixels;
the electronic device further includes a third power supply and a fourth power supply for supplying power to the plurality of pixels and the sequential circuit.
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| CN110728939A (en) * | 2018-07-16 | 2020-01-24 | 三星显示有限公司 | Display device |
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| CN102237810A (en) * | 2010-04-22 | 2011-11-09 | 通嘉科技股份有限公司 | Control method of SMPS (switch mode power supply) and compensating circuit |
| CN102299628A (en) * | 2010-06-25 | 2011-12-28 | 立锜科技股份有限公司 | Voltage regulator and control circuit and method therefor |
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