CN114297115B

CN114297115B - Dual-channel data communication anti-collision system based on FPGA

Info

Publication number: CN114297115B
Application number: CN202111508842.4A
Authority: CN
Inventors: 罗毅; 李亚楠; 龙志详; 刘杰
Original assignee: Guizhou Aerospace Kaishan Petroleum Instrument Co Ltd
Current assignee: Guizhou Aerospace Kaishan Petroleum Instrument Co Ltd
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2024-04-16
Anticipated expiration: 2041-12-10
Also published as: CN114297115A

Abstract

The invention provides A dual-channel data communication anti-collision system based on an FPGA (field programmable gate array), which consists of A PC (personal computer), an RJ45 communication module, A DSP, FPGA, RS A communication module and an RS485B communication module, wherein A DSP (digital signal processor) generates 4ms timed interrupt, the FPGA is connected with A485A port to extract inertial measurement front end data at fixed time and receive 485B port 4ms data, the FPGA is used for realizing A synchronous 485 hardware interface circuit, A1K byte FIFO (first in first out) is built in the FPGA and is used for receiving and caching 485B port data, the RJ45 communication module is used for communicating with the PC, and the RS485A communication module and the RS485B communication module are used for communicating with the inertial measurement front end. To overcome the shortcomings of current inertial measurement front-end performance detection techniques and devices. Belongs to the technical field of industrial control communication.

Description

Dual-channel data communication anti-collision system based on FPGA

Technical Field

The invention relates to a dual-channel data communication anti-collision system based on an FPGA, and belongs to the technical field of industrial control communication.

Background

In the flying process of certain weapon equipment, the inertial measurement front end needs to send the real-time acquisition data of the gyroscopes in the flying process to the on-bullet central control device through the channel A, and meanwhile, the real-time acquisition data of the gyroscopes also need to be sent to ground remote monitoring equipment through the channel B. The method is characterized in that the flight state of the remote guided missile in the flight process is monitored in real time while the remote guidance is realized. The A channel data is collected by the on-board central control device at a timing (4 ms), and the B channel data is sent to the ground remote monitoring equipment at an inertial measurement front end at a timing (4 ms). In order to monitor whether the inertial measurement front end operates normally, whether the dual-channel data communication of the inertial measurement front end A, B is normal is checked before assembly.

The current detection device mainly adopts two modes to detect the receiving A, B channels.

1. And the A, B-channel data are processed in parallel by a two-channel 485 processor, one channel reads the A-channel data at a timing of 4ms, and the other channel passively receives the B-channel data. The two channels send the received data to the PC through the RJ45 interface, and the mode has the problem that the received data is wrong because the two channels have a certain probability of collision.

2. The PC is connected with the front end of the inertial measurement through a high-speed 485 communication card, periodically collects the data of the A channel, simultaneously receives the data of the B channel, and processes the data of the two channels on the PC. However, the PC operation has no hardware timer, only software timing based on Windows operating system can not ensure accurate 4ms timing, and the reliability of the performance detection of the inertial measurement front end is affected to a certain extent.

Disclosure of Invention

The invention provides a dual-channel data communication anti-collision system based on an FPGA (field programmable gate array), which aims to overcome the defects of the current technology and equipment for detecting the performance of the front end of inertial measurement.

In order to achieve the above purpose, such A dual-channel data communication anti-collision system based on an FPGA is to be adopted, the system is composed of A PC, an RJ45 communication module, A DSP, FPGA, RS A communication module and an RS485B communication module, the DSP generates 4ms timed interrupt, the front end data of inertial measurement is extracted at fixed time through the connection 485A port of the FPGA, the front end data of the inertial measurement is received through the connection 485A port of the FPGA, the FPGA is used for realizing A synchronous 485 hardware interface circuit, A1K byte FIFO is built in and used for receiving and buffering the 485B port data, the RJ45 communication module is used for communicating with the PC, and the RS485A communication module and the RS485B communication module are used for communicating with the front end of inertial measurement.

And opening 1K byte FIFO (first in first out) in the FPGA, caching the data in the FIFO when receiving the front end data of inertial measurement, setting a data valid flag, waiting for the DSP to inquire and read, dividing the 4ms timing into 41 ms time slices, extracting 485A port data at the 1 st time slice starting point, inquiring whether the FIFO corresponding to the FPGA receives 485B port data, extracting if the data is received, and only inquiring whether the FIFO corresponding to the FPGA receives 485B port data at the 2 nd, 3 rd and 4 th time slice starting points, and extracting if the data is received.

Compared with the prior art, the invention adopts the FPGA internal FIFO combined with the DSP time slice data polling mechanism, thereby not only realizing the two-channel data communication, but also effectively solving the A, B-channel data collision problem.

Due to the adoption of the technical scheme, the FPGA internal FIFO combines with a DSP time slice data polling mechanism and has the following characteristics:

1. The invention adopts a hardware architecture of combining a DSP and an FPGA, and the DSP and the FPGA are connected through an EMIF bus.

2. The FPGA is internally provided with a 1K byte data FIFO for passively receiving 485B port data, caching the data in the FIFO, setting the valid bit of the received data, and waiting for the DSP to extract.

3. The DSP generates a time slice by adopting a hardware timer, and polls A, B channel data by taking the time slice as a unit.

4. The invention adopts RS485 double channels, wherein one channel adopts an active extraction mode, and the other channel adopts a passive receiving mode.

5. The two parties of the communication equipment adopt the same timing data communication interval, and the characteristics of asynchronous timing starting points exist.

6. The invention has strong universality and is suitable for various hardware interfaces such as RS232, RS485, RS422 and the like.

Drawings

FIG. 1 is a schematic diagram of the system components of the present invention;

FIG. 2 is a schematic diagram of the internal design of an FPGA;

Fig. 3 is a schematic diagram of a DSP time-slice data polling mechanism.

Detailed Description

For the purpose of promoting an understanding of the principles of the invention, reference will now be made in detail to the embodiments described herein, including examples, illustrated in the accompanying drawings.

Examples

Referring to fig. 1 to 3, the present embodiment provides A dual-channel data communication anti-collision system based on FPGA, which is composed of A PC, an RJ45 communication module, A DSP, FPGA, RS A485A communication module, and an RS485B communication module, as shown in fig. 1.

The DSP generates 4ms timing interrupt, and the FPGA is connected with 485A port to extract inertial measurement front end data at fixed time and receive 485B port 4ms data. The FPGA is used for realizing a synchronous 485 hardware interface circuit, is internally provided with a 1K byte FIFO and is used for receiving and caching 485B port data. The RJ45 communication module is used for communicating with the PC. The RS485A communication module and the RS485B communication module are used for communicating with the inertial measurement front end.

The dual-channel communication of the system has the following characteristics and difficulties:

1. since the 4ms timing of the DSP and the 4ms timing of the inertial measurement front end are two relatively independent timing systems, the timing starting points of the two systems are not synchronous, and the timing starting points have randomness.

2. The DSP is connected with the FPGA through an EMIF bus, the data extraction process of the DSP at the 485A port cannot be interrupted, the data receiving process of the DSP at the 485B port cannot be interrupted at regular time, and otherwise, communication data errors can be caused.

3. According to the two points, the problem that the data of the 485B port arrives in the process of extracting the data of the 485A port by the DSP and the two-channel data collision is generated is necessarily existed.

The system adopts the FPGA internal FIFO data caching technology and combines a DSP time slice data polling mechanism to effectively solve the problem of data collision, and the specific implementation method is as follows.

As shown in fig. 2, a 1K byte FIFO is opened in the FPGA, and when receiving the inertial measurement front-end data, the data is cached in the FIFO, and the data valid flag is set, waiting for the DSP to query and read. As shown in fig. 3, the DSP splits the 4ms timing into 41 ms time slices, extracts 485A port data at the start of the 1 st time slice, queries whether the FIFO corresponding to the FPGA receives 485B port data, and extracts the data if the FIFO receives the data. And (3) only inquiring whether the FIFO corresponding to the FPGA receives 485B port data or not at the starting points of the 2 nd, 3 rd and 4 th time slices, and extracting if the data is received.

The FPGA internal FIFO is combined with the DSP time slice data polling mechanism, so that the dual-channel data communication is realized, and the A, B-channel data collision problem is effectively solved.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1.A binary channels data communication anticollision system based on FPGA, its characterized in that: the system consists of A PC, an RJ45 communication module, A DSP, FPGA, RS A communication module and an RS485B communication module, wherein the DSP generates 4ms timed interrupt, the DSP is connected with an RS485A port through an FPGA to extract inertial measurement front end data at fixed time and receive the 4ms data of the RS485B port, the FPGA is used for realizing A synchronous RS485 hardware interface circuit, A1K byte FIFO is built in and used for receiving and caching the data of the RS485B port, the RJ45 communication module is used for communicating with the PC, and the RS485A communication module and the RS485B communication module are used for communicating with the inertial measurement front end; when receiving the front end data of inertial measurement, the FPGA opens 1K byte FIFO, caches the data in the FIFO, sets a data effective mark, waits for the DSP to inquire and read, breaks the 4ms timing into 41 ms time slices, extracts the RS485A port data at the starting point of the 1 st time slice, inquires whether the FIFO corresponding to the FPGA receives the RS485B port data, extracts the RS485B port data if the data is received, inquires only whether the FIFO corresponding to the FPGA receives the RS485B port data at the starting point of the 2 nd, 3 rd and 4 th time slices, and extracts the RS485B port data if the data is received.