CN114285412A - Detection method of N-bit analog-to-digital converter - Google Patents

Abstract

A method of testing an N-bit analog-to-digital converter, the method comprising: selecting continuous M bits of to-be-detected bits according to the requirement of static integral nonlinear errors of the N bits of analog-to-digital converters to be detected, wherein at least one bit of the M bits of to-be-detected bits is a non-precise bit, and determining the judgment condition of the integral nonlinear errors of the M bits of to-be-detected bits, wherein M and N are positive integers, and M is less than N; carrying out integral nonlinear error test on the M bits to be tested; and confirming that the N-bit analog-to-digital converter is qualified in response to the measured integral nonlinear error meeting the judgment condition, and confirming that the N-bit analog-to-digital converter is unqualified in response to the measured integral nonlinear error not meeting the judgment condition.

Description

Detection method of N-bit analog-to-digital converter

Technical Field

The disclosure relates to the technical field of integrated circuit testing, in particular to a detection method of an N-bit analog-to-digital converter.

Background

An Analog-to-Digital converter (ADC), i.e., an a/D converter, is generally referred to as a chip for converting an Analog signal into a Digital signal. The performance test is performed on the chip, and mainly includes dynamic parameters such as signal-to-noise ratio (SNR) and harmonic distortion (THD), and static parameters such as differential nonlinear error (DNL) and integral nonlinear error (INL).

Testing the analog-to-digital converter is one of the most challenging tasks, and the differential non-linearity error (DNL) and the integral non-linearity error (INL) of the analog-to-digital converter are parameters for describing the correctness of each conversion coding in the static characteristics of the analog-to-digital converter, and have a very important role in various application fields. The lengthy test time and expensive test instruments make testing the static characteristics of the high-precision analog-to-digital converter a difficult and costly task.

Disclosure of Invention

Some embodiments of the present disclosure provide a detection method for an N-bit analog-to-digital converter, where the detection method includes:

selecting continuous M bits of to-be-detected bits according to the requirement of static integral nonlinear errors of the N bits of analog-to-digital converters to be detected, wherein at least one bit of the M bits of to-be-detected bits is a non-precise bit, and determining the judgment condition of the integral nonlinear errors of the M bits of to-be-detected bits, wherein M and N are positive integers, and M is less than N;

carrying out integral nonlinear error test on the M bits to be tested;

and confirming that the N-bit analog-to-digital converter is qualified in response to the measured integral nonlinear error meeting the judgment condition, and confirming that the N-bit analog-to-digital converter is unqualified in response to the measured integral nonlinear error not meeting the judgment condition.

In some embodiments, according to the requirement of static integral nonlinear error of an N-bit analog-to-digital converter to be measured, M consecutive bits to be measured are selected, wherein at least one bit of the M bits to be measured is a non-precision bit, and the determination condition for determining the integral nonlinear error of the M bits to be measured includes;

determining the 1 st to J bits from low to high in the N bits as non-precise bits according to the requirement of static integral nonlinear error of the N-bit analog-to-digital converter to be detected;

selecting M as a position to be measured from the J-th position to the I-th position in sequence, wherein the J-th position to the J-th position are used as non-precise positions in the M position to be measured, J is a positive integer, I is a natural number, I is more than J and less than N, and I is more than M; and

determining the judgment condition of the integral nonlinear error of the M positions to be measured as follows:

INL_M<(2^I+1-1)LSB_M

wherein INL_MFor the integral non-linear error, LSB, of the M-bit to-be-detected bit_MThe least significant bit of the bits to be detected is M bits.

In some embodiments, performing the integrated non-linear error test on the M bits under test comprises:

performing integral non-linear error test on the M bits to be tested of the N-bit analog-to-digital converter by using direct-current linear ramp voltage with preset frequency, wherein the voltage range of the ramp voltage is 0-V_MWherein V is_M＝2^M+J-I-1/2^N·V_NWherein V is_NIs the full scale voltage of the N-bit analog-to-digital converter.

In some embodiments, performing the integrated non-linear error test on the M bits under test comprises:

performing integral non-linear error test on the M bits to be tested of the N-bit analog-to-digital converter by using direct-current linear ramp voltage with preset frequency, wherein the voltage range of the ramp voltage is V_J-I～V_MWherein V is_J-I＝2^J-I/2^N·V_N，V_M＝2^M+J-I-1/2^N·V_NWherein V is_NIs the full scale voltage of the N-bit analog-to-digital converter.

In some embodiments, performing the integrated nonlinear error test on the M bits under test further comprises: sampling one or more times for each code in the M-bit positions to be detected.

In some embodiments, performing the integrated nonlinear error test on the M bits under test further comprises: sampling one or more times for each code in the M-bit positions to be detected.

In some embodiments, the integrated nonlinear error INL of the M bits of bits to be measured_MIs determined by the following formula:

wherein the content of the first and second substances,

h(i)_THEORETICALthe number of times of the ith code in the ideal circuit condition, h (i)_THEORETICAL＝MT/(2^M–2)，h(i)_ACTUALIndicates the number of times of the ith code actually occurring, MT indicates the total number of times of acquisition, i is 1,2, … 2^M–2。

Some embodiments of the present disclosure provide a computer-readable storage medium, on which a computer program is stored, wherein the computer program is configured to implement the detection method of the foregoing embodiments when executed by a processor.

Some embodiments of the present disclosure provide an electronic device, including:

one or more processors;

a storage device for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the detection method as described in the preceding embodiments.

Compared with the related art, the scheme of the embodiment of the disclosure has at least the following beneficial effects:

the high-precision analog-to-digital converter is detected by taking part of bits of the high-precision analog-to-digital converter as test bits, so that the high-precision analog-to-digital converter can be quickly detected, and the mass production detection efficiency is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

fig. 1 is a flowchart of a detection method of an N-bit analog-to-digital converter according to some embodiments of the present disclosure;

FIG. 2 is a detailed flowchart of step S10 in FIG. 1;

FIG. 3 is a schematic diagram of binary digits provided by some embodiments of the present disclosure;

FIG. 4 is a graph of test results provided by some embodiments of the present disclosure;

fig. 5 is a block diagram of an electronic device provided in some embodiments of the present disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present disclosure, rather than all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

The terminology used in the embodiments of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in the disclosed embodiments and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and "a plurality" typically includes at least two.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present disclosure, these should not be limited to these terms. These terms are only used to distinguish one from another. For example, a first could also be termed a second, and, similarly, a second could also be termed a first, without departing from the scope of embodiments of the present disclosure.

It is also noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, the recitation of an element by the phrase "comprising a" does not exclude the presence of additional like elements in a commodity or device comprising the element.

The analog-digital converter is a very key component module in the current digital-analog mixed signal and digital signal processing system. With the rapid development of SOC technology and communication industry in recent years, the performance requirements for analog-to-digital converters are also increasing. The pipelined analog-to-digital converter can meet the performance requirements of high speed and high precision at the same time, and is widely applied to various fields, such as radio frequency technology, multimedia data processing, automatic testers and the like. Test time is one of the most important concerns for analog-to-digital converter manufacturers who need to assess the quality of such devices. How to quickly and effectively test the high-speed high-precision analog-to-digital converter not only directly relates to the production period and the service life of the chip, but also indirectly influences the market acceptance of the chip. For a high-speed high-precision analog-to-digital converter chip, the design and process cost of the chip is a large part, and if a sufficiently short test time cannot be ensured in the chip test flow, the total cost is greatly increased. Therefore, in order to improve the reliability of the product and from the viewpoint of test cost, the biggest obstacle at present is to lack an effective fast test method for high-speed and high-precision analog-to-digital converter.

The differential non-linearity error of the related art analog-to-digital converter is defined as a difference between an actual quantization step and an ideal value corresponding to 1LSB, which is the least significant bit of the analog-to-digital converter. For an ideal analog-to-digital converter, the differential nonlinear error DNL is 0LSB (each analog quantization step is equal to LSB V_FSR/2^NIn which V is_FSRFor full scale voltage, N is the analog to digital converterThe interval between transition values is 1 LSB). If the difference nonlinear error index DNL is less than or equal to 1LSB, the transmission function has guaranteed monotonicity and no missing code. The integrated non-linearity error, which represents the degree to which the actual transfer function deviates from a straight line, is measured in percentage of LSB or Full Scale (FSR) and is more truly descriptive of the linearity of the device under test.

The integral nonlinear error test is generally a full code linear test, and the test method is as follows: the method comprises the steps of inputting a full-scale ramp wave with low signal frequency, sampling to obtain an actual digital output signal, and determining an integral nonlinear error result by comparing an actually measured transmission characteristic with an ideal transmission characteristic.

Since the high-precision analog-to-digital converter has more bits, usually more than 20 bits, the code number needs to be at least more than 2^NAnd N is the number of bits of the high-precision analog-to-digital converter. Taking a 24-bit (bit) analog-to-digital converter as an example, the code number needs to be at least greater than 16777216, and the high-precision analog-to-digital converter chip has a relatively low working frequency, usually at tens of Hz, and the conventional integral nonlinear error parameter testing method needs tens of hours, so that the efficiency and cost of mass production testing cannot be borne.

Some embodiments of the present disclosure provide a detection method of an N-bit analog-to-digital converter, the detection method including: selecting continuous M bits of to-be-detected bits according to the static integral nonlinearity requirement of the to-be-detected N-bit analog-to-digital converter, wherein at least one bit of the M bits of to-be-detected bits is a non-precise bit, and determining the integral nonlinearity judgment condition of the M bits of to-be-detected bits, wherein M and N are positive integers, and M is less than N; carrying out integral nonlinear test on the M bits to be tested; and confirming that the N-bit analog-to-digital converter is qualified in response to the measured integral nonlinearity meeting the judgment condition, and confirming that the N-bit analog-to-digital converter is unqualified in response to the measured integral nonlinearity not meeting the judgment condition. The high-precision analog-to-digital converter is detected by taking part of bits of the high-precision analog-to-digital converter as test bits, so that the high-precision analog-to-digital converter can be quickly detected, and the mass production detection efficiency is improved.

Alternative embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Fig. 1 is a flowchart of a detection method of an N-bit analog-to-digital converter according to some embodiments of the present disclosure. As shown in fig. 1, the present disclosure provides a detection method for an N-bit adc, where N is a positive integer and the value of N is generally greater than or equal to 20, i.e., the N-bit adc is a high-precision adc. The detection method comprises the following steps:

s10: selecting continuous M bits of to-be-detected bits according to the requirement of static integral nonlinear errors of the N bits of analog-to-digital converters to be detected, wherein at least one bit of the M bits of to-be-detected bits is a non-precise bit, and determining the judgment condition of the integral nonlinear errors of the M bits of to-be-detected bits, wherein M and N are positive integers, and M is less than N;

s30: carrying out integral nonlinear error test on the M bits to be tested;

s50: determining whether the N-bit analog-to-digital converter is qualified based on whether the measured integrated non-linearity error satisfies the decision condition. And specifically, in response to the measured integral non-linear error meeting the determination condition, the N-bit analog-to-digital converter is determined to be qualified, and in response to the measured integral non-linear error not meeting the determination condition, the N-bit analog-to-digital converter is determined to be unqualified.

Fig. 2 shows a detailed flowchart of step S10 in fig. 1. As shown in fig. 2, step S10 specifically includes the following steps:

s11: determining the 1 st to J bits from low to high in the N bits as non-precise bits according to the requirement of static integral nonlinear error of the N-bit analog-to-digital converter to be detected, wherein J is a positive integer, and J is more than 0 and less than N;

specifically, taking a 24-bit high-precision analog-to-digital converter chip as an example, that is, N is 24, it can be seen from a data sheet (datasheet) of the chip that the full-scale input amplitude of the chip is 5V, under the condition that the operating frequency of the chip is less than 60Hz, the differential nonlinear error requirement is less than or equal to 1LSB, and the integral nonlinear error requirement is "± 0.0015% of FSR", where FSR represents the full-scale.

From this, the integral nonlinear error INL ±. 0.0015% × 2 can be calculated²⁴± 0.0015% × 16777216 ≈ 512 codes. 512 is the power of 2 to the 9 th power, so that the core is obtainedThe slice allows the 1 st bit to the 9 th bit from low to high among the 24 bits to be an imprecise bit. Fig. 3 is a schematic diagram of binary digits provided by some embodiments of the present disclosure, as shown in fig. 3, the 1 st digit to the 24 th digit are sequentially arranged from right to left, and Δ and a-solidup in the diagram represent the digits, that is, each of Δ and a-solidup represents 1 digit, a-represents an inaccurate digit, and Δ represents an accurate digit. As shown in fig. 3, according to the requirement of the integrated nonlinear error of the chip, the 1 st bit to the 9 th bit are non-precise bits and the 10 th bit to the 24 th bit are precise bits among the 24 bits.

S13: and sequentially selecting M bits from the J-th bit to the I-th bit as bits to be detected, wherein the J-th bit to the J-th bit are non-precise bits in the M bits to be detected, J is a positive integer, I is a natural number, I is more than or equal to 0 and less than J and less than N, and I is less than M.

Specifically, the example where I is 1 and M is 8 is explained, and 8 bits are sequentially selected as bits to be measured from the 8 th bit, and as shown in fig. 3, the 8 th bit to the 15 th bit which are framed are bits to be measured. The selection of I and M is based on the actual requirement of the test, the value of I determines the judgment condition of the integral nonlinear error of the subsequently mentioned M bits of to-be-tested bits, and the value of M determines the test time. In other embodiments, I may also be, for example, 0, 2, etc., and M may be, for example, 7, 9, 10, 11, 12, etc.

S15: determining the judgment condition of the integral nonlinear error of the M positions to be measured as follows: INL_M<(2^I+1-1)LSB_MWherein INL_MFor the integral non-linear error, LSB, of the M-bit to-be-detected bit_MThe least significant bit of the bits to be detected is M bits.

Specifically, for the explanation of the example where I is 1 and M is 8, since two non-precision bits, i.e., the 8 th bit and the 9 th bit, and 6 precision bits, i.e., the 10 th bit to the 15 th bit, exist in the 8-bit bits to be measured, the determination condition of the integral nonlinear error of the 8-bit bits to be measured is: INL <3 LSB.

In step S30, in particular, in some embodiments, the M bits to be tested of the N-bit analog-to-digital converter are subjected to an integral non-linear error test using a dc linear ramp voltage with a predetermined frequency, wherein the voltage range of the ramp voltage is V_J-I～V_MWherein V is_J-I＝2^J-I/2^N·V_N，V_M＝2^M+J-I-1/2^N·V_NWherein V is_NThe full scale voltage of the N-bit analog-to-digital converter is, for example, 5V, thereby making it possible for the test result (pass/fail) of the M-bit to-be-tested bit to be equivalent to the test result (pass/fail) of the N-bit analog-to-digital converter.

Taking a 24-bit high-precision analog-to-digital converter chip as an example, where N is 24, M is 8, and I is 1, for example, an integral nonlinear error test is performed on the 8-bit to-be-measured bit of the high-precision analog-to-digital converter chip by using a dc linear ramp voltage with a predetermined frequency, the frequency of the ramp voltage is 60Hz, for example, and the voltage range of the ramp voltage is 0.015mV to 9.8 mV.

In some embodiments, the M bits to be tested of the N-bit analog-to-digital converter are subjected to an integral non-linear error test using a dc linear ramp voltage having a predetermined frequency, wherein the voltage range of the ramp voltage is 0-V_MWherein V is_M＝2^M+J-I-1/2^N·V_NWherein V is_NIs the full scale voltage of the N-bit analog-to-digital converter. Due to V_J-IIs very small, the starting point of the ramp voltage can be set to 0, 0 to V_J-ICorresponding to the voltages from the 1 st bit to the J-I-1 st bit, the 1 st bit to the J-I-1 st bit are discarded non-detection bits.

Taking a 24-bit high-precision analog-to-digital converter chip as an example, where N is 24, M is 8, and I is 1, for example, an integral nonlinear error test is performed on the 8-bit to-be-measured bit of the high-precision analog-to-digital converter by using a dc linear ramp voltage with a predetermined frequency, the frequency of the ramp voltage is 60Hz, for example, and the voltage range of the ramp voltage is 0 to 9.8 mV. In consideration of actual test conditions, the maximum value of the ramp voltage to be used is usually slightly enlarged to ensure that the test requirements are met, for example, the voltage range of the ramp voltage is 0-10 mV.

In some embodiments, each code in the M bits of bits to be detected is sampled one or more times. For example, a digitizer is used to acquire a digital signal output by a chip, each code uses, for example, 12 samples, when M is 8, the number of codes (codes) is 256, and the total number of samples is 3072, and it takes about 52 seconds to complete a test of one chip. Compared with the full code test of the chip, when the number of the codes is 16777216 when the number of the codes is 24, even if each code collects 1 sample, the test time for completing one chip is about 77 hours, and therefore, the test efficiency of the high-precision analog-to-digital converter chip can be obviously improved by adopting the method disclosed by the invention.

In step S50, it is determined whether the N-bit analog-to-digital converter is qualified by, for example, a chip tester collecting the chip output digital signal through a digitizer.

Fig. 4 is a test result chart provided by some embodiments of the present disclosure, which takes a test of a 24-bit high-precision analog-to-digital converter chip as an example, where N is 24, M is 8, J is 9, and I is 1. As shown in fig. 4 (a), when the test waveform output by the chip under test is substantially a continuous slope and is substantially a continuous step after amplification, the INL value measured is 1.7385LBS, which meets the determination condition of integral non-linear error: INL <3LSB, so the high precision analog to digital converter chip can be considered to be acceptable. As shown in fig. 4 (B), when the test waveform output by the tested chip is discontinuous, its measured INL value is 121.475LBS, which does not meet the determination condition of integral non-linear error: INL <3LSB, so the high precision analog to digital converter chip can be considered to be rejected.

The following describes in detail the testing principles of differential nonlinear error (DNL) and integral nonlinear error (INL), and the linear ramp histogram testing method is used to test the differential nonlinear error (DNL) and the integral nonlinear error (INL). An ascending or descending linear ramp wave is input at the analog input end of the analog-to-digital converter, the analog-to-digital converter is used for collecting the linear ramp wave at a fixed sampling rate, and because each code has the same occurrence probability, the occurrence frequency of each code should be as many as the occurrence frequency of each code under the ideal condition (except for two ends). The occurrence frequency of each code is drawn into a histogram, and the code occurrence frequency is high, which indicates that the quantization step is wide, otherwise, the code occurrence frequency is narrow.

The total number of times of acquisition is represented by MT (except the two ends), the number of times of generation of the ith code is represented by h (i), and i is 1,2, … 2^M-2, M being the number of consecutive test bits. For generating ith code in ideal circuit conditionNumber of times h (i)_THEORETICAL＝MT/(2^M-2). If used with h (i)_ACTUALRepresenting the actual number of occurrences of the ith code, the differential nonlinear error DNL can be calculated using the following equation:

integral non-linear error INL_MObtained by accumulating DNL;

the disclosed embodiments provide a non-volatile computer storage medium having stored thereon computer-executable instructions that may perform the method steps as described in the embodiments above.

The present disclosure provides a computer program product comprising a computer program which, when executed by a processor, implements the method as described in the above embodiments.

As shown in fig. 5, the present embodiment provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the one processor to cause the at least one processor to perform the method steps of the above embodiments.

Referring now to FIG. 5, shown is a schematic diagram of an electronic device suitable for use in implementing embodiments of the present disclosure. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., car navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 5 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 5, the electronic device may include a processing means (e.g., central processing unit, graphics processor, etc.) 501 that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)502 or a program loaded from a storage means 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data necessary for the operation of the electronic apparatus are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.

Generally, the following devices may be connected to the I/O interface 505: input devices 506 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 5011 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, and the like; storage devices 508 including, for example, magnetic tape, hard disk, etc.; and a communication device 509. The communication means 509 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. While fig. 5 illustrates an electronic device having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.

In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 509, or installed from the storage means 508, or installed from the ROM 502. The computer program performs the above-described functions defined in the methods of the embodiments of the present disclosure when executed by the processing device 501.

It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.

The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Finally, it should be noted that: the embodiments are described by way of example, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The system or the device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The above examples are only intended to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims (9)

1. A method for detecting an N-bit analog-to-digital converter, the method comprising:

selecting continuous M bits of to-be-detected bits according to the requirement of static integral nonlinear errors of the N bits of analog-to-digital converters to be detected, wherein at least one bit of the M bits of to-be-detected bits is a non-precise bit, and determining the judgment condition of the integral nonlinear errors of the M bits of to-be-detected bits, wherein M and N are positive integers, and M is less than N;

carrying out integral nonlinear error test on the M bits to be tested;

and confirming that the N-bit analog-to-digital converter is qualified in response to the measured integral nonlinear error meeting the judgment condition, and confirming that the N-bit analog-to-digital converter is unqualified in response to the measured integral nonlinear error not meeting the judgment condition.

2. The detection method according to claim 1, wherein continuous M bits of the bits to be detected are selected according to the requirement of static integral nonlinear error of the N bits of analog-to-digital converter to be detected, wherein at least one bit of the M bits of the bits to be detected is a non-precision bit, and the determination condition for determining the integral nonlinear error of the M bits of the bits to be detected comprises;

determining the 1 st to J bits from low to high in the N bits as non-precise bits according to the requirement of static integral nonlinear error of the N-bit analog-to-digital converter to be detected;

selecting M bits as bits to be detected from the J-th to I bits in sequence, wherein the J-th to J-th bits are used as non-precise bits in the M bits to be detected, J is a positive integer, I is a natural number, I is more than J and less than N, and I is more than M; and

determining the judgment condition of the integral nonlinear error of the M positions to be measured as follows:

INL_M<(2^I+1-1)LSB_M

wherein INL_MFor the integral non-linear error, LSB, of the M-bit to-be-detected bit_MThe least significant bit of the bits to be detected is M bits.

3. The detection method according to claim 1 or 2, wherein performing an integral non-linear error test on the M bits under test comprises:

performing integral non-linear error test on the M bits to be tested of the N-bit analog-to-digital converter by using direct-current linear ramp voltage with preset frequency, wherein the voltage range of the ramp voltage is 0-V_MWherein V is_M＝2^M+J-I-1/2^N·V_NWherein V is_NIs the full scale voltage of the N-bit analog-to-digital converter.

4. The detection method according to claim 1 or 2, wherein performing an integral non-linear error test on the M bits under test comprises:

performing integral non-linear error test on the M bits to be tested of the N-bit analog-to-digital converter by using direct-current linear ramp voltage with preset frequency, wherein the voltage range of the ramp voltage is V_J-I～V_MWherein V is_J-I＝2^J-I/2^N·V_N，V_M＝2^M+J-I-1/2^N·V_NWherein V is_NIs the full scale voltage of the N-bit analog-to-digital converter.

5. The detection method of claim 3, wherein performing an integral non-linear error test on the M bits under test further comprises: sampling one or more times for each code in the M-bit positions to be detected.

6. The detection method of claim 4, wherein performing an integral non-linear error test on the M bits under test further comprises: sampling one or more times for each code in the M-bit positions to be detected.

7. The detection method according to claim 2, wherein the integrated nonlinear error INL of the M bits of bits to be detected_MIs determined by the following formula:

wherein the content of the first and second substances,

h(i)_THEORETICALthe number of times of the ith code in the ideal circuit condition, h (i)_THEORETICAL＝MT/(2^M–2)，h(i)_ACTUALIndicates the number of times of the ith code actually occurring, MT indicates the total number of times of acquisition, i is 1,2, … 2^M–2。

8. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the detection method according to any one of claims 1 to 7.

9. An electronic device, comprising:

one or more processors;

storage means for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the detection method of any one of claims 1 to 7.

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