CN114285293A - Mathematical modeling method and device for topological structure, storage medium and electronic equipment - Google Patents
Mathematical modeling method and device for topological structure, storage medium and electronic equipment Download PDFInfo
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Abstract
The invention discloses a mathematical modeling method and device of a topological structure, a storage medium and electronic equipment. Wherein, the method comprises the following steps: acquiring a charge-discharge state formed between the master circuit and the slave circuit; determining a plurality of switch states of the plurality of switches according to the charge and discharge states; determining a plurality of state space expressions corresponding to the topology based on a plurality of switch states; and calculating to obtain the state space model of the topological structure through a plurality of state space expressions. The invention solves the technical problems of overlarge current stress, low fault tolerance and low working efficiency of the converter caused by the fact that the number of loops of a topological structure of the interleaved converter in the prior art is small and the complete offset of output ripples can be realized only under a specific duty ratio.
Description
Technical Field
The invention relates to the technical field of mathematical modeling, in particular to a mathematical modeling method and device of a topological structure, a storage medium and electronic equipment.
Background
The topological structure of the interleaved converter in the prior art mainly comprises a traditional two-phase interleaved buck converter, a single-phase stacked interleaved converter and the like, as shown in fig. 1 and fig. 2, the topological structure respectively controls the charging state or the discharging state of an inductor through each switch, although the model structure is simple, the number of loops is small, when any bridge arm circuit fails, the whole interleaved converter cannot normally work, and the fault tolerance is low; and the partially staggered converter can only realize the complete offset of output ripple under a specific duty ratio, the current stress is overlarge, the applicability is poor, and the working efficiency of the converter is low.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a mathematical modeling method, a mathematical modeling device, a mathematical modeling storage medium and electronic equipment for a topological structure, which are used for at least solving the technical problems of overlarge current stress, low fault tolerance and low working efficiency of a converter caused by the fact that the number of loops of the topological structure of an interleaved converter in the prior art is small and the output ripple can only be completely offset under a specific duty ratio.
According to an aspect of the embodiments of the present invention, there is provided a mathematical modeling method for a topology, the topology at least including: the bridge arm circuit comprises main loops, slave loops and bridge arm circuits, wherein the main loops are connected in parallel, each slave loop is connected with a capacitor in series, each bridge arm circuit is provided with a plurality of switches, and the bridge arm circuit comprises: acquiring a charge-discharge state formed between the master circuit and the slave circuit; determining a plurality of switch states of the plurality of switches according to the charge and discharge states; determining a plurality of state space expressions corresponding to the topology based on a plurality of switch states; and calculating to obtain the state space model of the topological structure through a plurality of state space expressions.
Optionally, the method is applied to a topology structure of a three-phase stacked interleaved converter, the master circuit includes a first master circuit Lp1, a second master circuit Lp2 and a third master circuit Lp3, the slave circuit includes a first slave circuit Ls1, a second slave circuit Ls2 and a third slave circuit Ls3, and the charging and discharging states include a first charging and discharging state, a second charging and discharging state, a third charging and discharging state and a fourth charging and discharging state, wherein the first charging and discharging state is Lp1 charging, Lp2, Lp3 discharging, Ls1 discharging, Ls2, Ls3 charging; the second charge-discharge state is Lp2 charge, Lp1 and Lp3 discharge, Ls2 discharge and Ls1 and Ls3 charge; the third charge-discharge state is Lp3 charge, Lp1 and Lp2 discharge, Ls3 discharge and Ls1 and Ls2 charge; the fourth charge-discharge state is discharge of Lp1, Lp2 and Lp3, and charge of Ls1, Ls2 and Ls 3.
Optionally, the bridge arm circuits include a first bridge arm circuit, a second bridge arm circuit, and a third bridge arm circuit, where the first bridge arm circuit is provided with a first switch S11A second switch S21And a third switch S31The second bridge arm circuit is provided with a fourth switch S12The fifth switch S22And a sixth switch S32A seventh switch S is arranged on the third bridge arm circuit13The eighth switch S23And a ninth switch S33Wherein the switch state of the switch is determined according to the charge and discharge state, and the packageComprises the following steps: determining the S when the charge-discharge state is the first charge-discharge state11、S32、S23The switch is in an open state, and the other switches are in a closed state; determining the S when the charge-discharge state is the second charge-discharge state21、S12、S33The switch is in an open state, and the other switches are in a closed state; determining the S when the charge-discharge state is the third charge-discharge state31、S22、S13The switch is in an open state, and the other switches are in a closed state; determining the S when the charge/discharge state is the fourth charge/discharge state21、S22、S23And the other switches are in the closed state.
Optionally, the state space expression:
wherein A isjA state matrix, which is related to inductance parameters and capacitance parameters in the topological structure and is used for representing the connection state of the topological structure; b isjAn input matrix associated with said charge and discharge states, each of said charge and discharge states corresponding to one of said input matrices; vinIs the supply voltage; x is a current-voltage matrix, wherein the current-voltage matrix at least comprises: a master loop current, a slave loop current, and a capacitor voltage.
Optionally, the calculating, through a plurality of state space expressions, to obtain the state space model of the topological structure includes: determining a duty ratio corresponding to the topological structure; determining the duration of each of the charge and discharge states according to the duty cycle; and calculating to obtain the state space model based on the duration and the plurality of state space expressions.
Optionally, the method further includes: judging whether a fault bridge arm circuit exists in the topological structure; and if the topological structure is detected to have the fault bridge arm circuit, the topological structure continues to work normally after the fault bridge arm circuit is removed.
Optionally, the method further includes: determining a duty ratio corresponding to the topological structure; inputting the duty ratio and the state space model into an MATLAB simulation model; and carrying out MATLAB simulation processing on the state space model to obtain a simulation image, wherein the simulation image is used for verifying the accuracy and the actual parameter performance of the topological structure.
According to another aspect of the embodiments of the present invention, there is also provided a mathematical modeling apparatus for a topological structure, where the topological structure at least includes: the bridge arm circuit comprises a main loop, a slave loop and bridge arm circuits, wherein a plurality of main loops are connected in parallel, each slave loop is connected with a capacitor in series, each bridge arm circuit is provided with a plurality of switches, and the bridge arm circuit comprises: an acquisition module configured to acquire a charge/discharge state formed between the master circuit and the slave circuit; a first determining module, configured to determine multiple switch states of the switches according to the charge and discharge states; a second determining module, configured to determine, based on a plurality of switch states, a plurality of state space expressions corresponding to the topology; and the calculation module is used for calculating to obtain the state space model of the topological structure through a plurality of state space expressions.
According to another aspect of the embodiments of the present invention, there is also provided a non-volatile storage medium storing a plurality of instructions, the instructions being adapted to be loaded by a processor and to perform any one of the above mathematical modeling methods for a topology.
According to another aspect of the embodiments of the present invention, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform any one of the above mathematical modeling methods for a topological structure.
In the embodiment of the invention, a mathematical modeling mode of a topological structure is adopted, and a charge-discharge state formed between the main loop and the auxiliary loop is obtained; determining a plurality of switch states of the plurality of switches according to the charge and discharge states; determining a plurality of state space expressions corresponding to the topology based on a plurality of switch states; the state space model of the topological structure is obtained through calculation through a plurality of state space expressions, the state space model of the multiphase stacked interleaved converter topological structure is built, and the purpose of simplifying the converter model structure is achieved, so that the technical effects of improving the working efficiency of the converter and the current stress of the topological structure and reducing the fault tolerance are achieved, and the technical problems of overlarge current stress, low fault tolerance and low working efficiency of the converter caused by the fact that the number of loops of the topological structure of the interleaved converter in the prior art is small, and the complete offset of output ripples can be realized only under a specific duty ratio are solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic circuit diagram of a conventional two-phase interleaved buck converter according to the prior art;
FIG. 2 is a schematic circuit diagram of a single-phase stacked interleaved converter according to the prior art;
FIG. 3 is a flow chart of a method of mathematical modeling of a topology according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a topology of a three-phase stacked interleaved converter according to an embodiment of the invention;
FIG. 5 is a schematic diagram of an alternative three-term stacked interleaved converter topology according to an embodiment of the present invention;
FIG. 6a is a schematic diagram of a topology of a three-phase stacked interleaved converter in a first charge-discharge state according to an embodiment of the present invention;
FIG. 6b is a schematic diagram of a topology of a three-phase stacked interleaved converter in a second charging/discharging state according to an embodiment of the invention
FIG. 6c is a schematic diagram of a topology of a three-phase stacked interleaved converter in a third charge-discharge state according to an embodiment of the present invention;
FIG. 6d is a schematic diagram of a topology of a three-phase stacked interleaved converter in a fourth charge-discharge state according to an embodiment of the present invention;
FIG. 7 is a flow diagram of an alternative method of mathematical modeling of a topology in accordance with an embodiment of the present invention;
FIG. 8 is a schematic diagram of a topology of a two-phase stacked interleaved converter according to an embodiment of the invention;
FIG. 9a is a schematic diagram of a topology of a two-phase stacked interleaved converter in a fifth charge-discharge state according to an embodiment of the present invention;
FIG. 9b is a schematic diagram of a topology of a two-phase stacked interleaved converter in a sixth charging/discharging state according to an embodiment of the invention
FIG. 9c is a schematic diagram of a topology of a two-phase stacked interleaved converter in a fifth charge-discharge state according to an embodiment of the invention;
FIG. 10a is a schematic diagram of an alternative MATLAB simulation model in accordance with an embodiment of the present invention;
FIG. 10b is a simulated graph of an alternative three-phase stacked interleaved converter according to an embodiment of the invention;
FIG. 10c is a simulation of an alternative two-phase stacked interleaved converter in accordance with embodiments of the invention;
fig. 11 is a schematic structural diagram of a mathematical modeling apparatus for a topology according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
The topological structure of the interleaved converter in the prior art mainly comprises a traditional two-phase interleaved buck converter, a single-phase stacked interleaved converter and the like, wherein the traditional two-phase interleaved buck converter (as shown in fig. 1) has the advantages that the inductances on two branches are charged and discharged in an interleaved manner, the ripple of output current can be completely eliminated only under the condition that the duty ratio is 50%, and the partial cancellation of the ripple can be realized only under other duty ratios, so that the working efficiency of the converter is influenced to a certain extent; the stacked interleaved converter (as shown in fig. 2) has a capacitor connected in series to a loop of the conventional two-phase interleaved parallel converter, so that the ripple cancellation with the duty ratio of 0 to 100% can be realized, but the current flowing through the inductor of the main loop is increased and equal to the load current, and the current stress on the switch is increased, so that the working efficiency of the converter is greatly reduced.
Therefore, for the staggered parallel buck converter, four switches of two bridge arms are adopted, and due to the staggered conduction of the switches, the converter can completely offset output ripples only under the condition that the duty ratio is 50%, so that the limitation of the converter is very large, and the working efficiency is greatly reduced; for the stacked interleaved converter, two bridge arms and four switches are also adopted, and direct current of a slave loop is isolated due to the existence of a slave loop capacitor, so that current flowing through a main loop is equal to load current, the stress of the current flowing through the four switches is increased, and the efficiency is greatly reduced; meanwhile, when one bridge arm fails, the topological structure is invalid, so that the limitation is still large.
In view of the foregoing, it should be noted that the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
Fig. 3 is a flowchart of a mathematical modeling method of a topology according to an embodiment of the present invention, as shown in fig. 3, the topology at least includes: the bridge arm circuit comprises main loops, slave loops and bridge arm circuits, wherein the main loops are connected in parallel, each slave loop is connected with a capacitor in series, and each bridge arm circuit is provided with a plurality of switches, and the method comprises the following steps:
step S102, acquiring a charge-discharge state formed between the main loop and the auxiliary loop;
step S104, determining a plurality of switch states of the switches according to the charge and discharge states;
step S106, determining a plurality of state space expressions corresponding to the topological structure based on a plurality of switch states;
and step S108, calculating to obtain a state space model of the topological structure through a plurality of state space expressions.
In the embodiment of the invention, a mathematical modeling mode of a topological structure is adopted, and a charge-discharge state formed between the main loop and the auxiliary loop is obtained; determining a plurality of switch states of the plurality of switches according to the charge and discharge states; determining a plurality of state space expressions corresponding to the topology based on a plurality of switch states; the state space model of the topological structure is obtained through calculation through a plurality of state space expressions, the state space model of the multiphase stacked interleaved converter topological structure is built, and the purpose of simplifying the converter model structure is achieved, so that the technical effects of improving the working efficiency of the converter and the current stress of the topological structure and reducing the fault tolerance are achieved, and the technical problems of overlarge current stress, low fault tolerance and low working efficiency of the converter caused by the fact that the number of loops of the topological structure of the interleaved converter in the prior art is small, and the complete offset of output ripples can be realized only under a specific duty ratio are solved.
Optionally, the topology structure may be applied to, but not limited to, a buck circuit, a boost circuit, and a z-source conversion circuit, so as to achieve the purpose of effectively improving the working efficiency of the converter.
Optionally, fig. 4 is a schematic diagram of a topology structure of an optional multi-phase stacked interleaved converter according to an embodiment of the present invention, as shown in fig. 4, the topology structure includes (2n +2) master loops, (2n +2) slave loops, and (2n +2) bridge arm circuits, where a plurality of the master loops are connected in parallel, each of the slave loops is connected in series with a capacitor, and each of the bridge arm circuits is provided with 3 switches.
It should be noted that, in the topology structure, since the plurality of main circuits are connected in parallel, the total output current is shunted, and a large current output result can be obtained, so that the average current flowing through the inductor is reduced, and the current stress flowing through each switch is also reduced; meanwhile, the fault tolerance of the circuit is improved, and when one bridge arm circuit breaks down, other bridge arm circuits can continue to work, so that the aim of improving the working efficiency of multi-phase stacking and staggering is fulfilled.
The embodiment of the invention can at least realize the following technical effects: the complete offset of output current ripples within a certain duty ratio range is realized; meanwhile, as a plurality of main loops are arranged, the shunting function can be realized, so that the current stress flowing through each switching tube can be reduced, and the output of large current is realized; the fault tolerance of the circuit is improved, and therefore the working efficiency of the converter is greatly improved.
In an alternative embodiment, the method is applied to a topology structure of a three-phase stacked interleaved converter, the master loop includes a first master loop Lp1, a second master loop Lp2 and a third master loop Lp3, the slave loop includes a first slave loop Ls1, a second slave loop Ls2 and a third slave loop Ls3, the charging and discharging states include a first charging and discharging state, a second charging and discharging state, a third charging and discharging state and a fourth charging and discharging state, wherein: the first charge-discharge state is that Lp1 is charged, Lp2 and Lp3 are discharged, Ls1 is discharged, and Ls2 and Ls3 are charged; the second charge-discharge state is Lp2 charge, Lp1 and Lp3 discharge, Ls2 discharge and Ls1 and Ls3 charge; the third charge-discharge state is Lp3 charge, Lp1 and Lp2 discharge, Ls3 discharge and Ls1 and Ls2 charge; the fourth charge-discharge state is discharge of Lp1, Lp2 and Lp3, and charge of Ls1, Ls2 and Ls 3.
In addition, the first master circuit Lp1, the second master circuit Lp2, and the third master circuit Lp3 have a one-to-one correspondence relationship with the first slave circuit Ls1, the second slave circuit Ls2, and the third slave circuit Ls3, and when the master circuits are in a charging state, the corresponding slave circuits are in a discharging state; similarly, when the master loop is in the discharging state, the corresponding slave loop is in the charging state, and the complete elimination of the current ripple can be realized only in this way.
As an alternative embodiment, fig. 5 is a schematic diagram of a topology structure of an alternative three-item stacked interleaved converter according to an embodiment of the present invention, as shown in fig. 5, in the topology structure, the master loop includes a first master loop Lp1, a second master loop Lp2, and a third master loop Lp3, the slave loop includes a first slave loop Ls1, a second slave loop Ls2, and a third slave loop Ls3, wherein the bridge arm circuit includes a first bridge arm circuit, a second bridge arm circuit, and a third bridge arm circuit, and the first bridge arm circuit is provided with a first switch S11A second switch S21And a third switch S31The second bridge arm circuit is provided with a fourth switch S12The fifth switch S22And a sixth switch S32A seventh switch S is arranged on the third bridge arm circuit13The eighth switch S23And a ninth switch S33The sequence of the nine switches is
It should be noted that, in the process of analyzing the switch states, in consideration of the problem of switch sharing and the problem that switches on the same bridge arm circuit cannot be turned off at the same time, it can be obtained that the three main circuits in the topology structure cannot be charged at the same time, and then four effective charge and discharge states, that is, the first charge and discharge state, the second charge and discharge state, the third charge and discharge state, the fourth charge and discharge state, and the switch state and the state space expression corresponding to each charge and discharge state are obtained.
In an optional embodiment, determining the switch state of the switch according to the charge and discharge state includes:
step S202, when the charge-discharge state is the first charge-discharge state, determining the S11、S32、S23And the other switches are in the closed state.
Alternatively, as shown in fig. 6a, when the charge-discharge state is the first charge-discharge state, Lp1 is charged, Lp2 and Lp3 are discharged, Ls1 is discharged, and Ls2 and Ls3 are charged; the switch state at this time is
Namely, it is determined that the above S11, S32, S23 are in the open state, and the remaining switches are in the closed state.
In an optional embodiment, determining the switch state of the switch according to the charge and discharge state includes:
step S204, when the charge-discharge state is the second charge-discharge state, determining the S21、S12、S33And the other switches are in the closed state.
Alternatively, as shown in fig. 6b, when the charge-discharge state is the second charge-discharge state, Lp2 is charged, Lp1 and Lp3 are discharged, Ls2 is discharged, and Ls1 and Ls3 are charged; the switch state at this time is
Namely, determining the above S21、S12、S33In an open state, the other switches are in a closed state。
In an optional embodiment, determining the switch state of the switch according to the charge and discharge state includes:
step S206, when the charge-discharge state is the third charge-discharge state, determining the S31、S22、S13And the other switches are in the closed state.
Alternatively, as shown in fig. 6c, when the charge-discharge state is the third charge-discharge state, Lp3 is charged, Lp1 and Lp2 are discharged, Ls3 is discharged, and Ls1 and Ls2 are charged; the switch state at this time is
Namely, determining the above S31、S22、S13And the other switches are in the closed state.
In an optional embodiment, determining the switch state of the switch according to the charge and discharge state includes:
step S208, when the charge-discharge state is the fourth charge-discharge state, determining the S21、S22、S23And the other switches are in the closed state.
Alternatively, as shown in fig. 6d, when the charge-discharge state is the fourth charge-discharge state, Lp1, Lp2 and Lp3 are discharged, and Ls1, Ls2 and Ls3 are charged; the switch state at this time is
Namely, determining the above S21、S22、S23And the other switches are in the closed state.
In an alternative embodiment, the above state space expression:
wherein A isjIs a state matrix, and is involved in the inductance in the topology structureThe number is related to the capacitance parameter and is used for representing the connection state of the topological structure; b isjAn input matrix associated with said charge and discharge states, each of said charge and discharge states corresponding to one of said input matrices; vinIs the supply voltage; x is a current-voltage matrix, wherein the current-voltage matrix at least comprises: a master loop current, a slave loop current, and a capacitor voltage.
It should be noted that each charge-discharge state has a different state space expression, and that different topologies correspond to different state space expressions, i.e. to different state matrices ajInput matrix BjAnd a current-voltage matrix x. Taking the topology structure of the three-phase stacked interleaved converter as an example, the state space expression corresponding to the topology structure can be expressed as
Wherein the content of the first and second substances,
j is 1,2,3,4 respectively corresponding to four charge and discharge states, and different charge and discharge states have different state matrixes AjInput matrix BjWherein, the above ip1、ip2、ip3Respectively representing the current values of the three main circuits, is1、is2、is3Respectively representing the current values of the three slave circuits, VCs1、VCs2、VCs3Respectively representing the values of the capacitor voltages on the three slave loops, said VC0Representing the load capacitor voltage value.
Optionally, when the charge-discharge state is the first charge-discharge state, the state matrix a1Input matrix B1Can be expressed as:
wherein L isp1、Lp2、Lp3Respectively on three main circuitsThe inductance value of (1), above Ls1、Ls2、Ls3Respectively representing the inductance values of the three slave loops, Cs1、Cs2、Cs3Respectively representing the capacitance values on the three slave loops, C0Represents a load capacitance value, R0Representing the load resistance value.
Optionally, when the charge-discharge state is the second charge-discharge state, the state matrix a2Input matrix B2Can be expressed as:
wherein L isp1、Lp2、Lp3Respectively, the inductance values of the three main loops, Ls1、Ls2、Ls3Respectively representing the inductance values of the three slave loops, Cs1、Cs2、Cs3Respectively representing the capacitance values on the three slave loops, C0Represents a load capacitance value, R0Representing the load resistance value.
Optionally, when the charge-discharge state is the third charge-discharge state, the state matrix a3Input matrix B3Can be expressed as:
wherein L isp1、Lp2、Lp3Respectively, the inductance values of the three main loops, Ls1、Ls2、Ls3Respectively representing the inductance values of the three slave loops, Cs1、Cs2、Cs3Respectively representing the capacitance values on the three slave loops, C0Represents a load capacitance value, R0Representing the load resistance value.
Optionally, when the charge-discharge state is the fourth charge-discharge state, the state matrix a4Input matrix B4Can be expressed as:
wherein L isp1、Lp2、Lp3Respectively, the inductance values of the three main loops, Ls1、Ls2、Ls3Respectively representing the inductance values of the three slave loops, Cs1、Cs2、Cs3Respectively representing the capacitance values on the three slave loops, C0Represents a load capacitance value, R0Representing the load resistance value.
As an alternative embodiment, fig. 7 is a flowchart of an alternative mathematical modeling method for a topological structure according to an embodiment of the present invention, and as shown in fig. 7, a state space model of the topological structure is obtained through calculation by using a plurality of state space expressions, where the method includes:
step S302, determining the duty ratio corresponding to the topological structure;
step S304, determining the duration of each charge-discharge state according to the duty ratio;
step S306, calculating the state space model based on the duration and the plurality of state space expressions.
Optionally, still taking the topology structure of the three-phase stacked interleaved converter as an example, determining that the duty ratio corresponding to the topology structure is D, the duration times of the four charging and discharging states are DT, (1-3D) T, respectively, substituting the duration times into state space expressions corresponding to the four charging and discharging states, calculating an average value of the four state space expressions, and obtaining a state space model
Wherein:
the above state space model
Wherein L isp1、Lp2、Lp3Respectively, the inductance values of the three main loops, Ls1、Ls2、Ls3Respectively representing the inductance values of the three slave loops, Cs1、Cs2、Cs3Respectively representing the capacitance values on the three slave loops, C0Represents a load capacitance value, R0Representing the load resistance value.
In an optional embodiment, the method further includes:
step S402, judging whether a fault bridge arm circuit exists in the topological structure;
and S404, if the topological structure is detected to have the fault bridge arm circuit, the topological structure continues to work normally after the fault bridge arm circuit is removed.
Optionally, still taking the topology structure of the three-phase stacked interleaved converter as an example, in a working period, four switching states (i.e., charging and discharging states) are cyclically switched, so that three-phase stacked interleaving can be realized; when any one of the three bridge arm circuits fails, the topological structure of the three-phase stacked interleaved converter can be changed into the topological structure of the two-phase stacked interleaved converter for continuous use, and the fault tolerance of the topological structure is reflected. For example, if a third bridge arm circuit in the topology structure of the three-phase stacked interleaved converter fails, a master loop and a slave loop related to the third bridge arm circuit are eliminated, as shown in fig. 8, the topology structure includes two master loops, two slave loops, and two bridge arm circuits, i.e., a first bridge arm circuit and a second bridge arm circuit, where the first bridge arm circuit is provided with a first switch S11A second switch S21And a third switch S31The second bridge arm circuit is provided with a fourth switch S12The fifth switch S22And a sixth switch S32The sequence of the six switches is
Optionally, the topology structure of the two-phase stacked interleaved converter includes three charge and discharge states, namely a fifth charge and discharge state, a sixth charge and discharge state, and a seventh charge and discharge state, where different charge and discharge states correspond to different switch states, so as to obtain different state space expressions.
Optionally, fig. 9a is a schematic diagram of a topology structure of a two-phase stacked interleaved converter in a fifth charge-discharge state, and as shown in fig. 9a, when the charge-discharge state of the topology structure is the fifth charge-discharge state, a switch state corresponding to the topology structure is a switch state
At this time, L21 was charged and L22 was discharged; l11 discharge, L12 charge, state space expression is
Wherein the content of the first and second substances,
optionally, fig. 9b is a schematic diagram of a topology structure of the two-phase stacked interleaved converter in a sixth charging and discharging state, and as shown in fig. 9b, when the charging and discharging state of the topology structure is the sixth charging and discharging state, the switch state corresponding to the topology structure is the sixth charging and discharging state
At this time, L22 was charged and L21 was discharged; l12 Electricity, L11 Charge, State space expression
Wherein the content of the first and second substances,
optionally, fig. 9c is a schematic diagram of a topology structure of the two-phase stacked interleaved converter in a seventh charge-discharge state, and as shown in fig. 9b, when the charge-discharge state of the topology structure is a sixth charge-discharge state, a switch state corresponding to the topology structure is a switch state
At this time, L21 was charged and L22 was discharged; l11 discharge, L12 charge, state space expression is
Wherein the content of the first and second substances,
optionally, it is determined that the duty ratio corresponding to the topology is D, and the durations of the fifth charge-discharge state, the sixth charge-discharge state, and the seventh charge-discharge state are DT, (1-2D) T, respectively, where T is a period, and based on three durations, an average value of each state space expression is calculated, so as to obtain a state space model, where:
the above state space model
In an optional embodiment, the method further includes:
step S502, determining the duty ratio corresponding to the topological structure;
step S504, inputting the duty ratio and the state space model into an MATLAB simulation model;
step S506, performing MATLAB simulation on the state space model to obtain a simulation image, where the simulation image is used to verify the accuracy and the actual parameter performance of the topology structure.
Alternatively, the actual parametric performance may include, but is not limited to, current ripple.
Optionally, a preset duty ratio (e.g., D ═ 0.17) and the state space model are input to the MATLAB simulation model shown in fig. 10a, and related parameters are taken in to perform MATLAB simulation processing on the state space model, so as to obtain a simulation image corresponding to the state space model, for example, fig. 10b and 10c respectively show a first simulation image corresponding to the state space model of the three-phase stacked interleaved converter and a second simulation image corresponding to the state space model of the two-phase stacked interleaved converter, and it can be seen that both the first simulation image and the second simulation image are smooth, and complete cancellation of the current waveforms is substantially achieved.
It should be noted that the topological structure of the multiphase stacked interleaved converter can realize complete cancellation of output current ripples within a certain duty ratio range; meanwhile, as a plurality of main loops exist in the topological structure, the effect of shunting can be achieved, so that the current flowing through the inductor is n times (n is the number of phases) of the load current, the current stress flowing through each switching tube is also reduced, the effect of outputting large current is achieved, and meanwhile, the working efficiency of the converter is obviously improved; in addition, the multiphase stacking and interleaving has better fault tolerance, and when one bridge arm fails, other bridge arms can still work continuously, so that the working efficiency of the converter is greatly improved.
Optionally, with the above embodiment, a state space expression of the n-phase stacked interleaved converter can be further derived:
it should also be noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it should be appreciated by those skilled in the art that the present invention is not limited by the illustrated ordering of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Example 2
In this embodiment, a mathematical modeling apparatus of a topology structure is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description of which has been already made is omitted. As used hereinafter, the terms "module" and "apparatus" may refer to a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
According to an embodiment of the present invention, there is further provided an embodiment of an apparatus for implementing the mathematical modeling method for a topological structure, fig. 11 is a schematic structural diagram of an apparatus for mathematically modeling a topological structure according to an embodiment of the present invention, as shown in fig. 11, where the topological structure at least includes: the bridge arm circuit comprises a main loop, a slave loop and bridge arm circuits, wherein a plurality of main loops are connected in parallel, each slave loop is connected with a capacitor in series, each bridge arm circuit is provided with a plurality of switches, and the mathematical modeling device of the topological structure comprises: an obtaining module 600, a first determining module 602, a second determining module 604, and a calculating module 608, wherein:
the acquiring module 600 is configured to acquire a charge/discharge state formed between the master circuit and the slave circuit;
the first determining module 602 is configured to determine a plurality of switch states of the plurality of switches according to the charge/discharge state;
the second determining module 604, configured to determine a plurality of state space expressions corresponding to the topology based on a plurality of switch states;
the calculating module 608 is configured to calculate a state space model of the topology through a plurality of the state space expressions.
It should be noted that the above modules may be implemented by software or hardware, for example, for the latter, the following may be implemented: the modules can be located in the same processor; alternatively, the modules may be located in different processors in any combination.
It should be noted here that the obtaining module 600, the first determining module 602, the second determining module 604, and the calculating module 608 correspond to steps S102 to S108 in embodiment 1, and the modules are the same as the corresponding steps in implementation examples and application scenarios, but are not limited to the disclosure in embodiment 1. It should be noted that the modules described above may be implemented in a computer terminal as part of an apparatus.
It should be noted that, reference may be made to the relevant description in embodiment 1 for alternative or preferred embodiments of this embodiment, and details are not described here again.
The above-mentioned mathematical modeling apparatus for a topology structure may further include a processor and a memory, where the above-mentioned obtaining module 600, the first determining module 602, the second determining module 604, the calculating module 608, and the like are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to implement corresponding functions.
The processor comprises a kernel, and the kernel calls a corresponding program unit from the memory, wherein one or more than one kernel can be arranged. The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
According to an embodiment of the present application, there is also provided an embodiment of a non-volatile storage medium. Optionally, in this embodiment, the nonvolatile storage medium includes a stored program, and when the program runs, the apparatus in which the nonvolatile storage medium is located is controlled to execute the mathematical modeling method of any one of the topology structures.
Optionally, in this embodiment, the nonvolatile storage medium may be located in any one of computer terminals in a computer terminal group in a computer network, or in any one of mobile terminals in a mobile terminal group, and the nonvolatile storage medium includes a stored program.
Optionally, the device in which the non-volatile storage medium is controlled to execute the following functions when the program runs: acquiring a charge-discharge state formed between the master circuit and the slave circuit; determining a plurality of switch states of the plurality of switches according to the charge and discharge states; determining a plurality of state space expressions corresponding to the topology based on a plurality of switch states; and calculating to obtain the state space model of the topological structure through a plurality of state space expressions.
Optionally, the device in which the non-volatile storage medium is controlled to execute the following functions when the program runs: determining the S when the charge-discharge state is the first charge-discharge state11、S32、S23The switch is in an open state, and the other switches are in a closed state; determining the S when the charge-discharge state is the second charge-discharge state21、S12、S33The switch is in an open state, and the other switches are in a closed state; determining the S when the charge-discharge state is the third charge-discharge state31、S22、S13The switch is in an open state, and the other switches are in a closed state; determining the S when the charge/discharge state is the fourth charge/discharge state21、S22、S23And the other switches are in the closed state.
Optionally, the device in which the non-volatile storage medium is controlled to execute the following functions when the program runs: determining a duty ratio corresponding to the topological structure; determining the duration of each of the charge and discharge states according to the duty cycle; and calculating to obtain the state space model based on the duration and the plurality of state space expressions.
Optionally, the device in which the non-volatile storage medium is controlled to execute the following functions when the program runs: judging whether a fault bridge arm circuit exists in the topological structure; and if the topological structure is detected to have the fault bridge arm circuit, the topological structure continues to work normally after the fault bridge arm circuit is removed.
Optionally, the device in which the non-volatile storage medium is controlled to execute the following functions when the program runs: determining a duty ratio corresponding to the topological structure; inputting the duty ratio and the state space model into an MATLAB simulation model; and carrying out MATLAB simulation processing on the state space model to obtain a simulation image, wherein the simulation image is used for verifying the accuracy and the actual parameter performance of the topological structure.
According to an embodiment of the present application, there is also provided an embodiment of a processor. Optionally, in this embodiment, the processor is configured to execute a program, where the program executes any one of the above mathematical modeling methods of the topology structure.
There is further provided, in accordance with an embodiment of the present application, an embodiment of a computer program product, which, when executed on a data processing device, is adapted to execute a program initializing a mathematical modeling method step having a topology of any of the above.
Optionally, the computer program product is adapted to perform a program for initializing the following method steps when executed on a data processing device: acquiring a charge-discharge state formed between the master circuit and the slave circuit; determining a plurality of switch states of the plurality of switches according to the charge and discharge states; determining a plurality of state space expressions corresponding to the topology based on a plurality of switch states; and calculating to obtain the state space model of the topological structure through a plurality of state space expressions.
According to an embodiment of the present application, there is further provided an embodiment of an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform any one of the above mathematical modeling methods for a topology.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable non-volatile storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a non-volatile storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned nonvolatile storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for mathematical modelling of a topological structure, characterized in that said topological structure comprises at least: the bridge arm circuit comprises main loops, slave loops and bridge arm circuits, wherein the main loops are connected in parallel, each slave loop is connected with a capacitor in series, each bridge arm circuit is provided with a plurality of switches, and the method comprises the following steps:
acquiring a charge-discharge state formed between the master loop and the slave loop;
determining a plurality of switch states of the switches according to the charge and discharge states;
determining a plurality of state space expressions corresponding to the topology structure based on a plurality of switch states;
and calculating to obtain the state space model of the topological structure through a plurality of state space expressions.
2. The method according to claim 1, wherein the method is applied to a topology of a three-phase stacked interleaved converter, the master loop comprises a first master loop Lp1, a second master loop Lp2, a third master loop Lp3, the slave loops comprise a first slave loop Ls1, a second slave loop Ls2, a third slave loop Ls3, the charging and discharging states comprise a first charging and discharging state, a second charging and discharging state, a third charging and discharging state, and a fourth charging and discharging state, wherein,
the first charge-discharge state is that Lp1 is charged, Lp2 and Lp3 are discharged, Ls1 is discharged, and Ls2 and Ls3 are charged;
the second charge-discharge state is that Lp2 is charged, Lp1 and Lp3 are discharged, Ls2 is discharged, and Ls1 and Ls3 are charged;
the third charge-discharge state is that Lp3 is charged, Lp1 and Lp2 are discharged, Ls3 is discharged, and Ls1 and Ls2 are charged;
the fourth charge-discharge state is discharge of Lp1, Lp2 and Lp3, and charge of Ls1, Ls2 and Ls 3.
3. The method of claim 2, wherein the leg circuits comprise a first leg circuit having a first switch S disposed thereon, a second leg circuit, and a third leg circuit11A second switch S21And a third switch S31A fourth switch S is arranged on the second bridge arm circuit12The fifth switch S22And a sixth switch S32A seventh switch S is arranged on the third bridge arm circuit13The eighth switch S23And a ninth switch S33Wherein determining the switch state of the switch according to the charge-discharge state comprises:
when the charging/discharging state is the first stateDetermining S in the charging and discharging state11、S32、S23The switch is in an open state, and the other switches are in a closed state;
determining the S when the charge-discharge state is the second charge-discharge state21、S12、S33The switch is in an open state, and the other switches are in a closed state;
determining the S when the charge-discharge state is the third charge-discharge state31、S22、S13The switch is in an open state, and the other switches are in a closed state;
determining the S when the charge-discharge state is the fourth charge-discharge state21、S22、S23And the other switches are in the closed state.
4. The method of claim 1, wherein the state space expression:
wherein A isjThe state matrix is related to inductance parameters and capacitance parameters in the topological structure and is used for representing the connection state of the topological structure; b isjIs an input matrix, related to said charge-discharge states, each of said charge-discharge states corresponding to one of said input matrices; vinIs the supply voltage; x is a current-voltage matrix, wherein the current-voltage matrix at least comprises: a master loop current, a slave loop current, and a capacitor voltage.
5. The method of claim 1, wherein computing a state space model of the topology from a plurality of the state space expressions comprises:
determining a duty ratio corresponding to the topological structure;
determining the duration of each charge-discharge state according to the duty ratio;
and calculating to obtain the state space model based on the duration and the plurality of state space expressions.
6. The method of claim 1, further comprising:
judging whether a fault bridge arm circuit exists in the topological structure;
and if the topological structure is detected to have the fault bridge arm circuit, the topological structure continues to work normally after the fault bridge arm circuit is removed.
7. The method of claim 1, further comprising:
determining a duty ratio corresponding to the topological structure;
inputting the duty cycle and the state space model to a MATLAB simulation model;
and carrying out MATLAB simulation processing on the state space model to obtain a simulation image, wherein the simulation image is used for verifying the accuracy and the actual parameter performance of the topological structure.
8. An apparatus for mathematical modelling of a topological structure, characterized in that said topological structure comprises at least: the bridge arm circuit comprises main loops, slave loops and bridge arm circuits, wherein the main loops are connected in parallel, each slave loop is connected with a capacitor in series, each bridge arm circuit is provided with a plurality of switches, and the bridge arm circuit comprises:
an acquisition module configured to acquire a charge-discharge state formed between the master circuit and the slave circuit;
the first determining module is used for determining multiple switch states of the switches according to the charging and discharging states;
a second determining module, configured to determine, based on the plurality of switch states, a plurality of state space expressions corresponding to the topology;
and the calculation module is used for calculating to obtain a state space model of the topological structure through a plurality of state space expressions.
9. A non-volatile storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the mathematical modeling method of the topology according to any one of claims 1 to 7.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is configured to execute the computer program to perform the method of mathematical modeling of a topology as defined in any one of claims 1 to 7.
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