CN114285045A - Redundancy control method and device based on high-voltage dynamic reactive power compensation device - Google Patents
Redundancy control method and device based on high-voltage dynamic reactive power compensation device Download PDFInfo
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Abstract
The embodiment of the invention provides a redundancy control method based on a high-voltage dynamic reactive power compensation device, which comprises the following steps: when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state; and when the bypass fault occurs to the SVG node of the first level of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first level is switched to a bypass state, and one node is selected from the SVG nodes of the m levels to be put into operation. The redundancy control method based on the high-voltage dynamic reactive power compensation device provided by the embodiment of the invention ensures that the SVG node level and the SVG system running state in the system after the fault occurs are consistent with those before the fault, the control process is simple and convenient, the control carrier does not need to be reset, the code non-constant in the control process is small, and the harmonic distortion rate of the voltage and the current of a power grid can not be influenced.
Description
Technical Field
The invention belongs to the technical field of high-voltage dynamic reactive power compensation, and particularly relates to a method and a device for redundancy control based on a high-voltage dynamic reactive power compensation device.
Background
The high-voltage dynamic reactive power compensation device is also called a Static Var Generator or Static synchronous compensator (SVG), and is a device for performing dynamic reactive power compensation through a freely phase-changing power semiconductor bridge converter. The method is mainly used for carrying out dynamic reactive compensation and harmonic suppression on the nonlinear load in the power distribution network, and improving the power quality of the power distribution network. Compared with the early-adopted reactive power compensation devices such as a synchronous phase modulator and a capacitor, the SVG system has the advantages of low harmonic wave, high efficiency, high dynamic response speed and the like, and becomes important equipment in a modern flexible alternating current transmission system. Among the current middle-high voltage transmission and distribution system who adopts the SVG system: on the one hand, because the core switch device of the SVG equipment is usually the IGBT, and is limited by the highest withstand voltage value of the single-stage IGBT, a cascade SVG architecture is usually adopted to realize voltage class matching with the power grid: on the other hand, the multistage SVG system generally adopts the chain structure, and in order to avoid that a certain one-level SVG node device breaks down and leads to the whole system to lose efficacy, one-level or multistage SVG nodes need to be added in the chain structure as redundancy backup. For example, as shown in fig. 1, in a medium-high voltage power transmission and distribution system, n-level SVG nodes need to be configured theoretically according to voltage level matching, but in practical application, an n + m-level structure is adopted, wherein m-level SVG nodes additionally configured can be used as redundant backup.
In the prior art, for a power transmission and distribution system adopting n + m-level SVG nodes, the n + m-level SVG nodes work on line simultaneously, and each level of SVG node operates according to a control carrier wave independently output by an FPGA. When the DSP detects that a certain SVG node is abnormal, the fault node is bypassed by a bypass device, so that the fault node is separated from the system; the level number of the SVG nodes becomes n + m-1 level. In order to ensure normal operation of the n + m-1 level SVG nodes, the control carriers of the SVG nodes at all levels need to be adjusted. The existing adjusting method comprises two methods: the first method is to adopt a carrier delay method to redistribute the carrier, and the method only needs to set different delays for the control carriers of the rest n + m-1 level SVG nodes without changing the waveform and the frequency of the existing carrier. Obviously, the control method is simple in implementation, but the voltage and current harmonic distortion rate of the power grid is obviously increased due to the reduction of the number of stages of the SVG system. The second method is to reallocate carriers to the remaining n + m-1 level SVG nodes, for example, using the carrier allocation method disclosed in chinese patent application 201210336049.5, "a single carrier control method suitable for cascaded SVG. Because the number of stages of the cascaded SVG is changed, the distribution mode of the carriers needs to be redesigned and the frequency of each carrier needs to be calculated, the control process is complex, the code quantity related to the carrier generation process and the control process in the DSP and the FPGA is increased, BUG is easy to appear, and error checking is not easy to occur.
Disclosure of Invention
In view of the above problems, embodiments of the present invention provide a method for controlling redundancy of a high-voltage dynamic reactive power compensation device, which can effectively solve the problem that when a bypass fault occurs in an SVG system, the number of stages of the SVG system changes, which causes an increase in the harmonic distortion rate of the power grid and the current or makes the control process complicated.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the invention provides a redundancy control method based on a high-voltage dynamic reactive power compensation device, wherein the high-voltage dynamic reactive power compensation device comprises n + m-level SVG nodes, wherein n and m are both natural numbers; the method based on the redundancy control of the high-voltage dynamic reactive power compensation device comprises the following steps:
when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state;
and when the bypass fault occurs to the SVG node of the first level of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first level is switched to a bypass state, and one node is selected from the SVG nodes of the m levels to be put into operation.
Optionally, the method for selecting one node from m-level SVG nodes to put into operation includes:
closing the bypass device of the selected SVG node, and switching the selected SVG node to an online operation state;
and allocating a control carrier for the selected SVG node.
Optionally, the method for allocating a control carrier to the selected SVG node includes:
reallocating node addresses for the SVG nodes in the online running state;
and maintaining the corresponding relation between the original address code and the sending carrier wave, and sending the control carrier wave to each SVG node in the online running state.
Optionally, the method for reallocating the node address for the SVG node in the online running state includes:
assigning a new node address to the SVG node with the bypassable fault;
and giving the original address of the SVG node with the bypass fault to the selected SVG node.
Optionally, the method for reallocating the node address for the SVG node in the online running state includes:
assigning a new address to the SVG node with the bypassable fault;
for the node with the unit address code smaller than the original address code of the SVG node with the bypass fault, keeping the original address unchanged;
and for the node with the unit address code larger than the original address code of the SVG node with the bypass fault, reducing the address code by 1.
Optionally, a new node address of the SVG node where the bypassable fault occurs is stored, and the fault information is prompted.
Optionally, the method for judging that a bypassable fault occurs in the SVG node of the first stage in which the high-voltage dynamic reactive power compensation device operates on line is as follows:
restarting the high-voltage dynamic reactive power compensation device after the node fault occurs to the high-voltage dynamic reactive power compensation device;
after restarting, if the fault is not eliminated, judging whether the fault is a bypass fault;
if so, determining that the node has a bypassable fault.
In a second aspect, the invention further provides a high-voltage dynamic reactive power compensation device, which comprises n + m-level SVG nodes, wherein n and m are natural numbers; when the high-voltage dynamic reactive power compensation device is in operation, the method of any one of the first aspect is adopted.
In a second aspect, the present invention also provides an electronic device, comprising:
a processor; and
a memory arranged to store computer executable instructions that, when executed, cause the processor to perform the method of any of the preceding first aspects.
In a fourth aspect, the present invention also provides a computer readable storage medium storing one or more programs which, when executed by an electronic device comprising a plurality of application programs, cause the electronic device to perform the method of any of the preceding first aspects.
The invention has the advantages and beneficial effects that: according to the method and the device for redundancy control based on the high-voltage dynamic reactive power compensation device, when a bypass fault occurs in an SVG node in online operation, the fault SVG node is bypassed, and the redundant SVG node is selected to replace the fault SVG node to be put into operation, so that the consistency between the SVG node level and the SVG system operation state in the system after the fault occurs and before the fault occurs is ensured. The control process of the embodiment of the invention is simple and convenient, the control carrier does not need to be reset, and the code non-constant of the control process is small; because the SVG node level and the working state of the online operation after the fault are completely consistent with those before the fault, the harmonic distortion of the voltage and the current of the power grid can not be influenced.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic overall structure diagram of a high-voltage dynamic reactive power compensation device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for controlling redundancy based on a high voltage dynamic reactive power compensation device according to an embodiment of the present invention;
fig. 3 is another flowchart of a method for controlling redundancy based on a high voltage dynamic reactive power compensation device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a schematic diagram of an overall structure of a high-voltage dynamic reactive power compensation device in the prior art. The high-voltage dynamic reactive power compensation device adopts a chain type cascade structure, comprises 3 paths of links formed by connecting a plurality of SVG nodes in series, corresponds to A, B, C three phases of a power grid respectively, and adopts a star-shaped connection structure. Taking phase A as An example, the phase A comprises n + m SVG nodes, namely A1, A2 … … An and An +1 … … An + m, and each SVG node is correspondingly provided with a bypass device, namely KA1, KA2 … … KAn and KAn +1 … … KAn + m. In the prior art, n-level SVG nodes are required to be configured on the link according to the voltage level, but an n + m-level structure is adopted in practical application, wherein the additionally configured m-level SVG nodes can be used as redundant backup. The n + m-level SVG nodes work on line simultaneously, and each level of SVG node operates according to the control carrier wave independently output by the FPGA. When an SVG node is detected to be abnormal, the fault node can be bypassed by a bypass device corresponding to the SVG node, so that the SVG node is separated from the link. At the moment, the stage number of the SVG node is changed from n + m stage to n + m-1 stage, so that the control carrier wave of the SVG node running on line at each stage needs to be adjusted after bypassing. Obviously, the technical scheme has the problems that the SVG node level changes, the carrier adjustment is complex, the voltage and current harmonic distortion of the power grid is influenced, and the like.
Example 1:
the embodiment provides a method based on redundancy control of a high-voltage dynamic reactive power compensation device.
As shown in fig. 1, the high-voltage dynamic reactive power compensation device includes n + m-stage SVG nodes, where m and n are both natural numbers. The n-level SVG node is a main node, and is in an online running state through a bypass device when the high-voltage dynamic reactive power compensation device runs normally; the m-level SVG node is a standby node, and when the high-voltage dynamic reactive power compensation device normally operates, the high-voltage dynamic reactive power compensation device is in a bypass redundancy state through a bypass device.
As shown in fig. 2, the method for controlling redundancy based on the high-voltage dynamic reactive power compensation device comprises the following steps:
when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state;
and when the bypass fault occurs to the SVG node of the first stage of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first stage is switched to a bypass state, and one node is selected from the n-stage SVG nodes to be put into operation.
Based on the method, when the bypass fault occurs to the primary SVG node in the online operation state, one of the standby nodes in the redundant state is selected to replace the fault SVG node, the stage number of the SVG node in the link cannot be changed, and the high-voltage dynamic reactive power compensation device can keep the same working state as that before switching after the SVG node is switched.
Specifically, the method for selecting one node from the n-level SVG nodes to be put into operation comprises the following steps: closing the bypass device of the selected SVG node, and switching the selected SVG node to an online operation state; and allocating a control carrier for the selected SVG node. The method for distributing the control carrier to the selected SVG node comprises the following steps: reallocating node addresses for the SVG nodes in the online running state; and maintaining the corresponding relation between the original address code and the sending carrier wave, and sending the control carrier wave to each SVG node in the online running state. The SVG node address refers to an address of each SVG node for receiving a control signal. For example, the running state of a power grid and the running state of each SVG node are detected in real time through the DSP, control information of each SVG node is generated, and the control information is sent to the FPGA; and the FPGA generates a carrier signal according to the control information and sends the carrier signal to the SVG node corresponding to the address code. Because the number of stages of the SVG nodes of the high-voltage dynamic reactive power compensation device which are put into operation is not changed, and the address codes of the SVG nodes are not changed, the FPGA can send control carriers to each SVG node in an online operation state according to the corresponding relation between the original address codes and the sending carriers. Therefore, by adopting the method, when the SVG node equipment is replaced, the FPGA is in a non-inductive state, namely the FPGA does not need to make response action or change output carrier waves, so that the control process of the FPGA is simplified, and the code amount of the FPGA is reduced.
The method for reallocating the node address for the SVG node in the online running state includes various methods, for example, one method is as follows: assigning a new node address to the SVG node with the bypassable fault; and giving the original address of the SVG node with the bypass fault to the selected SVG node. The method is the simplest to implement, but the method causes the physical sequence of the SVG nodes in the link to be inconsistent with the sequence of the address codes.
As a better method, the method for reallocating the node address for the SVG node in the m-level online running state is as follows: assigning a new address to the SVG node with the bypassable fault; for the node with the unit address code smaller than the original address code of the SVG node with the bypass fault, keeping the original address unchanged; and for the node with the unit address code larger than the original address code of the SVG node with the bypass fault, reducing the address code by 1.
As a specific embodiment, the address of each SVG node is expressed as follows:
assuming that the ith-stage SVG node device in the phase B has a bypassable fault, the relationship between the original address and the new address of each-stage SVG node device in the phase B is as follows:
| SVG node | Original address | New address |
| B1 | (n+m)+1 | (n+m)+1 |
| B2 | (n+m)+2 | (n+m)+2 |
| …… | ||
| Bi | (n+m)+i | 3(n+m)+1 |
| …… | …… | …… |
| Bn | (n+m)+n | (n+m)+n-1 |
| Bn+1 | (n+m)+n+1 | (n+m)+n+1-1 |
| …… | …… | …… |
| Bn+m | (n+m)+n+m | (n+m)+n+m-1 |
Therefore, after new addresses are given to the SVG nodes running on line and the rest m-1 redundant SVG nodes, the physical arrangement sequence of the SVG nodes running on line and the new node address codes are completely consistent with those before switching, so that the switching of the SVG nodes by the FPGA can be in a non-inductive state, the FPGA does not need to make any response to the switching or adjust output carriers, and the high-voltage dynamic reactive power compensation device can completely keep a working state before a fault. By adopting the method, the control process of the FPGA can be simplified to the maximum extent, and the code amount of a control program is reduced.
As an alternative solution, the new address coding assigned to the SVG node with the bypass fault is preferably out of 3(n + m) to avoid conflict with the address of the non-faulty SVG node. Still taking the above example as an example, Bi may be given a new node address set after 3(n + m), e.g., 3(n + m) + 1. Preferably, the storage device stores the new node address of the SVG node with the bypass-capable fault, and the display device prompts the fault information, so as to inform the staff of the fault of the equipment.
Furthermore, in order to avoid the false operation of the high-voltage dynamic reactive power compensation device caused by external interference or bug during operation, when the high-voltage dynamic reactive power compensation device has a fault and is abnormal, the high-voltage dynamic reactive power compensation device can be restarted to determine the fault reason. As a specific method for judging a bypassable fault of an SVG node at a first stage of the online operation of the high-voltage dynamic reactive power compensation device, as shown in fig. 3, the method includes the following steps:
when the high-voltage dynamic reactive power compensation device breaks down, judging whether the fault is a restarting fault;
if yes, restarting; if the restart is successful, the normal operation state is recovered;
if the fault is not a restarting fault or the fault is not eliminated after restarting, further judging whether the fault is a bypass-capable fault;
if the bypass fault is not detected, prompting error information to wait for intervention maintenance of an operator;
if the node is in the bypass-capable fault, determining that the node has the bypass-capable fault, issuing a bypass instruction, and entering a bypass interrupt processing program.
By adopting the method, the wrong switching operation caused by interference of the high-voltage dynamic reactive power compensation device can be avoided, and the running reliability of the system can be improved.
Example 2:
the embodiment provides a high-voltage dynamic reactive power compensation device which comprises n + m-level SVG nodes, wherein m and n are natural numbers. When the high-voltage dynamic reactive power compensation device is operated, the method of embodiment 1 is adopted, and the method at least comprises the following steps:
when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state;
and when the bypass fault occurs to the SVG node of the first stage of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first stage is switched to a bypass state, and one node is selected from the n-stage SVG nodes to be put into operation.
Obviously, the present embodiment has the same technical effects as embodiment 1.
Example 3:
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 4, at the hardware level, the electronic device includes a processor, and optionally further includes an internal bus, a network interface, and a memory. The processor may be a desktop computer processor, or may be an embedded system processor, such as a digital signal processor DSP, a single chip, or the like. The Memory may include a Memory, such as a Random-Access Memory (RAM), and may also include a non-volatile Memory, such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.
The processor, the network interface, and the memory may be connected to each other via an internal bus, which may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 3, but this does not indicate only one bus or one type of bus.
And the memory is used for storing programs. In particular, the program may include program code comprising computer operating instructions. The memory may include both memory and non-volatile storage and provides instructions and data to the processor.
The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs the computer program to form the detection device of the abnormal value of the GNSS signal on the logic level. The processor is used for executing the program stored in the memory and is specifically used for executing at least the following operations:
when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state;
and when the bypass fault occurs to the SVG node of the first stage of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first stage is switched to a bypass state, and one node is selected from the n-stage SVG nodes to be put into operation.
The method based on the redundancy control of the high-voltage dynamic reactive power compensation device disclosed in the embodiment of fig. 2 of the present application can be applied to or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.
Example 4
The present application further provides a computer-readable storage medium storing one or more programs, where the one or more programs include instructions, which when executed by an electronic device including a plurality of application programs, enable the electronic device to perform the method based on redundant control of a high-voltage dynamic reactive power compensation device in the embodiment shown in fig. 2, and are specifically configured to perform at least the following operations:
when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state;
and when the bypass fault occurs to the SVG node of the first stage of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first stage is switched to a bypass state, and one node is selected from the n-stage SVG nodes to be put into operation.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors, input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A redundancy control method based on a high-voltage dynamic reactive power compensation device comprises n + m-level SVG nodes, wherein n and m are natural numbers; the method is characterized by comprising the following steps of:
when the high-voltage dynamic reactive power compensation device normally operates, the n-level SVG nodes of the high-voltage dynamic reactive power compensation device are in an online operation state, and the m-level SVG nodes are in a bypass redundancy state;
and when the bypass fault occurs to the SVG node of the first level of the high-voltage dynamic reactive power compensation device in online operation, the SVG node of the first level is switched to a bypass state, and one node is selected from the SVG nodes of the m levels to be put into operation.
2. The method for controlling redundancy of high-voltage dynamic reactive power compensation device according to claim 1, wherein: the method for selecting one node from m-level SVG nodes to put into operation comprises the following steps:
closing the bypass device of the selected SVG node, and switching the selected SVG node to an online operation state;
and allocating a control carrier for the selected SVG node.
3. The method based on the redundancy control of the high-voltage dynamic reactive power compensation device according to claim 2, wherein: the method for distributing the control carrier waves to the selected SVG node comprises the following steps:
reallocating node addresses for the SVG nodes in the online running state;
and maintaining the corresponding relation between the original address code and the sending carrier wave, and sending the control carrier wave to each SVG node in the online running state.
4. The method for controlling redundancy of high-voltage dynamic reactive power compensation device according to claim 3, wherein: the method for reallocating the node address for the SVG node in the online running state comprises the following steps:
assigning a new node address to the SVG node with the bypassable fault;
and giving the original address of the SVG node with the bypass fault to the selected SVG node.
5. The method for controlling redundancy of high-voltage dynamic reactive power compensation device according to claim 3, wherein: the method for reallocating the node address for the SVG node in the online running state comprises the following steps:
assigning a new address to the SVG node with the bypassable fault;
for the node with the unit address code smaller than the original address code of the SVG node with the bypass fault, keeping the original address unchanged;
and for the node with the unit address code larger than the original address code of the SVG node with the bypass fault, reducing the address code by 1.
6. The method based on the redundant control of the high voltage dynamic reactive power compensation device according to claim 4 or 5, characterized in that: and storing the new node address of the SVG node with the bypassable fault, and prompting fault information.
7. The method for controlling redundancy of high-voltage dynamic reactive power compensation device according to claim 1, wherein: the method for judging the bypass fault of the SVG node of the first stage of the online operation of the high-voltage dynamic reactive power compensation device comprises the following steps:
restarting the high-voltage dynamic reactive power compensation device after the node fault occurs to the high-voltage dynamic reactive power compensation device;
after restarting, if the fault is not eliminated, judging whether the fault is a bypass fault;
if so, determining that the node has a bypassable fault.
8. A high-voltage dynamic reactive power compensation device comprises n + m-level SVG nodes, wherein n and m are natural numbers; the method for controlling the high-voltage dynamic reactive power compensation device based on the redundancy is characterized in that the method for controlling the high-voltage dynamic reactive power compensation device based on the redundancy is adopted in any one of the claims 1 to 7 when the high-voltage dynamic reactive power compensation device is operated.
9. An electronic device, comprising:
a processor; and
a memory arranged to store computer executable instructions which, when executed, cause the processor to perform the method of any of claims 1 to 7.
10. A computer readable storage medium storing one or more programs which, when executed by an electronic device comprising a plurality of application programs, cause the electronic device to perform the method of any of claims 1-7.
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