CN114281389A

CN114281389A - Method and device for upgrading SOC (system on chip) and automatic driving vehicle

Info

Publication number: CN114281389A
Application number: CN202210091123.5A
Authority: CN
Inventors: 李胜凯
Original assignee: Apollo Intelligent Technology Beijing Co Ltd
Current assignee: Apollo Intelligent Technology Beijing Co Ltd
Priority date: 2022-01-26
Filing date: 2022-01-26
Publication date: 2022-04-05

Abstract

The present disclosure provides a method for upgrading a system on chip SOC, which is applied to a target central processing unit CPU core, wherein the SOC includes at least two CPU cores, the target CPU core is one of the at least two CPU cores, and relates to the technical field of computers, in particular to the technical field of system on chip and intelligent driving. The specific implementation scheme is as follows: reading a preset configuration file; determining the role of the target CPU core based on the preset configuration file, wherein the role comprises a main core or a slave core; according to the determined role, performing one of: in response to determining that the role is a primary core, performing primary core flashing according to the detected upgrade instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

Description

Method and device for upgrading SOC (system on chip) and automatic driving vehicle

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to the field of System On Chip (SOC) and smart driving technologies, and in particular, to a method and an apparatus for upgrading an SOC, and an autonomous driving vehicle.

Background

With the rapid development of intelligent driving technology, higher requirements are also put forward on the processing capacity of the vehicle end. To meet performance requirements, SOCs are increasingly becoming widely used on the vehicle side.

In the prior art, a Micro Controller Unit (MCU) usually appears in a heterogeneous multi-core form, and an upgrade process usually performs information interaction between a fixed master core and the outside, and performs flash writing on other slave cores. The multi-core related to the upgrading process is a fixed master-slave structure, and the flashing direction is only from the master core to the slave core.

Disclosure of Invention

A method and apparatus for system-on-chip upgrade and an autonomous vehicle are provided.

According to a first aspect, there is provided a method for system-on-chip upgrade, applied to a target central processing unit CPU core, an SOC comprising at least two CPU cores, the target CPU core being one of the at least two central processing unit CPU cores, the method comprising: reading a preset configuration file; determining the role of a target CPU core based on a preset configuration file, wherein the role comprises a main core or a slave core; according to the determined role, performing one of: in response to the fact that the role is determined to be the main core, performing main core flashing according to the detected upgrading instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

According to a second aspect, there is provided an apparatus for system-on-chip upgrade, applied to a target central processing unit CPU core, an SOC comprising at least two central processing unit CPU cores, the target CPU core being one of the at least two central processing unit CPU cores, the apparatus comprising: a reading unit configured to read a preset configuration file; the determining unit is configured to determine the role of the target CPU core based on a preset configuration file, wherein the role comprises a main core or a slave core; an execution unit configured to execute, according to the determined role, one of: in response to the fact that the role is determined to be the main core, performing main core flashing according to the detected upgrading instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

According to a third aspect, there is provided a system-on-chip comprising: the system comprises at least two homogeneous CPU cores, wherein the at least two homogeneous CPU cores comprise a CPU core serving as a main core and at least one CPU core serving as a slave core; and a memory communicatively coupled to at least two homogeneous CPU cores; wherein the memory stores instructions executable by at least two homogeneous CPU cores, the instructions being executed by at least one CPU core to enable the at least one CPU core to perform the method as described in any implementation manner of the first aspect.

According to a fourth aspect, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for enabling a computer to perform the method as described in any one of the implementations of the first aspect.

According to a fifth aspect, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the method as described in any of the implementations of the first aspect.

According to a sixth aspect, there is provided an autonomous vehicle comprising a system on chip as described in the third aspect.

According to a seventh aspect, there is provided a roadside apparatus comprising the system on chip as described in the third aspect.

According to the technology disclosed by the invention, the CPU cores of the system on chip read the preset configuration files and respectively determine the roles of the CPU cores to be the main core or the slave core, so that the CPU core with the role as the main core bears the functions of external communication and upgrading, the dynamic determination of the roles of the main core and the slave core is realized, and a foundation is provided for ensuring the reliability of the whole system on chip upgrading.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram according to a first embodiment of the present disclosure;

FIG. 2 is a schematic diagram according to a second embodiment of the present disclosure;

FIG. 3 is a schematic diagram of one application scenario in which a method for system-on-chip upgrade of embodiments of the present disclosure may be implemented;

FIG. 4 is a schematic diagram of an apparatus for system-on-chip upgrade, according to an embodiment of the present disclosure;

FIG. 5 is a block diagram of a system-on-chip for implementing a method for system-on-chip upgrade of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Fig. 1 is a schematic diagram 100 illustrating a first embodiment according to the present disclosure. The method for upgrading the system on chip is applied to a target CPU core on an SOC (system on chip) comprising at least two CPU cores, and specifically comprises the following steps:

s101, reading a preset configuration file.

In this embodiment, an execution subject of the method for system-on-chip upgrade (e.g., a target CPU core on an SOC including at least two CPU cores) may read a preset configuration file in various ways. The target CPU core may be, for example, any CPU specified in advance. The preset configuration file may be used to indicate that a certain CPU of at least two CPUs in the SOC where the execution subject is located is a master core or a slave core. The master core and the slave core may be designed by using the same design architecture. As an example, the preset configuration file may record a corresponding relationship between an identifier of the CPU core and a corresponding role (e.g., a master core or a slave core), so that each CPU core may determine its own role according to the identifier.

It should be noted that the execution subject may be a target CPU core. The SOC may include at least two CPU cores. The target CPU core may be one of the at least two CPU cores.

S102, determining the role of the target CPU core based on a preset configuration file.

In this embodiment, the execution body may determine the role of the target CPU core in various ways based on the preset configuration file read in step S101. The roles may include a master core or a slave core. The primary core may generally be used to characterize a CPU core that interacts with information external to the system-on-chip. The master core may also send an upgrade instruction to the slave core via inter-core communication. The above-described slave core may be generally used to characterize a CPU core that has turned off external communication functions and active upgrade functions, which generally only retains the functionality of receiving a flush command and flushing itself.

S103, according to the determined role, executing one of the following two: in response to the fact that the role is determined to be the main core, performing main core flashing according to the detected upgrading instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

In this embodiment, according to the role determined in step S102, the execution subject may execute one of the following: in response to the fact that the role is determined to be the main core, performing main core flashing according to the detected upgrading instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

In this embodiment, in response to determining that the role determined in step S102 is a primary core, the execution subject may detect an upgrade instruction from outside the SOC. The upgrade instruction may be, for example, an upgrade instruction sent by the server to upgrade the SOC system. In response to determining that an upgrade instruction from outside the SOC is detected, the execution subject may perform a main core flush according to the detected upgrade instruction in various ways. As an example, the execution subject may perform the main core flash according to a preset upgrade flow or an upgrade flow indicated by the upgrade instruction.

In this embodiment, in response to determining that the role determined in step S102 is a slave core, the execution main body may stop communication with the outside of the SOC. Specifically, since at least two CPU cores on the SOC are usually designed by using the same design architecture, each of the at least two CPU cores has a basis for implementing all functions of the CPU core. The execution main body may close its module for communicating with the outside of the SOC only when a target CPU core of the at least two CPU cores determines that its own role is a slave core, so that it may still communicate with the master core by means of inter-core communication. Alternatively, the execution agent as a slave core may also shut down the module actively upgraded, thereby leaving only the module receiving the flush command and the flush itself.

In the method provided by the above embodiment of the present disclosure, each CPU core of the system on chip reads a preset configuration file, and determines that the CPU core is in the role of the master core or the slave core, so that the CPU core in which the role is the master core assumes the functions of external communication and upgrade, thereby implementing dynamic determination of the roles of the master core and the slave core, and providing a basis for ensuring the reliability of the upgrade of the whole system on chip.

In some optional implementation manners of this embodiment, based on a preset configuration file, the execution main body may determine the role of the target CPU core according to the following steps:

and S1021, responding to the fact that the preset configuration file indicates that the target CPU core is in the role of the main core, and sending a main core confirmation signal to other CPU cores on the SOC through inter-core communication.

In these implementations, in response to determining that the preset configuration file indicates that the role of the target CPU core is a master core, the execution master may send a master core acknowledge signal to other CPU cores on the SOC via inter-core communication. The master core acknowledge signal may be used to notify the existence of the master core.

Optionally, the execution main body may also periodically send a main core confirmation signal to other CPU cores on the SOC through inter-core communication at preset time intervals.

S1022, the role of the target CPU core is determined based on the received response confirmation information corresponding to the master confirmation signal.

In these implementations, the execution principal may determine the role of the target CPU core in various ways based on the received response confirmation information corresponding to the master core confirmation signal transmitted in step S1021.

For example, if the execution main body does not receive the response acknowledgement information corresponding to the master core acknowledgement signal sent in step S1021 within a preset time interval, the execution main body may determine that the target CPU core is in the role of a slave core. As another example, if the execution agent receives the response acknowledgement information corresponding to the master acknowledgement signal transmitted in step S1021, the execution agent may determine that the role of the target CPU core is the master core. The response confirmation information can be used for representing that the slave core approves the existence of the master core.

Based on the optional implementation manner, the role of the target CPU core can be comprehensively judged by using the main core confirmation signal for notifying the existence of the main core and the response confirmation information corresponding to the main core, so that the role determination accuracy of the target CPU core is improved, and technical guarantee is provided for subsequent system upgrade.

Optionally, based on the optional implementation manner, based on the received response acknowledgement information corresponding to the master core acknowledgement signal, the execution main body may determine the role of the target CPU core according to the following steps:

and in the first step, in response to receiving response confirmation information corresponding to the main core confirmation signal, checking again according to a preset configuration file.

In these implementations, in response to receiving the response confirmation information corresponding to the primary core confirmation signal, the execution main body may perform a re-check according to the preset configuration file to confirm whether the primary core indicated in the configuration file is itself.

And secondly, determining the role of the target CPU core according to the result of rechecking the preset configuration file.

In these implementations, the execution agent may determine the role of the target CPU core in various ways according to the result of the rechecking performed in the first step.

Optionally, based on the manner described in the second step, based on the result of performing re-verification according to a preset configuration file, the execution main body may determine the role of the target CPU core according to the following steps:

step 1, in response to the fact that the result of rechecking according to the preset configuration file indicates that the role of the target CPU core is the main core, determining that the role of the target CPU core is the main core.

And step 2, responding to the result of confirming to carry out recheck according to the preset configuration file to indicate that the role of the target CPU core is not the master core, and confirming that the role of the target CPU core is the slave core.

Based on the optional implementation manner, the scheme can perform recheck according to a preset configuration file after receiving the response confirmation information corresponding to the main core confirmation signal, and determine the role of the target CPU core according to the recheck result, so that the accuracy of determining the role of the target CPU core is further improved, and a more solid technical guarantee is provided for subsequent system upgrade.

In some optional implementation manners of this embodiment, based on a preset configuration file, in response to determining that the preset configuration file indicates that the role of the target CPU core is not a master core, the execution main body may determine that the role of the target CPU core is a slave core.

Based on the optional implementation manner, the method and the device can directly confirm that the role of the target CPU core is the slave core when the preset configuration file indicates that the target CPU core is not the master core, so that the efficiency of confirming the role of the target CPU core is improved.

In some optional implementations of this embodiment, in response to determining that the role is a slave core and receiving a master core acknowledge signal, the execution main body may further reply with a response acknowledge message.

In these implementations, the primary core acknowledgement signal described above may be used to inform the primary core of the presence. The response acknowledgement information may be used to characterize the acceptance of the master core by the slave core.

Based on the optional implementation manner, the scheme can realize the confirmation of the master core by sending the response confirmation information corresponding to the received master core confirmation signal by the slave core, thereby being beneficial to improving the accuracy of the master core determination.

In some optional implementations of this embodiment, in response to determining that the role is a slave core, the execution main body may further perform a flash according to a flash instruction received through inter-core communication.

In these implementations, in response to determining that the role is a slave core, the execution subject may perform a flash through a flash instruction sent by the master core and received through inter-core communication, thereby completing upgrading itself.

In these implementations, the complete upgrade compression package may be included in the above-described flush instruction, as an example. As another example, the flush instruction may include an upgrade file parsed by the main core, which is not limited herein.

In some optional implementation manners of this embodiment, in response to determining that the role is the master core, the execution subject may further send, according to a detected upgrade instruction from outside the SOC, a flash instruction to the CPU core with the role as the slave core on the SOC through inter-core communication.

In these implementations, the upgrade instruction from outside the SOC may be the same as described above, and will not be described herein. The flash instruction may include a complete upgrade compressed package, or may include an upgrade file parsed by the main core, which is not limited herein.

Based on the optional implementation mode, the scheme can realize the flash upgrading of the master core and the slave core through inter-core communication.

In some optional implementations of the present embodiment, the upgrade instructions from outside the SOC may be used to instruct upgrading of the vehicle software system.

In these implementations, the SOC may include a multi-core controller for a vehicle. The upgrade instruction from the outside of the SOC may be an instruction issued by a server connected to the communication system to instruct upgrading of the vehicle software system.

Based on the optional implementation mode, the scheme can be applied to the vehicle system, so that the reliability of multi-core SOC flash is improved, the maintenance cost is reduced, and the system upgrading reliability of the vehicle with the multi-core SOC controller is improved.

In some optional implementations of this embodiment, the executing body may further continue to perform the following steps:

the first step is to detect whether the preset configuration file is updated.

In these implementations, the execution body may detect whether the preset configuration file is updated in various ways. As an example, the execution body may detect whether the preset configuration file is updated through a file modification time, a file size, a file identifier (e.g., md5 checksum, etc.), and the like.

And a second step of re-reading the updated configuration file in response to determining that the preset configuration file update is detected.

And thirdly, determining the role of the target CPU core based on the updated configuration file.

In these implementations, the execution subject may refer to the method described in the foregoing step S102 and its optional implementations, and replace the "preset configuration file" with the "updated configuration file" so as to determine the role of the target CPU core.

Based on the optional implementation mode, the scheme can realize the role update of the master core and the slave core by modifying the configuration file, and improves the usability of the system.

In some optional implementations of this embodiment, in response to receiving an arbitration result indicating that the role of the target CPU core is the master core, the execution main body may further determine that the current role of the target CPU core is the master core.

In these implementations, the arbitration result may be generated by an arbitration method participated by at least two CPU cores on the SOC.

Based on the optional implementation mode, the main core can be reselected by an arbitration method under the condition that the main core is lost, so that the reliability of the whole SOC system is improved.

With continued reference to fig. 2, fig. 2 is a schematic diagram 200 according to a second embodiment of the present disclosure. The method for upgrading the system on chip is applied to a target CPU core on an SOC (system on chip) comprising at least two CPU cores, and specifically comprises the following steps:

s201, reading a preset configuration file.

S202, determining the role of the target CPU core based on a preset configuration file.

S203, according to the determined role, executing one of the following two: in response to the fact that the role is determined to be the main core, performing main core flashing according to the detected upgrading instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

S201, S202, and S203 may respectively correspond to S101, S102, S103 and their optional implementations in the foregoing embodiments, and the above description on S101, S102, S103 and their optional implementations also applies to S201, S202, and S203, which is not described herein again.

S204, responding to the fact that the role is determined to be the main core, and determining whether upgrading can be carried out through external communication by using the target CPU core.

In the present embodiment, in response to determining that the role is a master core, an execution subject of the method for system-on-chip upgrade (e.g., a target CPU core on an SOC including at least two CPU cores) may determine whether upgrade by external communication using the target CPU core is possible in various ways.

In the present embodiment, as an example, the execution main body may detect whether or not the relevant module can be used to control the upgrade of the SOC in accordance with the upgrade instruction acquired by the external communication.

S205, in response to determining that the target CPU core cannot be upgraded by external communication, updating the role of the target CPU core to the slave core.

In this embodiment, in response to the step S204 determining that the target CPU core cannot be upgraded by external communication, the execution subject may update the role of the target CPU core to the slave core.

In some optional implementations of this embodiment, the execution subject may determine whether the target CPU core can be upgraded through external communication according to the following steps:

s2041, a communication state with the SOC external device is detected.

In these implementations, the execution body may detect a communication state with the SOC external device in various ways. For example, the execution agent may test a communication state between the target CPU core and the SOC external device through a ping (packet Internet groper) command. Thereafter, the execution body may determine whether or not the upgrade by the external communication using the target CPU core is possible according to the communication state. As an example, when the execution main body determines that the connection condition is normal (for example, the connection rate is in a preset interval), it may be determined that the upgrade by the external communication using the target CPU core is possible.

S2042, in response to determining that the external communication state is abnormal, determining that the upgrade by the external communication using the target CPU core cannot be performed.

In these implementations, in response to determining that the external communication state is abnormal (e.g., disconnected or poorly connected), the execution agent may determine that the target CPU core cannot be used for upgrade through external communication.

Based on the optional implementation manner, the scheme can determine whether the target CPU core can be used for upgrading through external communication according to the detected communication state between the target CPU core and the SOC external device.

the first step is to detect whether the preset configuration file is updated.

As can be seen from fig. 2, a flow 200 of the method for system-on-chip upgrade in the present embodiment embodies a step of determining whether upgrade by external communication using a target CPU core is possible in response to determining that the role of the target CPU core is a master core, and a step of updating the role of the target CPU core to a slave core in response to determining that upgrade by external communication using the target CPU core is not possible. Therefore, according to the scheme described in this embodiment, the original master core can be switched to the slave core in time under the condition that the master core cannot be upgraded through external communication, so that the master core after the role update can continue to be upgraded through the external communication, and the reliability of the whole SOC system upgrade is ensured.

With continued reference to FIG. 3, FIG. 3 is a schematic diagram of an application scenario of a method for system-on-chip upgrade, according to an embodiment of the present disclosure. In the application scenario of fig. 3, the system-on-chip 3011 may be included in the vehicle 301 with the driving assistance function. The system on chip 3011 may include a CPU1 and a CPU 2. The CPU1 and the CPU2 can exchange information through inter-core communication. The CPU1 and the CPU2 may read a preset configuration file 3012, respectively. Based on the preset configuration file 3012, the CPU1 and the CPU2 may determine their roles, for example, the CPU1 is the master core and the CPU2 is the slave core. In response to determining that the role is primary, the CPU1 may perform a primary flush based on the detected upgrade instructions 303 sent from the external backend server 302. In response to determining that the role is a slave core, the CPU2 stops communication with the outside of the system-on-chip, for example, disconnects communication with the outside of the system-on-chip, and thus cannot receive the upgrade instruction 303 sent from the external background server 302.

At present, in one of the prior art, a heterogeneous multi-core form is usually adopted, a fixed main core performs information interaction with the outside, and other slave cores are flushed, the related multi-core is a fixed main-slave structure, and the flushing direction is only from the main core to the slave cores, so that the whole system on chip is affected after the main core fails, for example, communication failure or upgrading cannot be performed. In the method provided by the embodiment of the disclosure, each CPU core of the system on chip reads a preset configuration file and determines that the CPU core is in the role of the master core or the slave core, so that the CPU core with the role of the master core bears the functions of external communication and upgrading, thereby implementing dynamic determination of the roles of the master core and the slave core, and providing a basis for ensuring the reliability of upgrading of the whole system on chip.

With further reference to fig. 4, as an implementation of the methods shown in the above-mentioned figures, the present disclosure provides an embodiment of an apparatus for system-on-chip upgrade, which is applied to a target CPU core on an SOC including at least two CPU cores, and the embodiment of the apparatus corresponds to the embodiment of the method shown in fig. 1 or fig. 2, and the apparatus may be applied to various electronic devices in particular.

As shown in fig. 4, the apparatus 400 for system-on-chip upgrade, applied to a target CPU core on an SOC including at least two central processor CPU cores, provided by the present embodiment includes a reading unit 401, a determining unit 402, and an executing unit 403. The reading unit 401 is configured to read a preset configuration file; a determining unit 402 configured to determine a role of the target CPU core based on a preset configuration file, wherein the role includes a master core or a slave core; an execution unit 403 configured to, according to the determined role, perform one of: in response to the fact that the role is determined to be the main core, performing main core flashing according to the detected upgrading instruction from the outside of the SOC; in response to determining that the role is a slave core, communication with outside the SOC is stopped.

In the present embodiment, in the apparatus 400 for system-on-chip upgrade: the specific processing of the reading unit 401, the determining unit 402, and the executing unit 403 and the technical effects thereof can refer to the related descriptions of steps S101, S102, and S103 in the corresponding embodiment of fig. 1, which are not repeated herein.

In some optional implementations of this embodiment, the determining unit 402 may include: a sending module (not shown in the figure) configured to send a master core confirmation signal to other CPU cores on the SOC through inter-core communication in response to determining that the preset configuration file indicates that the role of the target CPU core is a master core; a determination module (not shown in the figure) configured to determine a role of the target CPU core based on the received response acknowledgement information corresponding to the master acknowledgement signal. The master core acknowledge signal may be used to notify the existence of the master core.

In some optional implementations of this embodiment, the determining module may include: a checking submodule (not shown in the figure) configured to perform a re-checking according to a preset configuration file in response to receiving a response confirmation information corresponding to the primary core confirmation signal; and a determining submodule (not shown in the figure) configured to determine a role of the target CPU core according to a result of performing recheck according to a preset configuration file.

In some optional implementations of this embodiment, the determining sub-module may be further configured to: and in response to determining that the re-checking result according to the preset configuration file indicates that the role of the target CPU core is the main core, determining that the role of the target CPU core is the main core. And determining that the role of the target CPU core is a slave core in response to determining that the result of rechecking according to the preset configuration file indicates that the role of the target CPU core is not the master core.

In some optional implementations of this embodiment, the determining unit 402 may be further configured to: and in response to determining that the preset configuration file indicates that the role of the target CPU core is not the master core, determining that the role of the target CPU core is the slave core.

In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: a reply unit (not shown in the figure) configured to reply the response acknowledgement message in response to determining that the role is a slave core and receiving the master core acknowledgement signal. The master core acknowledge signal may be used to notify the existence of the master core.

In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: a flush unit (not shown in the figure) configured to perform a flush according to a flush instruction received through inter-core communication in response to determining that the role is the slave core.

In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: an upgrade confirmation unit (not shown in the figure) configured to determine whether or not an upgrade can be performed by external communication using the target CPU core, in response to the determination that the role is the primary core; an updating unit (not shown in the figure) configured to update the role of the target CPU core to the slave core in response to determining that the target CPU core cannot be upgraded by the external communication.

In some optional implementations of the present embodiment, the upgrade confirmation unit may be further configured to: detecting a communication state with the SOC external device; in response to determining that the external communication state is abnormal, it is determined that the upgrade by the external communication using the target CPU core cannot be performed.

In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: a sending unit (not shown in the figure) configured to: and responding to the fact that the role is the main core, and sending a flash instruction to the CPU core with the role as the auxiliary core on the SOC through inter-core communication according to the detected upgrading instruction from the outside of the SOC.

In some optional implementations of the present embodiment, the apparatus 400 for system-on-chip upgrade may be further configured to: detecting whether a preset configuration file is updated or not; in response to determining that the preset configuration file update is detected, re-reading the updated configuration file; based on the updated configuration file, the role of the target CPU core is determined.

In some optional implementations of this embodiment, the apparatus 400 for system-on-chip upgrade may further include: a master core determination unit (not shown in the figure) configured to: and determining that the current role of the target CPU core is the main core in response to receiving an arbitration result for indicating that the role of the target CPU core is the main core. Wherein the arbitration result may be generated by an arbitration method participated by at least two CPU cores on the SOC.

In the apparatus provided in the foregoing embodiment of the present disclosure, each CPU core of the system on chip reads a preset configuration file through the reading unit 401, and determines that the CPU core is in a role of a master core or a slave core through the determining unit 402, and the execution unit 403 causes the CPU core in the role of the master core to assume functions of external communication and upgrading, and the CPU core in the role of the slave core stops the external communication, so that the dynamic determination of the roles of the master core and the slave core is realized, and a basis is provided for ensuring the reliability of upgrading of the entire system on chip.

In the technical scheme of the disclosure, the collection, storage, use, processing, transmission, provision, disclosure and other processing of the personal information of the related user are all in accordance with the regulations of related laws and regulations and do not violate the good customs of the public order.

The present disclosure also provides a system on chip, a readable storage medium, a computer program product, an autonomous vehicle, and a roadside apparatus according to embodiments of the present disclosure.

FIG. 5 illustrates a schematic block diagram of an example system on a chip 500 that may be used to implement embodiments of the present disclosure. The system on a chip 500 may be installed in various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

The autonomous vehicle provided by the present disclosure may include the above-described system-on-chip 500 as shown in fig. 5.

The roadside apparatus provided by the present disclosure may include a communication component and the like in addition to the above-described system on chip 500 shown in fig. 5, and the above-described system on chip 500 may be integrated with the communication component, or may be provided separately. The system on chip 500 may acquire data of a sensing device (e.g., a roadside camera), such as pictures and videos, for image video processing and data calculation.

As shown in fig. 5, the system on chip 500 includes a computing unit 501, which may perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM)502 or a computer program loaded from a storage unit 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The calculation unit 501, the ROM 502, and the RAM 503 are connected to each other by a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.

A number of components in the device 500 are connected to the I/O interface 505, including: an input unit 506 such as a keyboard, a mouse, or the like; an output unit 507 such as various types of displays, speakers, and the like; a storage unit 508, such as a magnetic disk, optical disk, or the like; and a communication unit 509 such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The computing unit 501 may be a variety of general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The computing unit 501 performs the various methods and processes described above, such as methods for system-on-chip upgrade. For example, in some embodiments, the method for system-on-chip upgrade may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 500 via the ROM 502 and/or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the method for system-on-chip upgrade described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured by any other suitable means (e.g., by means of firmware) to perform a method for system-on-chip upgrade.

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel or sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for system-on-chip (SOC) upgrade applied to a target Central Processing Unit (CPU) core, the SOC including at least two CPU cores, the target CPU core being one of the at least two CPU cores, comprising:

reading a preset configuration file;

determining the role of the target CPU core based on the preset configuration file, wherein the role comprises a main core or a slave core;

according to the determined role, performing one of: in response to determining that the role is a primary core, performing primary core flashing according to a detected upgrade instruction from the outside of the SOC; in response to determining that the role is a slave core, ceasing communication with outside the SOC.

2. The method of claim 1, wherein said determining the role of the target CPU core based on the preset configuration file comprises:

in response to determining that the preset configuration file indicates that the role of the target CPU core is a main core, sending a main core confirmation signal to other CPU cores on the SOC through inter-core communication, wherein the main core confirmation signal is used for notifying the existence of the main core;

determining a role of the target CPU core based on the received response acknowledgement information corresponding to the master acknowledgement signal.

3. The method of claim 2, wherein said determining the role of the target CPU core based on the received response acknowledgement information corresponding to the master acknowledgement signal comprises:

in response to receiving response confirmation information corresponding to the main core confirmation signal, performing recheck according to the preset configuration file;

and determining the role of the target CPU core according to the result of rechecking of the preset configuration file.

4. The method of claim 3, wherein the determining the role of the target CPU core according to the result of the rechecking according to the preset configuration file comprises:

and in response to determining that the re-checking result according to the preset configuration file indicates that the role of the target CPU core is the main core, determining that the role of the target CPU core is the main core.

And determining that the role of the target CPU core is a slave core in response to determining that the result of rechecking according to the preset configuration file indicates that the role of the target CPU core is not a master core.

5. The method of any of claims 1-4, wherein said determining the role of the target CPU core based on the preset configuration file comprises:

and determining that the role of the target CPU core is a slave core in response to determining that the preset configuration file indicates that the role of the target CPU core is not a master core.

6. The method according to one of claims 1-5, wherein the method further comprises:

responding to response confirmation information in response to the fact that the role is the slave core and receiving a master core confirmation signal, wherein the master core confirmation signal is used for informing the existence of the master core.

7. The method according to one of claims 1-6, wherein the method further comprises:

in response to determining that the role is a slave core, performing a flush according to a flush instruction received through inter-core communication.

8. The method according to one of claims 1-5, wherein the method further comprises:

in response to determining that the role is a primary core, determining whether an upgrade can be performed through external communication using the target CPU core;

updating the role of the target CPU core to a slave core in response to determining that the target CPU core cannot be upgraded via external communication.

9. The method of claim 8, wherein the determining whether an upgrade can be performed using the target CPU core through external communication comprises:

detecting a communication state with the SOC external device;

in response to determining that the external communication state is abnormal, determining that upgrading by external communication using the target CPU core cannot be performed.

10. The method according to one of claims 1-9, wherein the method further comprises:

and responding to the condition that the role is the main core, and sending a flash instruction to the CPU core with the role as the auxiliary core on the SOC through inter-core communication according to the detected upgrade instruction from the outside of the SOC.

11. The method of any of claims 1-10, wherein the upgrade instructions from outside the SOC are used to instruct an upgrade of a vehicle software system.

12. The method according to one of claims 1-11, wherein the method further comprises:

detecting whether the preset configuration file is updated or not;

in response to determining that the preset configuration file is detected to be updated, re-reading the updated configuration file;

determining the role of the target CPU core based on the updated configuration file.

13. The method according to one of claims 1 to 12, wherein the method further comprises:

determining that the target CPU core is currently in a master role in response to receiving an arbitration result indicating that the target CPU core is in the master role, wherein the arbitration result is generated by an arbitration method participated in by at least two CPU cores on the SOC.

14. An apparatus for system-on-chip (SOC) upgrade applied to a target Central Processing Unit (CPU) core, the SOC including at least two CPU cores, the target CPU core being one of the at least two CPU cores, comprising:

a reading unit configured to read a preset configuration file;

a determining unit configured to determine a role of the target CPU core based on the preset configuration file, wherein the role includes a master core or a slave core;

an execution unit configured to execute, according to the determined role, one of: in response to determining that the role is a primary core, performing primary core flashing according to a detected upgrade instruction from the outside of the SOC; in response to determining that the role is a slave core, ceasing communication with outside the SOC.

15. A system-on-chip SOC, comprising:

at least two homogeneous CPU cores, wherein the at least two homogeneous CPU cores comprise a CPU core as a master core and at least one CPU core as a slave core; and

a memory communicatively coupled to the at least two homogeneous CPU cores; wherein the content of the first and second substances,

the memory stores instructions executable by the at least two homogeneous CPU cores to enable the at least one CPU core to perform the method of any of claims 1-13.

16. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-13.

17. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-13.

18. An autonomous vehicle comprising the system-on-chip SOC of claim 15.

19. A roadside apparatus comprising the system on chip SOC of claim 15.