CN114281295B - Image processing method and device and LED display screen system - Google Patents
Image processing method and device and LED display screen system Download PDFInfo
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Abstract
The application relates to an image processing method, an image processing device and an LED display screen system; the image processing method comprises the following steps: receiving frame image data of an input source and writing the frame image data into a storage unit according to a first field signal; performing phase shift on the first field signal according to offset information between the frame image data starting point and the effective image data starting point to obtain a second field signal; and obtaining a data reading enabling signal according to the second field signal and the data reading enabling delay time length, and reading and outputting effective image data from the storage unit according to the data reading enabling signal. The method can solve the problem that when the offset of an input source is larger, the read data enabling signal is pulled up later, so that the effective part of image data to be output is sent incompletely, and the LED display screen is wrong in display.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an image processing method, an image processing device, and an LED display system.
Background
In the current LED display screen system, an LED display screen controller is responsible for storing an input source processed by a front-end video processing channel, reading the input source, framing according to a network protocol, sending the input source to an LED display screen scanning card through an image output interface such as a network port or an optical port, and lighting the LED display screen through the LED display screen scanning card. The processing procedure of the input source in the LED display screen controller is generally carried out by taking a frame as a unit, the whole frame is operated, a ping-pong frame mode is generally adopted when the input source is stored by an external storage unit (such as DDR), and an A frame is written and a B frame is read, so that the delay of one frame is increased. In order to reduce the processing delay of the existing system, the current scheme is to read and write the same frame, so that the processing delay of the whole system is lower than that of normal processing.
In the processing of the input source, the start of a frame is usually characterized by the edges of the field signal Vs, for example, a frame reset is performed when the rising edge of Vs comes, the processing flow of the current frame is started, and the processing of the next frame is started when the rising edge of the next Vs comes. The control input source in conventional processing writes and reads from the DDR with the same VS signal, and starts reading after writing a portion of the data, e.g., 10 lines of data, in the DDR. The offset of the input source means that only part of the image data in one frame of image data is read out and output to the receiving card, and the larger the offset of the input source is, the smaller the effective part of the image is.
When the offset of the input source is larger, since the read data needs to be written through the invalid part of the image and the part of the valid image, the enable signal of the read data is pulled up later, and when the next rising edge of the VS signal arrives, the valid part of the image data is not sent yet, so that a display error occurs in the display area of the LED display screen.
Disclosure of Invention
Therefore, the embodiment of the application provides an image processing method, an image processing device and an LED display screen system, which can solve the problems that when the offset of an input source is large, a read data enabling signal is pulled high later, so that the effective part of image data is sent incompletely, and the LED display screen has image residues or images.
Specifically, an embodiment of the present application proposes an image processing method, including: receiving frame image data of an input source and writing the frame image data into a storage unit according to a first field signal of the input source; the frame image data starts to be written into the storage unit from a frame image data starting point, and phase shifting is carried out on the first field signal according to offset information between the frame image data starting point and an effective image data starting point to obtain a second field signal; obtaining a data reading enabling signal according to the second field signal and the data reading enabling delay time length, and obtaining the effective image data in the storage unit according to the data reading enabling signal; and outputting the valid image data.
In the prior art, the writing and reading of an input source are controlled by adopting the same field signal, when the offset of the input source is larger, a read data enabling signal is pulled up later, so that the transmission of the excessive part of image data carried by a network port or the effective part of the image data of the input source is incomplete, and the problem of image residues or screen images of an LED display screen is caused. According to the embodiment, the writing and reading of the input source are respectively controlled through the first field and the second field signals with the same period and different phases, when the image offset is larger, the image data of the effective area carried by the data output interface can still be ensured to be completely read and transmitted, and the problem that the image data is incompletely transmitted, so that the image residues or the screen images appear on the LED display screen is avoided.
In an embodiment of the present application, the offset information includes an offset data line number and an offset data amount of each line, and the performing phase offset on the first field signal according to the offset information between the frame image data start point and the effective image data start point to obtain the second field signal specifically includes: determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line; and delaying the clock phase of the first field signal by the phase delay time length to obtain the second field signal.
In one embodiment of the present application, the determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data amount of each line includes: calculating offset data according to the offset data line number and the offset data of each line; calculating the phase delay time length according to the offset data quantity and the data writing speed; wherein the offset data amount is equal to a product of the offset data line number and the offset data amount per line; the phase delay period is equal to a quotient of the offset data amount and the data writing speed.
In one embodiment of the present application, the number of offset data lines is smaller than the number of frame image data lines of the frame image data, and the amount of offset data per line is smaller than the amount of frame image data per line of the frame image data.
In one embodiment of the present application, the image processing method further includes: and reading supplemental image data other than the frame image data according to the data reading enable signal, and outputting the supplemental image data.
In addition, an embodiment of the present application proposes an image processing apparatus including: the data writing module is used for receiving frame image data of an input source and writing the frame image data into the storage unit according to a first field signal of the input source; the signal obtaining module is used for carrying out phase shift on the first field signal according to offset information between the frame image data starting point and the effective image data starting point to obtain a second field signal; a data reading module, configured to obtain a data reading enable signal according to the second field signal and a data reading enable delay duration, and obtain the valid image data from the storage unit according to the data reading enable signal; and a data output module for outputting the effective image data.
In one embodiment of the present application, the offset information includes an offset data line number and an offset data amount per line; the signal obtaining module is specifically configured to: determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line; and delaying the clock phase of the first field signal by the phase delay time length to obtain the second field signal.
In one embodiment of the present application, the determining, by the signal obtaining module, a phase delay duration of the second field signal with respect to the first field signal according to the offset data line number and the offset data amount of each line includes: calculating offset data according to the offset data line number and the offset data of each line; calculating the phase delay time length according to the offset data quantity and the data writing speed; wherein the offset data amount is equal to a product of the offset data line number and the offset data amount per line; the phase delay period is equal to a quotient of the offset data amount and the data writing speed.
In one embodiment of the present application, the image processing apparatus further includes: and the data supplementing module is used for reading the supplementing image data except the frame image data according to the data reading enabling signal and outputting the supplementing image data.
Furthermore, an embodiment of the present application provides an LED display system, including: an LED display screen controller; the LED display screen scanning card is connected with the LED display screen controller; the LED display screen is connected with the LED display screen scanning card; the LED display screen controller is used for executing the image processing method according to any one of the embodiments.
Furthermore, an embodiment of the present application provides an image processing system, including: a memory storing a computer program, and a processor executing the image processing method according to any one of the embodiments described above.
Furthermore, an embodiment of the present application proposes a computer-readable storage medium storing computer-executable instructions for performing the image processing method according to any one of the embodiments described above.
From the above, the technical features of the present application may have beneficial effects: the writing and reading of the input source are respectively controlled through two field signals with the same period and different phases, when the image offset is larger, the image data of the effective area carried by the data output interface and the image data of the exceeding area can be completely read and transmitted, and the problems of image residues or screen images of the LED display screen caused by incomplete image data transmission are avoided.
Other aspects of the features of the present application will become apparent from the following detailed description, which refers to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for the purposes of illustration and not as a definition of the limits of the application. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a flowchart of an image processing method according to a first embodiment of the present application;
fig. 2 is a schematic diagram of a specific processing manner of an image processing method according to a first embodiment of the present application;
FIG. 3 is a schematic diagram showing a specific processing mode of image processing in the prior art;
fig. 4 is a schematic structural view of an image processing apparatus according to a second embodiment of the present application;
fig. 5 is a schematic structural view of still another image processing apparatus according to a second embodiment of the present application;
fig. 6 is a schematic structural diagram of an LED display system according to a third embodiment of the present application;
fig. 7 is a schematic structural diagram of an image processing system according to a fourth embodiment of the present application;
fig. 8 is a schematic structural view of a computer scale storage medium according to a fifth embodiment of the present application.
Description of the reference numerals
S11-S15: a step of an image processing method;
20: an image processing device; 201: a data writing module; 203: a signal obtaining module; 205: a data reading module; 207: a data reading module; 209: a data supplementing module;
30: an LED display screen system; 31: an LED display screen controller; 32: an LED display screen scanning card; 33: an LED display screen;
40: an image processing system; 41: a processor; 42: a memory;
50: computer readable storage media.
Detailed Description
It should be noted that, without conflict, the embodiments and features of the embodiments in the present application may be combined with each other. The present application will be described below with reference to the accompanying drawings in conjunction with the embodiments.
In order to enable those of ordinary skill in the art to better understand the technical solutions of the present application, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments, but not all embodiments, of the present application and should be within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are applicable to distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, it is possible to provide a device for the treatment of a disease. The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be further noted that the division of the embodiments in this application is only for convenience of description, and should not be construed as a specific limitation, and features in the various embodiments may be combined and mutually referenced without contradiction.
[ first embodiment ]
As shown in fig. 1, a first embodiment of the present application proposes an image processing method, for example, including steps S11 to S17.
Step S11: receiving frame image data of an input source and writing the frame image data into a storage unit according to a first field signal of the input source;
step S13: the frame image data starts to be written into the storage unit from a frame image data starting point, and phase shifting is carried out on the first field signal according to offset information between the frame image data starting point and an effective image data starting point to obtain a second field signal;
step S15: obtaining a data reading enabling signal according to the second field signal and the data reading enabling delay time length, and reading the effective image data in the frame image data from the storage unit according to the data reading enabling signal;
step S17: outputting the effective image data.
In step S11, frame image data of an input source is received, for example, by an LED display controller and written to a storage unit according to a first field signal of the input source. The LED display controller mentioned is, for example, a transmitting card in the LED display system, which includes, for example, a video source input interface such as HDMI (High Definition Multimedia Interface ) or DVI (Digital Visual Interface, digital video interface), a programmable logic device such as FPGA (Field Programmable Gate Array), a microcontroller such as MCU (Microcontroller Unit), and a memory such as a volatile memory including a Flash memory and a nonvolatile memory, and is, for example, a memory such as SDRAM (synchronous dynamic random-access memory), DDR (Double Data Rate), DDR1, DDR2, and the like. The image output interface herein may be, for example, an ethernet interface (or referred to as a network port), an optical fiber interface (or referred to as an optical port), or the like.
The input source mentioned is, for example, a medium such as video, picture, text, etc., the frame image data mentioned is image data in units of frames in the input source, the LED display screen controller receives the image data, for example, frame by frame, and writes the received image data in a storage unit, for example, a volatile memory such as DDR. The mentioned field signal is, for example, a field synchronizing signal, for controlling the input source to be written into or read from the memory cell, as shown in fig. 2, the first field signal Vs1 controls the write data, the second field signal Vs2 controls the read data, the edges of the field signal characterize the start of a frame, the frame reset is performed at the rising edge, the processing flow of the previous frame is started, and the processing of the next frame is started at the next rising edge.
In step S13, the frame image data is written into the storage unit from a frame image data start point, for example, from the LED display screen controller to the second field signal by shifting the clock phase of the first field signal according to the shift information between the frame image data start point and the effective image data start point. Since a plurality of image data are included in one frame image, for example, arranged in the form of data lines.
When writing frame image data, for example, writing is started from the first data of the first row as a starting point, and for one frame image, the LED display screen controller often outputs only a part of the one frame image, as shown in fig. 2, the S1 area and the S2 area together form one frame image, and the S2 area is image data to be output, that is, valid image data in the one frame image data. The offset information mentioned includes, for example, the number of offset data lines and the amount of offset data per line, for example, a direction is the data line direction, the image data of the S1 area and the S2 area are arranged along the a direction one line, the distance H of the S1 area and the S2 area in the data line direction indicates the number of offset data lines, for example, the distance H indicates 10 lines of image data, and the number of offset data lines is 10 lines. For example, the b direction is the data column direction, and the distance W between the S1 area and the S2 area in the data column direction represents the offset data amount per row, for example, the distance W represents 20 data, and the offset data amount per row is 20.
Further, performing phase shift on the first field signal according to the shift information to obtain a second field signal specifically includes: and determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line. Specifically, for example, the offset data amount is calculated according to the foregoing offset data line number and each line of offset data, and the calculation formula is as follows: offset data amount = offset data line number x offset data amount per line (i.e., W x H); and calculating the phase delay time length according to the offset data quantity and the data writing speed, wherein the calculation formula is as follows: phase delay time = offset data amount +.data writing speed. As shown in fig. 2, the phase delay time period is T1, and after the phase delay time period T1 is calculated, the clock phase of the first field signal Vs1 is delayed by the phase delay time period T1 to obtain the second field signal Vs2.
In step S15, a data read enable signal is obtained by the LED display controller, for example, from the second field signal Vs2 and the data read enable delay period. As shown in fig. 2, the data read enable signal K1 is obtained with the rising edge delay time period T2 of the second field signal Vs2 to the time period of the arrival of the second rising edge as a period of time T2.
The time period T2 indicates a time period T2 spent for writing the preset portion of the image data to the storage unit, and the image data of the S2 area is not read. As shown in fig. 2, for example, reading is started after writing 10 lines of data after T1 is continued, however, in other implementations of the present embodiment, the preset portion may be a user-defined number of lines of data, which is not limited to this application.
The image data of the loading area S2 is effective image data in one frame image, and the LED display controller reads the effective image data of the area S2 from the storage unit according to the data reading enable signal K1, for example. Therefore, the preset part of data is written first, then the data reading is started, the data writing speed is required to be greater than or equal to the data reading speed or the current frame of image data is completely written, the read data can be ensured to be the current frame of image data, the image data of the previous frame is prevented from being read, and a time allowance group data packet can be provided for the system and sent.
In step S17, the read effective image data is output, for example, by the LED display screen controller. As shown in fig. 3, a data transmission enable signal K2 may be obtained according to a clock period of the data read enable signal K1, and valid image data is output according to the data transmission enable signal K2.
Further, the offset data line number is smaller than the frame image data line number of the frame image data, for example, and the offset data amount per line is smaller than the frame image data amount per line of the frame image data, for example. The method can ensure that the effective image data output by the LED display screen controller does not exceed the range of the currently written frame image data, and avoid the situation of display errors on the LED display screen.
Further, the LED display screen controller needs to output supplementary image data other than the frame image data, such as S3 area in fig. 2, in addition to the effective image data in the frame image data, and the supplementary image data may be solid color data, such as red data, green data, blue data, black data, and the like. The supplementary image data is also read and transmitted according to the second field signal, for example, the reading is started after the reading of the effective image data is completed.
Because the data is read according to the second field signal, the second field signal is obtained by delaying the clock phase by the first time length by the first field signal, in one processing period of the second field signal, the read data can be ensured to be the data of the current frame, and the effective image data and the supplementary image data can be ensured to be completely read and transmitted in the processing period.
In order to further understand the technical solutions and advantageous effects of the present application, the following description of the present embodiment is given in connection with the prior art.
Fig. 3 is a schematic diagram showing a specific processing manner of image processing in the prior art, and as shown in fig. 3, the first field signal Vs1 is used for controlling writing data into and reading data from the memory cell. Since the image is shifted, the effective image data needs to be read after the first time period T1 consumed for writing the image data of the S1 area and the second time period T2 consumed for writing the preset part of the effective image data of the S2 area.
If the supplementary image data of the S3 area that the LED display controller needs to output is relatively large when the image offset is large, and the frame reset is performed when the second rising edge of the first field signal Vs1 arrives, the processing of the current frame needs to be stopped, at this time, a part of the supplementary image data of the S3 area may not be read yet, such as a hatched part in fig. 2, so that the part of the image is not updated on the LED display, resulting in a residual abnormal image on the LED display.
In addition, if the second rising edge of the first field signal Vs1 comes immediately when the writing of the image data is completed and the image offset is too large, for example, only 10 lines of effective image data are reserved, and the preset portion is also 10 lines of data, the frame reset is performed when the effective area S1 is not yet read, so that the effective image data is not transmitted, resulting in the LED display screen being patterned.
In the technical solution of the present embodiment, as shown in fig. 2, the first field signal Vs1 is used to control write data and the second field signal Vs2 is used to control read data, respectively. The second field signal Vs2 is obtained by delaying the clock phase by the first field signal Vs1 by the first time period T1, the first time period is the time period consumed by writing the image data of the S1 area, and the clock periods of the first field signal Vs1 and the second field signal Vs2 are the same, so that the second rising edge of the second field signal Vs2 correspondingly lags behind the first time period T1, and the effective image data of the S2 area and the supplementary image data of the S3 area which need to be output by the LED display screen controller can be ensured to be completely transmitted.
In summary, in the first embodiment of the present application, frame image data is written according to the first field signal, clock phases of the first field signal are shifted according to shift information of the frame image data to obtain the second field signal, a data reading enabling signal is obtained according to the second field signal and a data reading enabling delay time, effective image data in the image data is read according to the data reading enabling signal and is output, writing and reading of an input source are respectively controlled by two field signals with the same period and different phases, when the image shift is larger, it can still be ensured that the effective area image data and the exceeding area image data carried by the data output interface are completely read and transmitted, and the problem that the image data is incompletely transmitted, so that image residues or images are left on an LED display screen is avoided.
[ second embodiment ]
As shown in fig. 4, a second embodiment of the present application proposes an image processing apparatus. The image processing apparatus 20 includes, for example: a data writing module 201, a signal obtaining module 203, a data reading module 205 and a data outputting module 207.
Wherein the data writing module 201 is configured to receive frame image data of an input source and write the frame image data into a storage unit according to a first field signal of the input source. The frame image data is written into the storage unit from a frame image data starting point, and the signal obtaining module 203 is configured to obtain a second field signal by performing phase shift on the first field signal according to offset information between the frame image data starting point and an effective image data starting point. The data reading module 205 is configured to obtain a data reading enable signal according to the second field signal and a data reading enable delay period, and read the valid image data in the frame image data from the storage unit according to the data reading enable signal. The data output module 207 is configured to output the valid image data.
Further, the offset information includes an offset data line number and an offset data amount per line; the signal obtaining module 203 is specifically configured to: determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line; and delaying the clock phase of the first field signal by the phase delay time length to obtain the second field signal.
Further, the determining, by the signal obtaining module 203, a phase delay duration of the second field signal relative to the first field signal according to the offset data line number and the offset data amount of each line includes: calculating offset data according to the offset data line number and the offset data of each line; calculating the phase delay time length according to the offset data quantity and the data writing speed; wherein the offset data amount is equal to a product of the offset data line number and the offset data amount per line; the phase delay period is equal to a quotient of the offset data amount and the data writing speed.
Further, as shown in fig. 5, the image processing apparatus 20 further includes, for example: a data complement module 209 for reading complement image data other than the frame image data according to the data read enable signal, and outputting the complement image data.
The specific functional details of the data writing module 201, the signal obtaining module 203, the data reading module 205, the data outputting module 207, and the data supplementing module 209 may refer to the relevant descriptions of steps S11, S13, S15, and S17 in the foregoing first embodiment, and will not be repeated herein.
Furthermore, it should be noted that the data writing module 201, the signal obtaining module 203, the data reading module 205, the data outputting module 207 and the data supplementing module 209 may be software modules, which may be integrated into the programmable logic device in the LED display controller in the foregoing first embodiment.
[ third embodiment ]
As shown in fig. 6, a third embodiment of the present application proposes an LED display system. The LED display system 30 includes, for example: an LED display controller 31, an LED display scan card 32, and an LED display 33. The LED display screen scanning card 32 is connected with the LED display screen controller 31, and the LED display screen 33 is connected with the LED display screen scanning card 32.
Wherein the LED display screen controller 31 is used to implement the image processing method as described in the first embodiment. The specific image processing method may refer to the method described in the first embodiment, which is not described herein for brevity, and the beneficial effects of the LED display system 30 provided in this embodiment are the same as those of the image processing method provided in the first embodiment.
[ fourth embodiment ]
As shown in fig. 7, a fourth embodiment of the present application proposes an image processing system. The image processing system 40 includes, for example: a memory 42 and one or more processors 41 coupled to the memory 42. The memory 42 stores a computer program, and the processor 41 is configured to execute the computer program to implement the image processing method as described in the first embodiment. The specific image processing method may refer to the method described in the first embodiment, which is not described herein for brevity, and the beneficial effects of the image processing system 40 provided in this embodiment are the same as those of the image processing method provided in the first embodiment.
[ fifth embodiment ]
Fig. 8 is a computer readable storage medium according to a fourth embodiment of the present application. As shown in fig. 8, the computer-readable storage medium 50 is a nonvolatile memory and stores computer-readable instructions that, when executed by one or more processors, for example, cause the one or more processors to perform the image processing method described in the foregoing first embodiment. The specific image processing method may refer to the method described in the first embodiment, which is not described herein for brevity, and the beneficial effects of the computer readable storage medium 50 provided in this embodiment are the same as those of the image processing method provided in the first embodiment.
In addition, it is understood that the foregoing embodiments are merely exemplary descriptions of the present application, and the technical solutions of the embodiments may be arbitrarily combined and matched without conflict in technical features and contradiction in structure and without departing from the purpose of the present application.
In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and/or methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and the division of the units/modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units/modules described as separate units may or may not be physically separate, and units/modules may or may not be physically units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit/module in the embodiments of the present application may be integrated in one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated in one unit/module. The integrated units/modules may be implemented in hardware or in hardware plus software functional units/modules.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (6)
1. An image processing method, comprising:
receiving frame image data of an input source and writing the frame image data into a storage unit according to a first field signal of the input source;
the frame image data starts to be written into the storage unit from a frame image data starting point, and phase shifting is carried out on the first field signal according to offset information between the frame image data starting point and an effective image data starting point to obtain a second field signal;
obtaining a data reading enabling signal according to the second field signal and the data reading enabling delay time length, and reading the effective image data in the frame image data from the storage unit according to the data reading enabling signal; and
outputting the effective image data;
the step of performing phase shift on the first field signal according to the offset information between the frame image data starting point and the effective image data starting point to obtain a second field signal specifically includes:
determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line;
delaying the clock phase of the first field signal by the phase delay time length to obtain the second field signal;
the determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line comprises:
calculating offset data according to the offset data line number and the offset data of each line;
calculating the phase delay time length according to the offset data quantity and the data writing speed;
wherein the offset data amount is equal to a product of the offset data line number and the offset data amount per line; the phase delay period is equal to a quotient of the offset data amount and the data writing speed.
2. The image processing method according to claim 1, wherein the number of offset data lines is smaller than the number of frame image data lines of the frame image data, and the amount of offset data per line is smaller than the amount of frame image data per line of the frame image data.
3. The image processing method according to claim 1, characterized by further comprising:
and reading supplemental image data other than the frame image data according to the data reading enable signal, and outputting the supplemental image data.
4. An image processing apparatus, comprising:
the data writing module is used for receiving frame image data of an input source and writing the frame image data into the storage unit according to a first field signal of the input source;
the signal obtaining module is used for carrying out phase shift on the first field signal according to offset information between the frame image data starting point and the effective image data starting point to obtain a second field signal;
a data reading module, configured to obtain a data reading enable signal according to the second field signal and a data reading enable delay duration, and read the valid image data in the frame image data from the storage unit according to the data reading enable signal; and
the data output module is used for outputting the effective image data;
the offset information comprises an offset data line number and each line of offset data quantity; the signal obtaining module is specifically configured to:
determining the phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line;
delaying the clock phase of the first field signal by the phase delay time length to obtain the second field signal;
the signal obtaining module determining a phase delay time length of the second field signal relative to the first field signal according to the offset data line number and the offset data quantity of each line comprises:
calculating offset data according to the offset data line number and the offset data of each line;
calculating the phase delay time length according to the offset data quantity and the data writing speed;
wherein the offset data amount is equal to a product of the offset data line number and the offset data amount per line; the phase delay period is equal to a quotient of the offset data amount and the data writing speed.
5. The image processing apparatus according to claim 4, further comprising:
and the data supplementing module is used for reading the supplementing image data except the frame image data according to the data reading enabling signal and outputting the supplementing image data.
6. An LED display screen system, comprising:
an LED display screen controller;
the LED display screen scanning card is connected with the LED display screen controller;
the LED display screen is connected with the LED display screen scanning card;
wherein the LED display controller is configured to perform the image processing method according to any one of claims 1 to 3.
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