CN114281251B

CN114281251B - Data distribution and reprogramming optimization method for 3D TLC flash memory

Info

Publication number: CN114281251B
Application number: CN202111506480.5A
Authority: CN
Inventors: 龙林波; 黄金鹏; 蒋溢; 彭崎翔; 郑健聪
Original assignee: Chongqing University of Post and Telecommunications
Current assignee: Chongqing University of Post and Telecommunications
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2023-08-11
Anticipated expiration: 2041-12-10
Also published as: CN114281251A

Abstract

The invention relates to a data distribution and reprogramming optimization method for a 3D TLC flash memory, and belongs to the technical field of flash memory performance. The method comprises the following steps: s1: caching the temporarily accessed request data by means of a flash memory controller buffer area, and dividing the data into cold and hot read-write data according to the access characteristics of the request data; s2: classifying hot-write data according to the heat of the hot-write data, and establishing a multi-stage heat linked list; s3: according to the type and heat degree of the request data, combining two hot-writing data with highest heat degree with one hot-reading data, and respectively storing the hot-writing data and the hot-reading data in CSB, LSB, MSB pages of one word line; s4: and designing a reprogramming method based on the limiting layer number according to the limiting layer number of the 3D flash memory reprogramming. The invention provides a corresponding data distribution algorithm and reprogramming, realizes a flash memory controller layer and improves the read-write performance of the flash memory.

Description

Data distribution and reprogramming optimization method for 3D TLC flash memory

Technical Field

The invention belongs to the technical field of flash memory performance, and relates to a data distribution and reprogramming optimization method for a 3DTLC flash memory.

Background

With the advent of the big data age, higher demands are being placed on the capacity, performance, reliability, etc. of storage systems. In conventional memory systems, planar flash memory is the dominant. Unlike a two-dimensional flash memory, a three-dimensional flash memory increases capacity by stacking flash memory cells in a vertical direction. A typical three-dimensional flash block is made up of hundreds of layers. In general, each word line contains 64K to 128K flash memory cells, which may be SLC (Single layer memory cell mode), MLC (double layer memory cell mode), TLC (double triple layer memory cell mode) or QLC (four layer memory cell mode). A flash memory cell is a floating gate transistor that can store different charges in the floating gate, resulting in different voltages. The range of voltages may be divided into a plurality of voltage intervals to represent different values. In recent years, because three-dimensional stacked (3D) flash memory has better performance and storage density, the current advanced memory devices are all based on 3D flash memory. Therefore, how to optimize the 3D flash memory becomes a research hotspot in the current storage field.

The time delay is different for reading data at different positions on the flash memory unit for reading LSB (least significant bit), CSB (middle significant bit) and MSB (most significant bit). If the data on the LSB or CSB is invalid, an Invalid Data Aware (IDA) encoding technique is designed to incorporate duplicate voltage states in order to reduce the number of times the CSB or MSB voltage is identified. As shown in fig. three, if the LSB and CSB bits are not valid, the voltage states P1, P2, and P5 may be shifted to P5, and at the same time, P0, P3, and P4 may be shifted to P7. Likewise, if the LSB bit is not valid, P1, P2, P3, or P4 may be moved to P8, P7, P6, or P5, respectively. This may cause the read delay of the CSB page to approach the read delay of the LSB page, which is close to the read delay of the CSB page or the LSB page, respectively. While its validity is limited by the location of invalid data, which has the same probability of being present on LSB, CSB and SLC pages.

It is found through experimental verification that a significant proportion of data is frequently updated in most of the data, and the data with larger thermal reading accounts for a significant proportion of the data, that is, a part of the data can be updated in a shorter time, so that no optimization and improvement technology is provided in the prior art.

Disclosure of Invention

In view of the above, the present invention is directed to a data distribution and reprogramming optimization method for a 3DTLC flash memory. By identifying the cold and hot data, distinguishing the cold and hot data and modifying the distribution mode of the data, the invention optimizes the performance of the traditional reprogramming method.

In order to achieve the above purpose, the present invention provides the following technical solutions:

a data distribution and reprogramming optimization method for a 3D TLC flash memory comprises the following steps:

s1: caching the temporarily accessed request data by means of a flash memory controller buffer area, and dividing the data into hot read, hot write, cold read and cold write data according to the access characteristics of the request data;

s2: classifying the hot-write data according to the hot-write data, and establishing a multi-level hot-write linked list, wherein the higher the linked list level is, the higher the data hot degree is;

s3: according to the type and heat of the request data, a new data distribution optimization method is provided, two hot-writing data with highest heat and one hot-reading data are combined and respectively stored in CSB, LSB, MSB pages of one word line, so that average write request performance is improved;

s4: according to the limit layer number of 3D flash memory reprogramming, a reprogramming method based on the limit layer number is designed, and after CSB and LSB pages are updated, the reading performance of the thermal read data of the corresponding MSB page is improved.

Further, the step S1 includes: the method comprises the steps that data are stored through a request buffer area in a controller of an SSD, and the data are distinguished to be cold or hot through a heat filter; when the request queue enters the heat filter, judging whether the data is written for the first time, if so, recording the writing time of the data, and storing the data into a traditional programming area for traditional programming operation; if not, the data is distinguished by a heat filter, and the distinguished hot data is stored in a request buffer.

Further, in the step S1, the data is divided into read data and write data according to the access operation of the request data, the two access time intervals of the request data are calculated, if the time interval is less than one second, the data are divided into hot read data or hot write data, otherwise, the data are divided into cold read data or cold write data.

Further, in the step S2, a plurality of special linked lists are maintained in the request buffer of the controller to store hot data with the same update time, all data stored in the same linked list have the same heat, the data are updated at the same time point, a time line is always provided in the linked list, the time line is automatically advanced every other time period, and the data stored in the linked list are migrated to the linked list corresponding to the current update time; and setting a specified fixed time period as m, storing the hot data in the request buffer area into a linked list corresponding to the update time of the hot data, judging whether the data linked list has the time m, and if so, migrating the data in the original data linked list into the linked list corresponding to the data update time m.

Further, the step S2 specifically includes: the heat of the data represents the predicted time of the data to be accessed next time, and the higher the linked list level is, the higher the heat is, which represents the faster the data to be accessed; the step of establishing the heat linked list comprises the following steps:

s21: the new request data takes the time interval of the last two accesses as the heat, and adds into the corresponding linked list;

s22: and updating the heat of the data in the linked list at intervals of m, subtracting the time m from the heat of the data, and adding a new linked list again.

Further, the step S3 specifically includes: the method comprises the steps of taking hot data updated simultaneously at the front end parts of two linked lists, sending a cold data request to a heat filter by a buffer space, writing the frequently read cold data and hot write data in the linked list into TLC flash memory units together, writing the two simultaneously updated hot data into the first two LSBs and CSBs of the flash memory units, writing the frequently read cold data into the last MSB of the flash memory units, invalidating the first two LSBs and CSBs of the flash memory units when data update occurs, only leaving the most significant bit MSB, combining the original eight voltage states of TLC, combining the overlapped parts to finally leave only two significant voltage states, and very effectively improving the reprogramming performance when the most significant bit MSB stores the frequently read data.

Further, in the step S3, when there is a new data request, the allocation is performed according to the new data allocation optimization method, which includes the following steps:

s31: judging whether the request data is hot read data, if so, reading the data and marking the data, otherwise, executing step S32;

s32: judging whether the request data is cold reading data, reading the data, otherwise executing step S33;

s33: judging whether the request data is hot writing data, if so, executing the step S34, and if not, executing the step S35;

s34: judging whether a buffer area in the FLASH controller has a free space, if so, storing the request data into the buffer area, otherwise, directly writing the request data into the FLASH memory;

s35: and judging whether hot writing request data in the request buffer area is larger than 2, if so, selecting two hot writing request data in the request buffer area and cold writing data currently requested to be written into the flash memory together, placing the two hot writing request data on LSB and CSB on the same word line, placing the cold writing request on MSB, and otherwise, directly writing the request data into the flash memory.

Further, in the step S4, when data enter the request buffer, it is first determined whether the buffer space is full, if the buffer space is full, it is determined whether there is data that can be removed from the front end of the linked list, if there is data that can be removed, it is further determined whether the buffer space is full, if there is no data that can be removed, the data and other data in the buffer are written back to the flash memory together, so that the present invention cannot ensure that two data that are updated at the same time are written back each time; if the buffer space is not full, the operations of step S2 and step S3 are performed.

Further, in the step S4, the reprogramming method based on the number of limiting layers includes the steps of:

s41: checking invalid LSB pages and CSB pages in the maximum limit layer times when the 3D flash memory is in a new layer;

s42: when LSB and CSB on the same word line fail at the same time, reprogramming can reduce the times of reading data detection voltage on MSB and reduce the time delay of reading data on MSB;

s43: and simultaneously writing newly written data into the flash memory block while reprogramming the invalid LSB and the word line of the CSB, thereby sharing the cost of re-layering.

The invention has the beneficial effects that: the invention digs the improvement of the performance of the cold and hot data layout and the reprogramming operation, reduces the data reading and writing time expenditure and the erasing frequency for determining the durability of the unit, improves the programming speed, increases the storage capacity, and optimizes the service life and the performance of the flash memory.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the specification.

Drawings

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:

FIG. 1 is a diagram of a data allocation scheme for I/O requests;

FIG. 2 is a diagram of a data distribution scheme during data migration;

FIG. 3 is four cases of data allocation;

fig. 4 is a voltage state transition diagram for an inactive perceptual coding technique.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.

Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to limit the invention; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc., that indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or suggesting that the referred device or element must have a specific azimuth, be constructed and operated in a specific azimuth, so that the terms describing the positional relationship in the drawings are merely for exemplary illustration and should not be construed as limiting the present invention, and that the specific meaning of the above terms may be understood by those of ordinary skill in the art according to the specific circumstances.

Referring to fig. 1 to 4, the present invention improves the performance of the flash memory by using the difference between the hot and cold data to place the data in the ideal position of the flash memory cell and invoking the new reprogramming method of the present invention. In the process, the data can enter the buffer space through the heat filter, and if the flash memory space is full and no data which can be eliminated exists in the data link list, the data and other data in the buffer memory are written back to the flash memory page together.

Fig. 1 is a flow of a data allocation method of an I/O request, where r is recorded as a read case, w is recorded as a write case, c is recorded as a cool case, h is recorded as a hot case, and the process starts in step 101, and then:

step 102: setting a request buffer area in a controller of an SSD to store data, making a difference value according to the two request time of the page, setting the request as a hot request when the difference value is smaller than a certain threshold value, setting the request as a cold request when the difference value is larger than the threshold value, and executing step 103 if the request is judged to be a hot reading request; if the request is a cold read request, executing step 104; if the request is a hot write request, execute step 105; the other performs step 108.

Step 103: if it is determined in step 102 that the request is a hot request and the request is to read data at a location on a flash page, then the location data is read and the page of data is marked.

Step 104: if it is determined in step 102 that the data read in the read request is cold read data, the data at the location is read normally.

Step 105: if it is determined in step 102 that the request condition is hot writing, it is determined whether there is free space in the buffer in the FLASH controller, if so, step 106 is executed, and if not, step 107 is executed.

Step 106: in step 105, it is determined that if there is free space in the buffer, the data required to be written by the request is directly written to the buffer in the FLASH controller.

Step 107: if there is no free space in the buffer in the step 105 judgment, the data is directly written into the FLASH memory page.

Step 108: in step 102, judging that the request condition is other, then judging whether the number of hot writing pages in the buffer is larger than 2, if the number of hot writing pages in the buffer is larger than 2, executing step 109; otherwise, step 110 is performed.

Step 109: it is determined in step 108 that the hot write page is greater than 2 in the buffer, at which time two hot write pages are selected and data allocation scheme 1 is performed to write hot write data onto the LSB and CSB and cold write data onto the MSB.

Step 110: in step 108, it is determined that the hot writing page in the buffer is less than or equal to 2, and at this time, the request page is written into the FLASH memory page.

In step 111, the data allocation method of the i/O request ends.

Flow chart 2 is a flow chart of the data allocation method at the time of data migration, starting from step 101, and then:

let r be the read case, w be the write case, c be the cool case, h be the hot case (e.g., the hot write page recorded as hw)

Step 102: if hw is greater than or equal to 2& hr is greater than or equal to 1 in the page counter at this time, a loop is entered, and the loop comprises steps 102, 103 and 104.

Step 103: and selecting two hot write pages and one hot read page from the request Buffer to execute a data allocation strategy No. 2, wherein hot write data are allocated on LSB and CSB, and hot read data are allocated on MSB.

Step 104: because a portion of the requests in the buffer are completed in 103, the page case needs to be updated in the page counter, i.e., hw=hw-2, hr=hr-1.

Step 105: it is determined whether hr is greater than 0, and if so, step 107, or step 109 or step 111 is performed.

Step 106: if it is determined in step 105 that hr does not satisfy the condition, i.e., hr < =0, the remaining pages are written into the FLASH pages.

Step 107: if it is determined in step 105 that hr >0 is satisfied, it is determined whether 1<2×hr < cr is satisfied, if so, step 108 is executed, and if not, step 109 or step 111 is executed.

Step 108: if 1<2×hr++cr is satisfied in step 107, then the data allocation scheme 3 is executed, i.e. two hot-written data are written on LSB and CSB, respectively, and hot-read data are written on MSB, otherwise step 111 is executed.

Step 109: if it is determined in step 105 that hr satisfies the condition, i.e., hr >0, it is determined whether cr <2 x hr <4cr is satisfied.

Step 110: in step 108, if cr <2 x hr <4cr is satisfied in step 107, performing (2 hr-cr/3) data distribution scheme 3 to write two hot write data onto LSB and CSB, respectively, and write hot read data onto MSB; and performing (4 cr-hr)/3 times data distribution scheme 4 to write two hot read data onto LSB and CSB and one cold read data onto MSB.

Step 111: if it is determined in step 105 that hr satisfies the condition, i.e., hr >0, it is determined whether or not hr is satisfied.

Step 112: in step 111, if hr.gtoreq.2cr is satisfied in step 107, a data allocation scheme No. 3 is executed, two hot write data are written on LSB and CSB, respectively, and hot read data are written on MSB.

Step 113: and ending the data distribution mode during data migration.

Fig. 3 illustrates four cases of data allocation, allocation case 1: firstly, two hot-writing data pages are respectively programmed into an LSB page and a CSB page with lower writing time delay in one sub line, so that the writing performance is improved. Case 2 is allocated, i.e., two hot write requests are written on LSB and CSB to improve write performance and read performance. And if the number of hot writes in the buffer is less than 2, storing the hot read data page into a buffer area of the flash controller. If the buffer is not large enough to store all the hot read pages, we choose allocation case 3 and allocation case 4 to improve the read performance based on the proportion of hot read data in the remaining read data pages. The scheme in which case 3 is allocated is to put the data for hot reading on the LSB and the data for cold reading on the CSB and MSB. Allocation case 4 is to put the data for hot read on LSB and CSB and the data for cold read on MSB.

FIG. 4 is a voltage state transition diagram of an invalidation aware encoding technique for merging duplicate voltages when data on LSB or CSB is invalidated to reduce the number of times the identification voltage is read in CSB or MSB. As shown in fig. 4, if the LSB and CSB bits are not valid, the voltage states P1, P2, and P5 may be moved to P5, while P0, P3, and P4 may be moved to P7. Similarly, if the LSB bit is not valid, P1, P2, P3, or P4 may be moved to P8, P7, P6, or P5, respectively. Since the programming error is greatly improved when the reprogramming Cheng Cengshu is greater than 2 in the 3D TLC SSD, the maximum number of layers of reprogramming that we set is set to 2 to ensure correctness.

Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.

Claims

1. A data distribution and reprogramming optimization method for a 3DTLC flash memory is characterized in that: the method comprises the following steps:

s3: according to the type and heat of the request data, a new data distribution optimization method is provided, two hot-writing data with highest heat and one hot-reading data are combined and respectively stored in CSB, LSB, MSB pages of one wordline, so that average write request performance is improved; the step S3 specifically includes: the method comprises the steps that hot data which are updated simultaneously in front end parts of two linked lists are taken, a buffer space sends a cold data request to a heat filter, the cold data which are frequently read and the hot write data in the linked lists are written into TLC flash memory units together, the two hot data which are updated simultaneously are written into first two LSBs and CSBs of the flash memory units, the cold data which are frequently read are written into last MSBs of the flash memory units, when data updating occurs, the first two LSBs and the CSBs of the flash memory units are invalid, only the most significant bit MSBs are left, then a reprogramming method is applied, eight original voltage states of TLC are combined, and overlapped parts are combined to finally only two valid voltage states;

in the step S3, when there is a new data request, the allocation is performed according to a new data allocation optimization method, which includes the following steps:

s35: judging whether hot writing request data in a request buffer area is larger than 2, if so, selecting two hot writing request data in the request buffer area and cold writing data requested currently to be written into a flash memory together, placing the two hot writing request data on LSB and CSB on the same word line, placing the cold writing request on MSB, otherwise, directly writing the request data into the flash memory;

s4: according to the limit layer number of 3D flash memory reprogramming, a reprogramming method based on the limit layer number is designed, and after CSB and LSB pages are updated, the reading performance of thermal reading data of the corresponding MSB pages is improved; in the step S4, when data enter the request buffer area, it is first determined whether the buffer space is full, if yes, it is determined whether there is data that can be removed from the front end of the linked list, if yes, it is removed, it is further determined whether the buffer space is full, if not, it is written back to the flash memory together with other data in the buffer memory; if the buffer space is not full, performing the operations of the step S2 and the step S3; the reprogramming method based on the limiting layer number comprises the following steps:

s42: reprogramming when LSB and CSB on the same word line fail at the same time;

2. The data allocation and reprogramming optimization method for a 3DTLC flash memory according to claim 1, wherein: the step S1 includes: the method comprises the steps that data are stored through a request buffer area in a controller of an SSD, and the data are distinguished to be cold or hot through a heat filter; when the request queue enters the heat filter, judging whether the data is written for the first time, if so, recording the writing time of the data, and storing the data into a traditional programming area for traditional programming operation; if not, the data is distinguished by a heat filter, and the distinguished hot data is stored in a request buffer.

3. The data allocation and reprogramming optimization method for a 3DTLC flash memory according to claim 2, wherein: the step S1 is specifically to divide the data into read data and write data according to the access operation of the request data, calculate the two access time intervals of the request data, if the time interval is less than one second, divide the data into hot read data or hot write data, otherwise, divide the data into cold read data or cold write data.

4. The data allocation and reprogramming optimization method for a 3DTLC flash memory according to claim 1, wherein: in the step S2, a plurality of special linked lists are maintained in a request buffer of the controller to store hot data with the same update time, all data stored in the same linked list have the same heat, the data are updated at the same time point, a time line is always provided in the linked list, the time line is automatically advanced every other time period, and the data stored in the linked list are migrated to the linked list corresponding to the current update time; and setting a specified fixed time period as m, storing the hot data in the request buffer area into a linked list corresponding to the update time of the hot data, judging whether the data linked list has the time m, and if so, migrating the data in the original data linked list into the linked list corresponding to the data update time m.

5. The data allocation and reprogramming optimization method for a 3DTLC flash memory according to claim 4, wherein: the step S2 specifically comprises the following steps: the heat of the data represents the predicted time of the data to be accessed next time, and the higher the linked list level is, the higher the heat is, which represents the faster the data to be accessed; the step of establishing the heat linked list comprises the following steps: