CN114280449A - Test access architecture and test access method of digital chip - Google Patents

Abstract

The embodiment of the invention provides a test access architecture and a test access method of a digital chip, belonging to the technical field of integrated circuit testing. The architecture comprises: n test groups divided by all modules within the digital chip; each of the N test groups comprises a plurality of test modules, and the test modules in each test group are configured to be tested by adopting a distributed test access mechanism; the N test groups are configured to be tested by adopting a multi-way selection test access mechanism. The embodiment of the invention is suitable for framework division in the test process of the large-scale digital chip.

Description

Test access architecture and test access method of digital chip

Technical Field

The invention relates to the technical field of integrated circuit testing, in particular to a test access architecture and a test access method of a large-scale digital chip.

Background

With the rapid development of integrated circuit technology, more and more pure digital chips are applied to various fields. In a pure digital Chip at the present stage, a SoC (System On Chip) Chip has a large design scale and often includes a plurality of independent cores, so when testing the SoC Chip, the cores in the SoC Chip need to be tested in a modularized manner. At present, the test structure for performing modular test on SoC chips mainly includes three types: a multi-path selection structure, a daisy chain structure, and a distributed structure.

For the three test structures, especially when testing a large-scale SoC chip, the following disadvantages exist: when the multi-path selection structure is used for serially testing all modules in the SoC chip, the testing time is easy to be overlong; when all modules in the SoC chip are tested in parallel by the distributed structure, the test power consumption is easy to be overlarge, and the chip is easily burnt; the daisy chain structure is not easy to design and implement for a large-scale SoC chip, and increases the wiring overhead.

Disclosure of Invention

The embodiment of the invention aims to provide a test access architecture and a test access method of a digital chip, aiming at a large-scale digital chip, a mode of combining a distributed test access mechanism and a multi-path selection test access mechanism is adopted to test all modules in the digital chip in groups, the distributed test access mechanism is adopted among a plurality of test modules in the same test group to test, the test time is reduced, the cost of layout and wiring is reduced, in addition, the multi-path selection test access mechanism is adopted among the test groups to test, the test power consumption is reduced, and the requirement of the number of scanning ports is reduced.

In order to achieve the above object, an embodiment of the present invention provides a test access architecture for a digital chip, including: n test groups divided by all modules within the digital chip; each of the N test groups comprises a plurality of test modules, and the test modules in each test group are configured to be tested by adopting a distributed test access mechanism; the N test groups are configured to be tested by adopting a multi-way selection test access mechanism.

Further, the testing time difference value between the testing modules in each testing group is within the set time range.

Further, the difference of the total number of the triggers among the N test groups is within a set range.

Further, the total number of flip-flops in each test group ranges from 200 to 250 ten thousand.

Further, a connection relationship exists between at least two test modules in each test group.

Further, still include: and the serial data input port and the serial data output port are used for transmitting test excitation data, and the serial data input port and the serial data output port are respectively connected with each test group in the N test groups.

Further, each test group also comprises a parallel data input port and a parallel data output port which are connected with each test module.

Further, still include: and the serial data input port and the serial data output port are respectively connected with the test controller and used for controlling the test of the N test groups.

Further, the test controller is configured to test the N test groups in a multi-way selective test access mechanism according to a preset clock logic, and to close the scan clocks corresponding to the test groups that are not tested.

Further, the test controller is further configured to test the test modules in each test group according to a preset test mode in a distributed test access mechanism.

Further, the digital chip is an SoC chip.

Correspondingly, an embodiment of the present invention further provides a test access method for a digital chip, where the test access method is applied to the test access architecture of the digital chip, and the method includes: controlling the N test groups to execute the test of the multi-path selection test access mechanism; and when the test of one of the N test groups is executed, controlling a plurality of test modules in the test group to execute the test of the distributed test access mechanism.

Further, the controlling the N test groups to execute the test of the multiple-choice test access mechanism includes: and testing the N test groups by a multi-path selection test access mechanism according to preset clock logic, and closing the corresponding scanning clock of the test groups which are not tested.

Further, the controlling the plurality of test modules in the test group to execute the test of the distributed test access mechanism includes: and testing the plurality of test modules in the test group by a distributed test access mechanism according to a preset test mode.

Further, the preset test mode includes: at least one of a chip operation mode, a non-at-speed test mode, a scan shift mode for at-speed testing, or a capture mode for at-speed testing.

By the technical scheme, all modules in the digital chip are tested in a grouping mode by combining a distributed test access mechanism and a multi-path selection test access mechanism aiming at a large-scale digital chip, and a plurality of test modules in the same test group are tested by adopting the distributed test access mechanism, so that the test time is reduced, and meanwhile, the layout and wiring expenses are reduced.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:

FIG. 1 is a block diagram of a prior art architecture for a multiple-way test access mechanism employed by a test module in a digital chip;

FIG. 2 is a diagram of a prior art architecture that employs a daisy chain configuration for test modules in a digital chip;

FIG. 3 is a diagram of a prior art architecture that employs a distributed test access mechanism for test modules in a digital chip;

FIG. 4 is a diagram illustrating a test access architecture of a digital chip according to an embodiment of the present invention;

FIG. 5 is a schematic diagram illustrating an interconnection relationship between test modules and a test group division of an exemplary digital chip according to an embodiment of the present invention;

FIG. 6 is a block diagram illustrating the partitioned test groups of FIG. 5 according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating a test access method for a digital chip according to an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.

In the prior art, a multi-channel selection-based test access mechanism belongs to a time-sharing multiplexing structure, and all modules to be tested are subjected to serial test. Taking the example shown in fig. 1, the test access structure includes three modules under test. To minimize test cost, designers should use as much test bandwidth as possible for the purpose of reducing scan chain length. Another common test access mechanism is a daisy chain structure, as shown in fig. 2, in which the scan chain of each module under test is connected to the first bit of the scan chain of another module under test to form a longer scan chain. Still another common test access mechanism is a distributed test access mechanism, in which each module under test simultaneously obtains its own scan chain, so the number of scan chains at the top layer of the chip is at least the number of modules under test, as shown in fig. 3, in order to effectively utilize the scan bandwidth, scan chains with the same length are used as much as possible inside each module under test, which makes the scan chains between each module under test have the same length.

For the multi-channel selection test access mechanism, because of more modules in a large-scale SoC chip, the test time is too long when serial test is performed. For a distributed test access mechanism, parallel testing of all modules in a large-scale SoC chip can result in excessive test power consumption and chip burnout. For the daisy chain test access mechanism, when testing all modules in a large-scale SoC chip, the design and implementation are not easy, and the wiring overhead is increased. Therefore, by combining the above characteristics, the multi-path selection test access mechanism and the distributed test access mechanism are combined in the application, so that the balance between the test power consumption and the test time is realized. In addition, all modules in one SoC chip are grouped, a multi-path selection test access mechanism is adopted among test groups for testing, the number of scanning ports is reduced, meanwhile, the test power consumption is reduced, a distributed test access mechanism is adopted among the test modules in the test groups for testing, the test time is reduced, and meanwhile, the layout and wiring are reduced. Compared with a mode that a distributed test access mechanism is adopted for testing among test groups, and a multi-path selection test access mechanism is adopted for testing among test modules in the test groups, the rear-end wiring is easier, and the rear-end wire interference is not easy to occur.

Fig. 4 is a schematic diagram of a test access architecture of a digital chip according to an embodiment of the present invention. As shown in fig. 4, N test groups, including test group 1, test group 2, and test group N … …, divided by all modules within the digital chip are included; each of the N test groups comprises a plurality of test modules, and the test modules in each test group are configured to be tested by adopting a distributed test access mechanism; the N test groups are configured to be tested by adopting a multi-way selection test access mechanism.

Because the test modules in each test group are tested in parallel, the test time of each test group depends on the test module with the longest test time, and the length of the scan chain in each test module is the same, so the test time depends on the number of test vectors. The test groups are tested in series, so that the test time of the whole digital chip is the sum of the test times of all the test groups.

In addition, when dividing the digital chip, the following three factors need to be considered: test time per test module, test power consumption (e.g., number of flip-flops per module), and interconnection relationships between test modules.

The test time and the test power consumption of each test module depend on the scale of each test module and the number of triggers, and because the test modules in each test group perform parallel tests, the test time of each test group depends on the test time required by the test module with the longest test time in the test group, so that the test modules with approximately equal test time are divided into one test group when the test groups are divided. In the present application, the test time difference between the test modules in each test group may be within a set time range, for example, 200 ten thousand clock cycles. Therefore, test modules with relatively different test times are generally not divided into a test group.

In addition, the test power consumption of each test module can also be embodied in the number of triggers of each test module, so that after the test groups are divided, the difference of the total number of triggers among the N test groups can be ensured to be within a set range, for example, the set range is 50 ten thousand triggers. In addition, considering the problems of test time and test power consumption of a chip level, the number of test modules in each test group is not too large or too small, and the total number of the triggers in each test group ranges from 200 to 250 ten thousand.

In addition, considering the problems of wiring overhead and test coverage at the back end, test modules with more communication and closer position distance should be divided into a test group according to the layout of the digital chip. And a connection relationship exists between at least two test modules in each test group, and the connection relationship can be physical connection and communication connection. In addition, the test modules of different test groups at different intervals cannot be divided into one test group, for example, the test modules 1, 2 and 3 which are adjacent in sequence, when the test module 1 belongs to the test group a and the test module 2 belongs to the test group B, then the test module 3 cannot be divided into the test group a, so as to avoid the occurrence of the wire interference condition.

Therefore, the test modules with similar scales, relatively short position distances and more communication are divided into a test group so as to achieve the purposes of balancing test time and reducing wiring overhead. In a specific application, the three factors may be considered comprehensively, for example, the test modules of the core with a larger scale may be first divided with reference to the test time, the position relationship and the number of the triggers, and then the remaining test modules may be divided into a group. Taking the number of triggers of the test modules included in the SoC chip shown in table 1 and the interconnection relationship of each test module shown in fig. 5 as an example, since PEs (Processing elements) belong to the core of the digital chip and each PE includes a large number of triggers, first, 4 adjacent PEs are divided into one test group to obtain 4 test groups. Then, considering the number of flip-flops of the remaining test modules, the SPM (Sequential Processing Machine), the DMA (Direct Memory Access), the MICC (Micro Controller), the CBUF (Control Buffer, Control data set storage Buffer), and the DBG (debug Control logic) are divided into one test group, so as to obtain a test group division diagram as shown in fig. 5. The sum of the number of the flip-flops in the finally obtained 5 test groups is 2069240, 2069240, 2069240, 2069240 and 822016 in sequence. In the above example, since the test modules PE of the core are divided into 4 test groups, even though the size difference between the SPM, the DMA, the MICC, the CBUF, and the DBG is large, the test modules may be divided into one test group in consideration of the small sum of the number of flip-flops of the remaining test modules, thereby obtaining the test groups 1PEx4, 2PEx4, 3PEx4, 4PEx4, and 5(SPM, DMA, MICC, CBUF, DBG) as shown in fig. 6. And testing modules in the test groups in parallel, and testing the test groups in series.

TABLE 1

Test module name	Number of flip-flops
		DMA	38008
PE	517310
		MICC	3720
CBUF	29142
		DEBUGALL	536
SPM_FOUR	375305

In addition, as shown in fig. 4, the architecture further includes a serial data input port 11 and a serial data output port 12 for transmitting test stimulus data, wherein the serial data input port and the serial data output port are respectively connected to each of the N test groups.

Further, the architecture further includes a test controller 13, and the serial data input port and the serial data output port are respectively connected to the test controller, and are configured to control the testing of the N test groups, so as to perform unified scheduling on the test groups, and consider both the test time and the test power consumption. The test controller is further configured to test the N test groups by a multi-way selection test access mechanism according to a preset clock logic, and to close the scan clocks corresponding to the test groups that are not tested. Because a multi-path selection test access mechanism is adopted among the test groups, only one test group is in a tested state at each current moment, in order to effectively reduce the test power consumption, the N test groups can be tested in sequence according to the preset clock logic, and for the test groups which are not selected for testing, the corresponding scanning clock is closed, so that useless flip-flop overturning is prevented.

Taking the example given in table 1 above as an example, as shown in fig. 6, the test controller controls 5 test groups through the serial data input port and the serial data output port, that is, the test controller multiplexes the test input and the test output of different test groups through the multiplexing test access mechanism, and performs the selected test on the test groups through 5 groups of scan clocks scan _ clk 0-4.

In addition, each test set further includes a parallel data input port and a parallel data output port (not shown) connected to each test module. Because the test modules in the test group are tested by adopting a distributed test access mechanism, when the test controller tests one of the N test groups by using a multi-path selection test access mechanism according to the preset clock logic, all the test modules in the test group can be tested by using the distributed test access mechanism according to the preset test mode. Wherein the preset test mode comprises: at least one of a chip operation mode, a non-at-speed test mode, a scan shift mode for at-speed testing, or a capture mode for at-speed testing.

For example, when a delay Test is performed on a digital chip, a Test clock of an actual operating frequency of the digital chip needs to be generated, and at this time, an Automatic Test Equipment (ATE) needs to provide a fast Test clock. However, as the operating frequency of digital chips increases, high frequency ATE means higher test cost. Meanwhile, the pin speed on some digital chips limits the highest frequency transmitted from the outside of the digital chip to the inside of the digital chip, so that a clock control structure can be added in each test module according to the prior art.

The clock control structure in each Test module controls and switches the clocks by the control signals of corresponding Test _ mode, At _ speed, Scan _ enable and clk _ enable. Where Test _ mode is a Test mode enable signal, At _ speed is a full-speed clock signal, Scan _ enable is a Scan enable signal, and clk _ enable is a clock enable signal. (1) When the Test _ mode signal is invalid, the digital Chip is in a Chip working mode, and an OCC (On Chip clock) controller selects a fast clock generated by a phase-locked loop as a working clock of the logic circuit; (2) when the Test _ mode signal is valid and the At _ speed is invalid, the digital chip is in a non-real-speed Test mode, and the clock provided by the ATE is selected as the Test clock of the logic circuit by the clock control structure; (3) when the Test _ mode signal is effective, the At _ speed signal is effective and the Scan _ enable signal is effective, the digital chip is in a scanning shift mode of the At-speed Test, and the clock control structure selects a clock provided by the ATE as a Test clock of the logic circuit. (4) When the Test _ mode signal is valid, the At _ speed signal is valid, and the Scan _ enable signal is invalid, the digital chip is in a capture mode of the At-speed Test, and the clock control structure selects the fast clock generated by the phase-locked loop as the Test clock of the logic circuit. The clk _ enable signal is used to gate the capture clock for at speed testing, to generate a mode to shut down the clock, and requires an additional set of clock chains to control it.

By the test access architecture of the digital chip, the multi-path selection test access mechanism and the distributed test access mechanism are combined, balance of test time and test power consumption is realized, and wiring overhead is reduced. In addition, when the test modules of the digital chips are divided into test groups, the test time, the test power consumption and the interconnection relation of the test modules are comprehensively considered, and the test groups of the test modules are reasonably divided.

Correspondingly, fig. 7 is a flowchart illustrating a test access method for a digital chip according to an embodiment of the present invention. As shown in fig. 7, the method is applied to the test access architecture of the digital chip as described above, and the method includes the following steps:

step 701, controlling the N test groups to execute the test of the multi-path selection test access mechanism; and

step 702, when the test of one of the N test groups is executed, controlling the plurality of test modules in the test group to execute the test of the distributed test access mechanism.

The N test groups can be tested by a multi-path selection test access mechanism according to preset clock logic, and the corresponding scanning clock of the test group which is not tested is closed. When one test group is selected to be tested by setting N scanning clocks and presetting clock logic, in order to reduce test power consumption, the scanning clocks of other test groups which are not tested are closed. For example, when a test module in the SoC chip is divided into 5 test groups, 5 scan clocks can be set, and a corresponding test group is selected for testing according to a preset clock logic, so that unified scheduling of the test groups is realized, and both the test time and the test power consumption are taken into consideration.

In addition, when the test of one of the N test groups is executed, the plurality of test modules in the test group may be tested by a distributed test access mechanism according to a preset test mode. Wherein the preset test mode comprises: at least one of a chip operation mode, a non-at-speed test mode, a scan shift mode for at-speed testing, or a capture mode for at-speed testing. The four preset test modes can be used for testing all the test modules in the test group in parallel according to the sequence.

By the test method, a multi-path selection test access mechanism and a distributed test access mechanism are combined, and test time and test power consumption are balanced.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (15)

1. A test access architecture for a digital chip, comprising:

n test groups divided by all modules within the digital chip;

each of the N test groups comprises a plurality of test modules, and the test modules in each test group are configured to be tested by adopting a distributed test access mechanism;

the N test groups are configured to be tested by adopting a multi-way selection test access mechanism.

2. The test access architecture of the digital chip according to claim 1, wherein a test time difference between the test modules in each test group is within a set time range.

3. The test access architecture of the digital chip according to claim 1, wherein a difference of a sum of the number of flip-flops between the N test groups is within a set range.

4. The test access architecture of the digital chip according to claim 1, wherein the total number of flip-flops in each test group ranges from 200 to 250 ten thousand.

5. The test access architecture of the digital chip according to claim 1, wherein a connection relationship exists between at least two test modules in each test set.

6. The test access architecture for a digital chip according to claim 1, further comprising:

and the serial data input port and the serial data output port are used for transmitting test excitation data, and the serial data input port and the serial data output port are respectively connected with each test group in the N test groups.

7. The test access architecture of the digital chip of claim 1, further comprising a parallel data input port and a parallel data output port connected to each test module in each test group.

8. The test access architecture for a digital chip according to claim 6, further comprising:

and the serial data input port and the serial data output port are respectively connected with the test controller and used for controlling the test of the N test groups.

9. The test access architecture of the digital chip according to claim 8, wherein the test controller is further configured to test the N test groups in a multi-way selective test access scheme according to a preset clock logic, and to turn off the scan clocks corresponding to the test groups that are not tested.

10. The test access architecture of the digital chip according to claim 8, wherein the test controller is further configured to test the test modules in each test group in a distributed test access scheme according to a preset test pattern.

11. The test access architecture of the digital chip according to any of the claims 1-10, wherein the digital chip is a system on a chip, SoC, chip.

12. A test access method for a digital chip, the test access method being applied to the test access architecture of the digital chip according to any one of claims 1 to 11, the method comprising:

controlling the N test groups to execute the test of the multi-path selection test access mechanism; and

and when the test of one of the N test groups is executed, controlling a plurality of test modules in the test group to execute the test of the distributed test access mechanism.

13. The method of claim 12, wherein the controlling the N test sets to perform the testing of the multiple-choice test access mechanism comprises:

and testing the N test groups by a multi-path selection test access mechanism according to preset clock logic, and closing the corresponding scanning clock of the test groups which are not tested.

14. The method of claim 12, wherein the controlling the plurality of test modules in the test group to perform the test of the distributed test access mechanism comprises:

and testing the plurality of test modules in the test group by a distributed test access mechanism according to a preset test mode.

15. The method of claim 14, wherein the predetermined test mode comprises: at least one of a chip operation mode, a non-at-speed test mode, a scan shift mode for at-speed testing, or a capture mode for at-speed testing.

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