CN114275729A - Method for manufacturing nanopore array, nanopore array and nanopore array sensor - Google Patents

Abstract

The invention provides a method for manufacturing a nanopore array, the nanopore array and a nanopore array sensor, and the method for manufacturing the nanopore array comprises the following steps: providing a silicon wafer; forming a first mask layer and a second mask layer; forming a first patterned layer; forming a second patterned layer; carrying out first wet etching; carrying out second wet etching; forming a functional material layer; carrying out third wet etching on the second etching cavity to form a third etching cavity and expose the functional material layer positioned at the cone tip; and performing fourth etching on the functional material layer positioned at the conical tip to form a plurality of nano holes, so as to obtain a nano hole array. Therefore, the nanopore array structure with the advantages of uniform aperture, simple preparation process, high repeatability and the like can be prepared by a simple method.

Description

Method for manufacturing nanopore array, nanopore array and nanopore array sensor

Technical Field

The invention relates to the field of sensors, in particular to a method for manufacturing a nanopore array, the nanopore array and a nanopore array sensor.

Background

Nanopores are a pore structure of nanometer scale, fixed in a biological membrane or a solid material substrate, and can be divided into two types, biological nanopores and solid nanopores. Nanopore-based single molecule sequencing is called nanopore sequencing for short, belongs to one of 3 rd generation sequencing technical routes, and has the advantages of label-free, amplification-free, low cost, long reading length, high-throughput sequencing support and the like, so that the nanopore sequencing technology is considered to be a new generation sequencing technology which is most expected to realize low-cost human genome sequencing, and is generally regarded by the academic circles and the industrial circles all over the world.

At the present stage, the mainstream mechanism of nanopore sequencing is an ion blocking current detection method, and in the sequencing process, DNA molecules pass through the nanopore under the action of an electric field force, so that the flow of ions in a nanopore channel is blocked, and the ion current is reduced dramatically. According to the descending amplitude of the ion blocking current, the duration time of the blocking signal and the generation frequency of the blocking signal, researchers can evaluate physical information such as the blocking area, the blocking length and the base type of the DNA fragment to be detected. How to prepare nanopore array structures in batches at low cost has become one of the key challenges in preparing nanopores at present.

Therefore, the current methods of fabricating nanopore arrays, and nanopore array sensors still need to be improved.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.

In one aspect of the invention, the invention provides a method of fabricating a nanopore array, comprising: providing a silicon wafer having a first main surface and a second main surface which are oppositely arranged; forming a first mask layer on the first main surface of the silicon wafer, and forming a second mask layer on the second main surface of the silicon wafer; performing first dry etching on the first mask layer to form a first patterning layer, wherein the first patterning layer comprises a plurality of first sub-grooves; performing second dry etching on the second mask layer to form a second patterned layer, wherein the second patterned layer comprises a plurality of second sub-grooves, and the orthographic projection of one second sub-groove on the silicon wafer covers the orthographic projection of the plurality of first sub-grooves on the silicon wafer; performing first wet etching on the first sub-groove to form a first etching cavity, wherein the first etching cavity is of a conical structure, and the conical tip of the conical structure faces the second etching cavity; performing second wet etching on the second sub-groove to form a second etching cavity, wherein the first etching cavity is not communicated with the second etching cavity; forming a functional material layer on the surface of one side of the first etching cavity, which is far away from the second etching cavity; performing third wet etching on the second etching cavity to form a third etching cavity so as to expose the functional material layer positioned at the conical tip; and performing fourth etching on the functional material layer positioned at the conical tip to form a plurality of nano holes, so as to obtain the nano hole array. Therefore, the nanopore array structure with the advantages of uniform aperture, simple preparation process, high repeatability and the like can be prepared by a simple method.

According to an embodiment of the present invention, the forming the first patterned layer further comprises: forming a first photoresist layer on one side of the first mask layer, which is far away from the silicon wafer, performing first patterning treatment on the first photoresist layer to expose part of the surface of the first mask layer, and performing first dry etching on the first mask layer to form the first patterning layer. Thus, the preparation of the first patterned layer having the first groove may be facilitated.

According to an embodiment of the present invention, the forming the second patterned layer further comprises: and forming a second photoresist layer on one side of the second mask layer, which is far away from the silicon wafer, performing second patterning treatment on the second photoresist layer to expose part of the surface of the second mask layer, and performing second dry etching on the second mask layer to form a second patterning layer. Thus, the preparation of the second patterned layer having the second grooves may be facilitated.

According to an embodiment of the present invention, a material forming the first mask layer and the second mask layer includes at least one of silicon nitride and silicon oxide. Thus, the preparation of the patterned layer can be facilitated.

According to an embodiment of the present invention, the first dry etching and the second dry etching are ICP. Thus, the first and second grooves can be formed easily and accurately.

According to the embodiment of the invention, the etching rate of the first wet etching is v₁The etching rate of the second wet etching is v₂，v₁:v₂(60-80): (5-15), thereby facilitating control of the depths of the first etching chamber and the second etching chamber.

According to the embodiment of the invention, the etching rate of the third wet etching is v₃，v₁:v₃(60-80): (1-5). Thereby, the depth of the third etching chamber can be easily controlled.

According to the embodiment of the invention, the concentration of the etching solution of the first wet etching and the concentration of the etching solution of the second wet etching are the same as the concentration of the etching solution of the third wet etching. Therefore, the depths of the first etching cavity, the second etching cavity and the third etching cavity can be conveniently controlled.

According to the embodiment of the invention, the etching solution for the first wet etching, the etching solution for the second wet etching and the etching solution for the third wet etching comprise potassium hydroxide solutions. Thus, the control of the wet etching rate can be facilitated.

According to the embodiment of the invention, the depth of the first etching cavity is 3-5 microns in the thickness direction of the silicon wafer. Thereby, the formation of the functional material layer can be facilitated.

According to the embodiment of the invention, the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns. Thereby, the cone tip structure can be conveniently exposed.

According to an embodiment of the present invention, a material forming the functional material layer includes at least one of a metal, a metal oxide, and a non-metal oxide. Thus, the nanopore array can be made multifunctional.

According to an embodiment of the present invention, the process of forming the functional material layer includes at least one of electron beam evaporation, magnetron sputtering, and atomic layer deposition. Thereby, the formation of the functional material layer having the entire layer structure can be facilitated.

According to an embodiment of the present invention, the fourth etching includes: and etching the functional material layer positioned at the cone tip by using a focused ion beam source. Thereby, selective etching of the functional material layer may be facilitated.

According to an embodiment of the invention, the pore size of the nanopore is 1-500 nm. Therefore, a nanopore array structure with small pore size distribution can be obtained conveniently.

In another aspect of the present invention, the present invention provides a nanopore array fabricated by the method described above. Thus, the nanopore array has all the features and advantages of the method for manufacturing the nanopore array, which are not described herein again.

In yet another aspect of the present invention, the present invention provides a nanopore array sensor comprising the nanopore array as described above. Thus, the nanopore array sensor has all the features and advantages of the nanopore array structure, which are not described herein again.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 shows a schematic flow diagram of a method of fabricating a nanopore array according to one embodiment of the invention;

FIG. 2 shows a partial flow diagram of a method of fabricating a nanopore array according to yet another embodiment of the invention;

FIG. 3 shows a schematic flow chart of a subsequent process for preparing a nanopore array of the embodiment of FIG. 2;

FIG. 4 shows a partial flow diagram of a method of forming a first patterned layer according to one embodiment of the invention;

FIG. 5 is a schematic flow chart illustrating a subsequent process of the method of forming the first patterned layer of the embodiment of FIG. 4;

FIG. 6 shows a partial flow diagram of a method of forming a second patterned layer in accordance with one embodiment of the present invention;

FIG. 7 is a schematic flow chart illustrating a subsequent process of the method of forming the second patterned layer of the embodiment of FIG. 6;

fig. 8 shows a schematic structural diagram of a nanopore array according to one embodiment of the invention.

Reference numerals:

10: a first photoresist layer; 11: a first mask plate; 20: a second photoresist layer; 21: a second mask plate; 100: a silicon wafer; 210: a first mask layer; 211: a first patterned layer; 220: a second mask layer; 221: a second patterned layer; 310: a first etching chamber; 320: a second etching cavity; 330: a third etching chamber; 400: a functional material layer; 500: a nanopore.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

The present application is based on the discovery by the inventors of the following technical problems:

in the related art, the mainstream mechanism of nanopore sequencing is an ion blocking current detection method, and in the sequencing process, DNA molecules pass through a nanopore under the action of an electric field force, so that the flow of ions in a nanopore channel is blocked, and the ion current is reduced dramatically. Thus, the physical information of the DNA fragment is evaluated according to the descending amplitude of the ion blocking current, the duration of the blocking signal and the generation frequency of the blocking signal. The inventor finds that the blocking current is influenced by the surface material of the inner wall of the nanopore, and the surface state of the inner wall of the nanopore is modified, so that the amplitude of low-frequency noise can be effectively reduced, the signal-to-noise ratio of sequencing is improved, and the accuracy and the stability of a sequencing result are further improved. By modifying the functional material inside the nanopore, the electrical property of the inner wall surface can be changed, so that the influence of low-frequency noise in nanopore DNA sequencing is effectively reduced, the sequencing signal-to-noise ratio is improved, and high-precision testing is realized.

In one aspect of the invention, the invention provides a method for manufacturing a nanopore array, which comprises the steps of using a silicon wafer as a substrate, depositing a mask layer on the silicon wafer substrate through physical or chemical deposition, transferring the patterned array to the mask layer by utilizing a photoetching technology to form a patterned layer, removing the corresponding mask layer by adopting dry etching to expose silicon, forming a conical etching cavity on the upper surface of the substrate by utilizing the characteristic of anisotropic corrosion of corrosive liquid to the silicon, depositing a functional material layer on the conical etching cavity, attaching the functional material layer to the conical inner wall, so that the functional material layer and the first etching cavity have the same conical tip structure, and etching a silicon film wrapping the functional material layer at the conical tip from the back of the substrate through wet etching to expose the functional material layer at the conical tip. And finally, etching the functional material at the cone tip by adopting a focused ion beam, opening the cone tip of the functional material layer after etching, and finally synchronously forming a plurality of nano holes to obtain a large-scale nano hole array.

Specifically, referring to fig. 1, the method of fabricating a nanopore array comprises the steps of:

s10: providing a silicon wafer

According to some embodiments of the invention, a silicon wafer is provided at this step, the silicon wafer having a first major surface and a second major surface disposed opposite. The thickness of the silicon wafer is not particularly limited, and for example, the thickness of the silicon wafer may be 250-300 μm.

S20: forming a first mask layer on a first main surface of a silicon wafer, and forming a second mask layer on a second main surface of the silicon wafer

According to some embodiments of the present invention, referring to fig. 2 (a), the first mask layer 210 and the second mask layer 220 are formed at this step, and the material for forming the first mask layer and the second mask layer is not particularly limited as long as it does not undergo an etching reaction with an etching solution for wet etching a silicon wafer, for example, the material for forming the first mask layer and the second mask layer may include at least one of silicon nitride and silicon oxide.

S30: performing a first dry etching process on the first mask layer

According to some embodiments of the present invention, referring to fig. 2 (b), the first mask layer is subjected to a first dry etching at this step to form a first patterned layer 211, wherein the first patterned layer includes a plurality of first sub-grooves, i.e., grooves formed by regions of the first mask layer etched away by the first dry etching. Therefore, in the subsequent wet etching process, anisotropic wet etching can be carried out along the plurality of first sub-grooves to form a first etching cavity.

According to some embodiments of the invention, referring to fig. 4 and 5, forming the first patterned layer further comprises:

referring to (b) of fig. 4, a first photoresist layer 10 is formed on a side of the first mask layer 210 away from the silicon wafer 100.

Referring to fig. 4 (c), a first patterning process is performed on the first photoresist layer to expose a portion of the surface of the first mask layer, specifically, in this step, the first mask plate 11 may be used to shield an area that needs to be reserved on the first photoresist layer, so that an area corresponding to the first groove on the first photoresist layer is etched away through the light irradiation process, and a portion of the surface of the first mask layer 210 corresponding to the first groove is exposed.

Referring to (d) and (e) of fig. 5, the first patterned layer 211 is formed by performing a first dry etching on the first mask layer 210 at this step, wherein a first groove is formed in a region not blocked by the first mask plate during the first patterning process, that is, a position in the first patterned layer 211 where the original material of the first mask layer 210 is not present.

Referring to (f) of fig. 5, after the first patterned layer 211 is formed, the remaining first photoresist layer may be removed by a photo process, and in particular, the same conditions as the aforementioned first patterning process for the first photoresist layer may be applied, except that a mask plate is not required for the masking.

According to some embodiments of the present invention, the method of the first dry etching is not particularly limited, and for example, the first dry etching may be performed by using an inductively coupled plasma method.

S40: performing a second dry etching on the second mask layer

According to some embodiments of the present invention, referring to fig. 2 (b), the second mask layer is subjected to a second dry etching at this step to form a second patterned layer 221, wherein the second patterned layer 211 includes a plurality of second sub-grooves, i.e., grooves formed in the second mask layer at regions etched away by the second dry etching. The orthographic projection of one second sub-groove on the silicon wafer 100 covers the orthographic projections of the plurality of first sub-grooves on the silicon wafer 100, that is, one second sub-groove corresponds to the plurality of first sub-grooves. Therefore, in the subsequent wet etching process, anisotropic wet etching can be performed along the plurality of second sub-grooves to form a second etching cavity.

According to some embodiments of the invention, forming the second patterned layer further comprises:

referring to (b) of fig. 6, a second photoresist layer 20 is formed on a side of the second mask layer 220 away from the silicon wafer 100.

Referring to fig. 6 (c), a second patterning process is performed on the second photoresist layer to expose a part of the surface of the second mask layer, specifically, in this step, the second mask plate 21 may be used to shield an area that needs to be reserved on the second photoresist layer, so that an area corresponding to the second groove on the second photoresist layer is etched away through the light irradiation process, and a part of the surface of the second mask layer 210 corresponding to the second groove is exposed.

Referring to (d) and (e) of fig. 7, the second mask layer 220 is subjected to a second dry etching process to form a second patterned layer 221 through this step. The second groove is formed in a region not shielded by the second mask plate during the second patterning process, that is, a position of the second patterning layer 221 not having the original material of the first mask layer 220 is the second groove.

Referring to (f) of fig. 7, after the second patterning layer 221 is formed, the remaining first photoresist layer may be removed through a photo process, and in particular, the same conditions as those for the aforementioned second patterning process on the second photoresist layer may be applied, except that a mask plate is not required for the masking.

According to some embodiments of the present invention, the method of the second dry etching is not particularly limited, and for example, the second dry etching may be performed by using an inductively coupled plasma method.

When it needs to be specifically stated, the forming sequence of the first patterned layer and the second patterned layer is not particularly limited, for example, the first mask layer and the second mask layer may be formed on the surfaces of both sides of the silicon wafer, and then the first mask layer is subjected to the first dry etching, and then the second mask layer is subjected to the second dry etching; or forming a first mask layer on one side surface of the silicon wafer, performing first dry etching on the first mask layer, forming a second mask layer on the other side surface of the silicon wafer, and performing second dry etching on the second mask layer. The selection can be made by those skilled in the art according to the actual situation.

S50: carrying out first wet etching on the first sub-groove

According to some embodiments of the present invention, referring to (c) of fig. 2, in this step, the first etching chamber 310 is formed by performing the first wet etching on the first sub-groove, and the structure of the first etching chamber 310 is not particularly limited as long as the structure exposed by the first etching chamber has a tip when the third etching chamber is formed by the third wet etching, for example, the first etching chamber 310 may be a tapered structure, and the tapered tip of the tapered structure faces the second etching chamber 320.

According to some embodiments of the present invention, the etching liquid of the first wet etching is not particularly limited, and for example, the etching liquid of the first wet etching may be a potassium hydroxide solution. The silicon wafer has anisotropy when being subjected to wet etching by adopting a potassium hydroxide solution, so that a first etching cavity with a conical structure is formed conveniently.

According to some embodiments of the present invention, the depth of the first etching cavity is not particularly limited, and for example, the depth of the first etching cavity may be 3 to 5 micrometers in the thickness direction of the silicon wafer. When the depth of the first etching cavity is within the range, etching liquid with lower concentration can be adopted for etching treatment, so that the etching depth of the first etching cavity can be conveniently regulated and controlled.

S60: performing second wet etching on the second sub-groove

According to some embodiments of the present invention, referring to fig. 2 (c), in this step, a second wet etching is performed on the second sub-groove to form a second etching cavity 320, wherein the first etching cavity 310 is not communicated with the second etching cavity 320, so that the functional material layer with a tapered structure may be exposed by a subsequent third wet etching, and if the first etching cavity is communicated with the second etching cavity, the functional material layer with a tapered structure may not be formed.

According to some embodiments of the invention, the etch rate v of the first wet etch is lower than the etch rate v of the second wet etch₁And the etching rate v of the second wet etching₂Is not particularly limited, e.g., v₁:v₂(60-80): (5-15). Therefore, the first etching cavity with the conical structure can be conveniently and quickly formed, the second etching cavity can be quickly formed, and the second etching cavity is not communicated with the second etching cavity through speed regulation. According to some embodiments of the present invention, the concentration of the etching liquid of the second wet etching liquid is not particularly limited, for example, the concentration of the etching liquid of the second wet etching liquid may be the same as the concentration of the etching liquid of the first wet etching.

According to some embodiments of the present invention, the depth of the second etching chamber is not particularly limited, for example, when the sum of the height of the second etching chamber and the height of the first etching chamber is a and the thickness of the silicon wafer substrate is b, the difference of b-a should be not less than 5 μm. Namely, the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns. Specifically, when the thickness of the silicon wafer is 300 microns, the depth of the second etching cavity can be 290 microns; when the thickness of the silicon wafer is 250 micrometers, the depth of the second etching cavity can be 240 micrometers. When the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns, the etching rate can be conveniently regulated and controlled during the subsequent third wet etching; when the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is less than 5 microns, the third wet etching speed is high, so that the structure of the third etching cavity is not easily controlled, the functional material layer except the conical tip structure is easily exposed, and the formation of the nano-hole with a small aperture is not facilitated.

It should be noted that, the first wet etching and the second wet etching may be performed synchronously, or may be performed sequentially, for example, the first wet etching may be performed first, and then the second wet etching is performed, or the second wet etching may be performed first, and then the first wet etching is performed. The selection can be made by those skilled in the art according to the actual situation.

It should be particularly noted that the rate adjustment of the first wet etching and the second wet etching is not limited to the adjustment of the concentration of the etching solution, and the etching temperature and the etching time of the first wet etching and the second wet etching may also be adjusted to realize a structure in which the depth of the second etching cavity is larger and the depth of the first etching cavity is smaller.

S70: forming a functional material layer on the surface of one side of the first etching cavity far away from the second etching cavity

According to some embodiments of the present invention, referring to (d) of fig. 2, the functional material layer 400 is formed at a surface of the first etch chamber 310 on a side away from the second etch chamber 320 in this step. The material forming the functional material layer is not particularly limited, and for example, the material forming the functional material layer may include at least one of a metal, a metal oxide, and a non-metal oxide. Because the functional material layer can be made of various materials, the surface electrical properties of the inner wall of the formed nano-hole are different, and correspondingly, the nano-hole array also has different physical and chemical properties, so that the nano-hole array can be widely applied to multiple fields of biomolecule detection, molecule storage, calculation and the like.

According to some embodiments of the present invention, the process of forming the functional material layer is not particularly limited as long as it can form the functional material layer on a surface of the first etching chamber on a side away from the second etching chamber, and for example, the process of forming the functional material layer may include at least one of electron beam evaporation, magnetron sputtering, and atomic layer deposition.

S80: performing third wet etching on the second etching cavity

According to some embodiments of the present invention, referring to (e) in fig. 3, at this step, the third etching cavity 330 is formed by increasing the depth of the second etching cavity through the third wet etching, so that the functional material layer 400 at the taper point is exposed.

According to some embodiments of the present invention, the concentration of the etching liquid of the third wet etching liquid is not particularly limited, for example, the concentration of the etching liquid of the third wet etching liquid may be the same as the concentration of the etching liquid of the second wet etching.

According to some embodiments of the invention, the etch rate v of the first wet etch is lower than the etch rate v of the second wet etch₁And the etching rate v of the third wet etching₃Is not particularly limited, e.g., v₁:v₃(60-80): (1-5). Therefore, the third etching cavity can be formed conveniently and slowly, so that the metal layer at the conical tip is exposed slowly, and the metal layer which does not need to be etched subsequently is not exposed excessively.

It should be particularly noted that the adjustment of the rate of the third wet etching is not limited to the adjustment of the concentration of the etching solution, and the third etching chamber structure may also be formed by adjusting the etching temperature and the etching time of the third wet etching.

S90: fourth etching is carried out on the functional material layer positioned at the cone tip

According to some embodiments of the present invention, referring to (f) and (g) of fig. 3, a plurality of nano-holes 500 are formed by performing a fourth etching on the functional material layer 400 located at the cone tip at this step, and finally a nano-hole array is obtained. Therefore, the nanopore array structure with the advantages of uniform aperture, simple preparation process, high repeatability and the like can be prepared by a simple method.

According to some embodiments of the present invention, the process of the fourth etching is not particularly limited, and for example, the fourth etching may be etching the functional material layer 400 located at the cone tip by a focused ion beam source. The etching rate of the fourth etching can be adjusted by the acceleration voltage, the working current and the beam spot size of the ion beam, and due to the selectivity of the ion beam to the silicon and the functional material layer, only the functional material layer 400 is etched, and finally the functional material layer 400 at the cone tip is etched and removed to form the nanopore 500.

According to some embodiments of the present invention, the pore size of the nanopore formed by the aforementioned method is not particularly limited, and for example, the pore size of the nanopore formed may range from 1 to 500 nm. Therefore, various nanopore array sensors can be conveniently prepared by the nanopore array structure.

In summary, the present invention provides a method for fabricating a nanopore array, which has at least the following advantages:

firstly, the process of opening the nano-holes (i.e. the fourth etching) is in a liquid-free environment, so that the problems of air bubbles and solution fluctuation caused by the liquid environment in the wet etching process adopted by the conventional process, unbalanced temperature distribution in the water bath heating process and the like can be effectively avoided, and the uniformity of the preparation of the nano-hole array can be effectively improved.

Secondly, because the focused ion beam can process a large-scale area simultaneously, and the etching rate can be adjusted by accelerating voltage, working current, beam spot size and the like, the size of the nano-hole in the preparation process can be accurately controlled.

Thirdly, the semiconductor process and the MEMS technology are adopted in the whole preparation process, large-scale preparation can be realized, batch production is easy, and meanwhile, the manufacturing cost can be reduced, so that the manufacturing method can be widely applied to the fields of semiconductors, integrated circuits and nano processing.

In another aspect of the invention, the invention provides a nanopore array fabricated by the foregoing method. Thus, the nanopore array has all the features and advantages of the method for manufacturing the nanopore array, which are not described herein again.

In yet another aspect of the present invention, the present invention provides a nanopore array sensor, referring to fig. 8, the nanopore array sensor comprising the aforementioned nanopore array. Thus, the nanopore array sensor has all the features and advantages of the nanopore array structure, which are not described herein again. In summary, the nanopore array sensor has the advantages of adjustable internal electrochemical properties, high detection sensitivity, high detection speed and high reproducibility.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (11)

1. A method of fabricating a nanopore array, comprising:

providing a silicon wafer having a first main surface and a second main surface which are oppositely arranged;

forming a first mask layer on the first main surface of the silicon wafer, and forming a second mask layer on the second main surface of the silicon wafer;

performing first dry etching on the first mask layer to form a first patterning layer, wherein the first patterning layer comprises a plurality of first sub-grooves;

performing second dry etching on the second mask layer to form a second patterned layer, wherein the second patterned layer comprises a plurality of second sub-grooves, and the orthographic projection of one second sub-groove on the silicon wafer covers the orthographic projection of the plurality of first sub-grooves on the silicon wafer;

performing first wet etching on the first sub-groove to form a first etching cavity, wherein the first etching cavity is of a conical structure, and the conical tip of the conical structure faces the second etching cavity;

performing second wet etching on the second sub-groove to form a second etching cavity, wherein the first etching cavity is not communicated with the second etching cavity;

forming a functional material layer on the surface of one side of the first etching cavity, which is far away from the second etching cavity;

performing third wet etching on the second etching cavity to form a third etching cavity so as to expose the functional material layer positioned at the conical tip;

and performing fourth etching on the functional material layer positioned at the conical tip to form a plurality of nano holes, so as to obtain the nano hole array.

2. The method of claim 1, wherein the forming a first patterned layer further comprises:

forming a first photoresist layer on one side of the first mask layer far away from the silicon wafer,

performing a first patterning process on the first photoresist layer to expose a portion of a surface of the first mask layer,

and performing the first dry etching on the first mask layer to form the first patterning layer.

3. The method of claim 1, wherein the forming a second patterned layer further comprises:

forming a second photoresist layer on one side of the second mask layer far away from the silicon wafer,

performing a second patterning process on the second photoresist layer to expose a portion of the surface of the second mask layer,

and performing the second dry etching on the second mask layer to form the second patterning layer.

4. The method of any of claims 1-3, wherein the material forming the first mask layer and the second mask layer comprises at least one of silicon nitride and silicon oxide;

preferably, the first dry etching and the second dry etching are ICP.

5. The method of claim 1, wherein the first wet etch has an etch rate of v₁The etching rate of the second wet etching is v₂，v₁:v₂＝(60-80)：(5-15)；

Optionally, the etch rate of the third wet etch is v₃，v₁:v₃＝(60-80)：(1-5)；

Preferably, the concentration of the etching solution of the first wet etching, the concentration of the etching solution of the second wet etching and the concentration of the etching solution of the third wet etching are the same;

optionally, the etching solution of the first wet etching, the etching solution of the second wet etching and the etching solution of the third wet etching are potassium hydroxide solutions.

6. The method according to claim 5, wherein the depth of the first etching cavity in the thickness direction of the silicon wafer is 3-5 μm;

optionally, the difference between the sum of the depth of the second etching cavity and the depth of the first etching cavity and the thickness of the silicon wafer is not less than 5 microns.

7. The method of claim 1, wherein the material forming the functional material layer comprises at least one of a metal, a metal oxide, and a non-metal oxide;

optionally, the process of forming the functional material layer includes at least one of electron beam evaporation, magnetron sputtering, and atomic layer deposition.

8. The method of claim 6 or 7, wherein the fourth etching comprises: and etching the functional material layer positioned at the cone tip by using a focused ion beam source.

9. The method of claim 1, wherein the nanopore has a pore size of 1-500 nm.

10. A nanopore array, wherein said nanopore array is fabricated by the method of any of claims 1-9.

11. A nanopore array sensor, comprising the nanopore array structure of claim 10.

Images