CN114268401B

CN114268401B - Quantum measurement and control output synchronization method

Info

Publication number: CN114268401B
Application number: CN202111504827.2A
Authority: CN
Inventors: 胡广建; 李清石; 刘强
Original assignee: Shandong Inspur Scientific Research Institute Co Ltd
Current assignee: Shandong Inspur Scientific Research Institute Co Ltd
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2023-06-02
Anticipated expiration: 2041-12-10
Also published as: CN114268401A

Abstract

The invention provides a quantum measurement and control output synchronization method, which realizes high-speed synchronization signal output. A quantum measurement and control output synchronization method comprises the following steps: (1) trigger signal pulsing: the reference clock CLK is used as a sampling clock of the algorithm module, and the trigger signal PXI_STAR is changed into tau (t) signal output after being sampled by the algorithm module, wherein tau (t) is a pulse signal at a certain moment t; (2) According to PXIe protocol specification, 10M and 100M synchronous clocks from the backboard are arranged in each slot, the synchronous clocks to each board are provided with FPGA internal PLL phase lock, the synchronous clocks are used as a reference for PXI_STRA signal delay synchronization and used for measuring PXI_STRA delay, and corresponding delay operation is carried out on tau (t) signals; (3) And (3) determining the maximum error time according to the step (2), carrying out delay debugging on the board, and curing parameters after finishing the adjustment.

Description

Quantum measurement and control output synchronization method

Technical Field

The invention relates to a quantum measurement and control output synchronization method, and belongs to the technical field of quantum computing.

Background

In 1997, the national instruments chinese limited (National Instruments) proposed a completely new solution for testing and measuring applications: PXI (PCI eXtensions for Instrumentation) -Compact PCI optimized for testing tasks. In 1998, the PXI system consortium, where NI was cooperated with other test equipment manufacturers, brought PXI to market as an open industry standard. To date, PXI has become the standard platform for today's testing, measurement and automation applications, and its cost advantages of open architecture, flexibility and PC technology have brought an innovation to the measurement and automation industry in a roll-over.

Since the 1997 PXI Specification was developed, over 70 manufacturers have now supported and over 1500 PXI products are offered. To date, PXI has become the standard platform for today's testing, measurement and automation applications, and PXI applications have reached many areas of each industry. Through the PCI Express technology of fusing high bandwidth, the brand-new PXI Express bus (PXIE, which is a technology based on PCIE) opens up brand-new application space for the test and measurement industry.

The quantum measurement and control system must keep clock synchronization among all devices, when PXI_STAR is used as a trigger signal, errors caused by certain delay and signal quality exist, an AWG card FPGA is used for collecting the PXI_STAR to be used as an internal trigger signal, and because the FPGA is a digital logic device, the input level format of the FPGA is LVCMOS level, and when the PXI_STAR has the signal quality problem, the FPGA can misjudge. For example, when the signal rises, there is a return channel, and the FPGA can mistakenly consider the falling edge when the FPGA just collects the signal at the return channel. Meanwhile, when PXI_STAR has equal length errors or signal pulse, the delay caused by the equal length errors or the signal pulse is also asynchronous.

Disclosure of Invention

The invention aims to provide a quantum measurement and control output synchronization method for realizing high-speed synchronization signal output.

The invention aims to achieve the aim, and the aim is achieved by the following technical scheme:

a quantum measurement and control output synchronization method comprises the following steps:

(1) Pulsing the trigger signal: the reference clock CLK is used as a sampling clock of the algorithm module, and the trigger signal PXI_STAR is changed into tau (t) signal output after being sampled by the algorithm module, wherein tau (t) is a pulse signal at a certain moment t;

(2) According to PXIe protocol specification, 10M and 100M synchronous clocks from the backboard are arranged in each slot, the synchronous clocks to each board are provided with FPGA internal PLL phase lock, the synchronous clocks are used as references for PXI_STRA signal delay synchronization and used for measuring PXI_STRA delay, and corresponding delay operation is carried out on tau (t) signals;

(3) And (3) determining the maximum error time according to the step (2), carrying out delay debugging on the board, and curing parameters after finishing the adjustment.

The quantum measurement and control output synchronization method adopts a preferable scheme, and the algorithm module comprises the following implementation steps:

(1) When the input signal PXI_STAR is 0 or 1 level, τ (t) is 0 at time t0, t1 and t 2;

(2) When the input signal PXI_STAR is changed at the rising edge, the pulse signal is output only when the rising moment is checked, and the FPGA judging strategy is as follows:

at the time t0-t2, the input signal is unchanged, and tau (t) outputs are 0;

at time t0-t2, when the input signal changes to 0,1, τ (t 2) =1 only;

at times t0-t2, when the input signal changes to 0,1, τ (t 1) =1 only.

In the preferred scheme of the quantum measurement and control output synchronization method, if the tau 3 (T) is advanced by delta T, the tau 3 (T) and tau 2 (T) synchronous output is corrected, and the correction is as follows: τ3 (Δt1- Δt) =1, Δt= Δt1+ +Δt3- Δt2, wherein: τ3 (t) and τ2 (t) are output signals after pulse processing, Δt1 is an equal length error between the two trigger signals, Δt2 and Δt3 are errors between the two trigger signals and the output signals after pulse processing, respectively, and τ (t) is an output signal.

The invention has the advantages that:

the trigger signal is pulsed through a certain algorithm, the interference of the pulsed signal is greatly reduced, and the problem caused by SI signal quality is shielded; the algorithm module adopts a delay compensation algorithm to solve the delay problem.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention.

FIG. 1 is a block diagram of the invention trigger signal pulsing.

Fig. 2 is a waveform diagram of the input signal pxi_star of the present invention when it is 0 or 1.

FIG. 3 is a waveform diagram of the input signal of the present invention when it is changed to 0, 1.

Fig. 4 is a waveform diagram of the input signal of the present invention when it is changed to 0, 1.

Fig. 5 is a waveform diagram of τ (t 1) =1 when the input signal is changed to 0, 1.

FIG. 6 is a schematic diagram of the PXI_STAR and its pulse processed output signal waveforms according to the present invention.

Fig. 7 is a block diagram of a lead variation according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

(1) Pulsing the trigger signal: referring to fig. 1, a reference clock CLK is used as a sampling clock of an algorithm module, and a trigger signal pxi_star is sampled by the algorithm module and then becomes a signal τ (t) to be output, where τ (t) is a pulse signal at a certain time t, for example, the pxi_star signal is a rectangular wave, and the algorithm module outputs a pulse signal τ (t) at each rising edge; because the change time of the PXI_STAR edge is far smaller than the period of the whole rectangular wave, the interference problem caused by the signal quality problem is greatly reduced by edge pulsing in the step;

The algorithm module of the invention comprises the following implementation steps:

(1) Referring to FIG. 2, when the input signal PXI_STAR is 0 or 1 level, τ (t) is 0 at times t0, t1, t 2;

(2) Referring to fig. 3 and 4, when the input signal pxi_star is a rising edge change, the pulse signal is output only when the rising time is checked, and the FPGA determines that the strategy is:

at the time t0-t2, the input signal is unchanged, and tau (t) outputs are 0;

at time t0-t2, when the input signal changes to 0,1, τ (t 2) =1 only;

when the input signal changes to 0,1 at time t0-t2, only τ (t 1) =1, and almost all interference signals can be shielded by adopting the step as long as signal interference does not occur at the rising edge.

Referring to fig. 5, 6 and 7, assuming that τ3 (T) leads by Δt, τ3 (T) is corrected to be output in synchronization with τ2 (T), modified as follows: τ3 (Δt1- Δt) =1, Δt= Δt1+ +Δt3- Δt2, wherein: τ3 (t) and τ2 (t) are output signals after pulse processing, Δt1 is an equal length error between the two trigger signals, Δt2 and Δt3 are errors between the two trigger signals and the output signals after pulse processing, respectively, and τ (t) is an output signal.

Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The quantum measurement and control output synchronization method is characterized by comprising the following steps of:

(3) According to the step (2), determining the maximum error time, performing delay debugging on the board, and curing parameters after finishing the adjustment;

the algorithm module comprises the following implementation steps:

at the time t0-t2, the input signal is unchanged, and tau (t) outputs are 0;

at time t0-t2, when the input signal changes to 0,1, τ (t 2) =1 only;

at times t0-t2, when the input signal changes to 0,1, τ (t 1) =1 only.

2. The quantum measurement and control output synchronization method according to claim 1, wherein: let τ3 (T) advance by Δt, correct τ3 (T) and τ2 (T) synchronous output, modify as follows: τ3 (Δt1- Δt) =1, Δt= Δt1+ +Δt3- Δt2, wherein: τ3 (t) and τ2 (t) are output signals after pulse processing, Δt1 is an equal length error between the two trigger signals, Δt2 and Δt3 are errors between the two trigger signals and the output signals after pulse processing, respectively, and τ (t) is an output signal.