CN114267736A

CN114267736A - Stacked full-gate nanosheet device and manufacturing method thereof

Info

Publication number: CN114267736A
Application number: CN202110616334.1A
Authority: CN
Inventors: 肖德元
Original assignee: Qingdao Shengrui Photoelectric Technology Co ltd
Current assignee: Qingdao Shengrui Photoelectric Technology Co ltd
Priority date: 2021-06-02
Filing date: 2021-06-02
Publication date: 2022-04-01

Abstract

The invention provides a stacked all-gate nanosheet device and a manufacturing method thereof. According to the method, a channel region and a drift region are formed by stacked nano sheets, a source region is formed at one end of the channel region of the nano sheet, and a drain region is formed at one end of the drift region. The channel region, the drift region, the source region and the drain region have the same doping polarity, and the doping concentration of the source region and the drain region is greater than that of the channel region and the drift region. The junction-free fully-surrounded gate device formed in the above way has higher breakdown voltage, so that the device has better electrical performance and reliability, and is more suitable for high-voltage application environments.

Description

Stacked full-gate nanosheet device and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor devices, in particular to a stacked all-gate nanosheet device and a manufacturing method thereof.

Background

As the semiconductor industry moves into nanotechnology process nodes in pursuit of higher device densities, higher performance and lower costs, challenges in both manufacturing and design issues have led to the development of three-dimensional designs, such as fin field effect transistors (finfets). A typical FinFET is formed with a thin vertical "fin" (or fin structure) extending from a substrate, for example, by etching away a portion of a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is formed over (e.g., encasing) the fin. Having gates on both sides of the fin structure allows for gate control of the channel from both sides.

In the manufacture of integrated circuits, there is an increasing need to fit more devices and circuits in each chip. The goals of miniaturization/space utilization and increased speed have all driven this desire. In order to meet the demands for increased speed and reduced size, three-dimensional methods such as finfets have been developed for semiconductor devices. The FinFET is a non-planar FET. The fin is a narrow vertical semiconductor structure forming a channel between source and drain regions, covered by a thin insulating material, and surrounded on two or three sides by an overlying gate. Finfets improve the density and gate control of the device channel. Such three-dimensional device architectures are used in many types of applications, including Static Random Access Memory (SRAM) and logic devices.

In the 2017 th VLSI technology and circuit workshop held in Kyoto in 6 th and 5 th of 2017, it is announced that IBM and its research union partner GLOBALFOUNDRIES and Samsung are chips with 5nm nodes, and a novel transistor is manufactured, and is called a 'nanoshieet' transistor. The transition from the vertical fin architecture to the horizontal silicon stack opens a fourth "gate" on the transistor, allowing electrical signals to pass through and providing optimal electrostatic control for the gate. Meanwhile, vertically stacking a plurality of horizontal nanosheets may increase the drive current.

With the development of semiconductor devices, higher voltage requirements continue to emerge for their use. MOSFET technologies such as laterally-diffused metal-oxide semiconductor (LDMOS) are intended to handle higher voltages. LDMOS devices employ many features to handle higher voltages. For example, voltage consumption is increased by forming a low doped drift region, and voltage consumption is increased by forming an isolation trench to increase a circuit path.

However, the above-mentioned means only reduces the effective voltage of the device from the consumption end, and cannot fundamentally improve the breakdown voltage of the device, and cannot effectively solve the high voltage problem faced by the device.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a stacked full-gate nanosheet device and a method of manufacturing the same. According to the method, a channel region and a drift region are formed by stacked nano sheets, a source region is formed at one end of the channel region of the nano sheet, and a drain region is formed at one end of the drift region. The channel region, the drift region, the source region and the drain region have the same doping polarity, for example, all the source region, the drift region, the source region and the drain region are doped with P-type particles, and the doping concentration of the source region and the drain region is greater than that of the channel region and the drift region. The junction-free fully-surrounded gate device formed in the above way has higher breakdown voltage, so that the device has better electrical performance and reliability, and is more suitable for high-voltage application environments.

To achieve the above and other related objects, the present invention provides a stacked full-gate nanosheet device, comprising:

a substrate;

a plurality of stacked nanosheets suspended above the substrate, the nanosheets forming a channel region and a drift region in the direction of extension of the nanosheets;

a gate structure surrounding the channel region of the nanosheet;

the source region is connected to one end of the channel region of the nano sheet, and the drain region is connected to one end of the drift region of the nano sheet;

wherein the channel region, the drift region, the source region and the drain region have the same doping polarity.

Optionally, the material of the channel region and the drift region includes P-type ion doped silicon.

Optionally, the material of the source region and the drain region includes P-type ion doped silicon germanium.

Optionally, the source region and the drain region have the same first doping concentration, and the channel region and the drift region have the same second doping concentration.

Optionally, the first doping concentration is greater than the second doping concentration.

Optionally, the cross-sectional shape of the nanosheet is racetrack-shaped.

Optionally, an insulating dielectric layer surrounds the outside of the drift region.

Optionally, the gate structure includes:

the gate dielectric layer surrounds the channel region of the nanosheet;

the grid conducting layer surrounds the grid dielectric layer;

a common gate electrode connecting together the gate conductive layers surrounding the channel region of each of the nanosheets and completely surrounding the gate conductive layers.

Optionally, an insulating buried layer is disposed above the substrate.

According to another aspect of the invention, there is provided a method for manufacturing a stacked full-gate nanosheet device, the method comprising the steps of:

providing a substrate;

forming a stacked structure in which sacrificial layers and nanosheet layers are alternately arranged on the substrate;

removing the sacrificial layer in the stacked structure to form a nano sheet suspended above the substrate, wherein the nano sheet forms a channel region and a drift region in the extending direction of the nano sheet;

forming a gate structure surrounding the channel regions of the nanoplatelets;

forming a source region at one end of the channel region of the nano sheet, and forming a drain region at one end of the drift region of the nano sheet;

Optionally, providing the substrate further comprises: and forming an insulating buried layer above the substrate.

Optionally, removing the sacrificial layer in the stacked structure, and forming the nanosheets suspended above the substrate further includes:

etching the stacked structure to form a fin structure;

and etching the sacrificial layer in the fin structure to form the suspended nano sheet, wherein along the extension direction of the fin structure, partial sacrificial layers at two ends of the fin structure are reserved to form a support structure of the nano sheet.

Optionally, after removing the sacrificial layer in the stacked structure and forming the nanosheets suspended above the substrate, the method further includes:

forming an oxide layer on the surface of the nanosheet;

removing the oxide layer by wet etching;

and annealing in mixed gas of deuterium and hydrogen to enable the cross section of the nanosheet to be in a racetrack shape.

Optionally, a source region is formed at one end of the channel region of the nanosheet, and before a drain region is formed at one end of the drift region of the nanosheet, the method further includes: and forming an insulating medium layer surrounding and covering the drift region.

Optionally, the channel region and the drift region are made of P-type ion doped silicon.

Optionally, the source region and the drain region are made of P-type ion doped silicon germanium.

Optionally, forming a source region at one end of the channel region of the nanosheet, and forming a drain region at one end of the drift region of the nanosheet further includes:

removing the sacrificial layer forming the support structure of the fin structure;

and removing the parts of the nano sheets corresponding to the support structures.

As described above, the stacked full-gate nanosheet device and the manufacturing method thereof provided by the invention have at least the following beneficial technical effects:

according to the invention, the stacked nanosheet structure is formed, and then the three-dimensional stacked all-surrounding-gate non-junction nanosheet device is formed, so that the multilayer stacking of the device can be realized, the channel length can be effectively shortened, the channel effect is reduced, the integration level of the device is improved, and the power of the device is greatly improved.

According to the invention, the P-type channel, the P-type drift region, the P-type source region and the P-type drain region are formed, and the germanium silicon generating tensile stress on the channel region is adopted as the source region and the drain region, so that the carrier migration rate can be enhanced, and the driving current of the device can be improved. Meanwhile, the doping concentration of the source region and the drain region is greater than that of the channel region and the drift region, and the source region and the drain region and the drift region act together to improve the breakdown voltage of the device and the performance and reliability of the device.

Drawings

Fig. 1a to 1c show structural schematic diagrams of a stacked all-gate nanosheet device according to an embodiment of the present invention, where fig. 1a is a top view of the device, fig. 1b is a schematic diagram of lines L2-L2 in a direction perpendicular to an extending direction of the nanosheets, and fig. 1c is a schematic diagram of lines L1-L1 in the extending direction of the nanosheets.

Fig. 2 is a schematic flow chart of a manufacturing method of a stacked all-gate nanosheet device according to a second embodiment of the present invention.

Fig. 3 shows a schematic view of the structure of the substrate provided in the manufacturing method shown in fig. 2, wherein fig. 3 is a schematic view in a direction perpendicular to the extending direction of the nanosheets.

Fig. 4 is a schematic diagram illustrating the formation of a nanosheet layer and a sacrificial layer on the substrate shown in fig. 3.

Fig. 5 is a schematic diagram illustrating the formation of a fin structure in the structure shown in fig. 4.

Fig. 6a shows a schematic view of the formation of nanosheets suspended above the substrate in the structure shown in fig. 5.

Fig. 6b shows a schematic view of the structure shown in fig. 5 along the extension direction of the nanoplatelets.

Figure 7 shows a schematic view of the rounding of the nanoplatelets shown in figure 6 a.

Fig. 8a is a schematic diagram illustrating the formation of a gate dielectric layer on the surface of the structure shown in fig. 7.

Fig. 8b shows a schematic view of the structure shown in fig. 8a along the extension direction of the nanoplatelets.

Fig. 9a is a schematic diagram illustrating the formation of a gate conductive layer over the gate dielectric layer shown in fig. 8 a.

Fig. 9b shows a schematic view of the structure shown in fig. 9a along the extension direction of the nanoplatelets.

Fig. 10a shows a schematic diagram of a structure in which a fully wrapped around gate electrode is formed on the structure shown in fig. 9 a.

Fig. 10b shows a schematic view of the structure shown in fig. 10a along the extension direction of the nanoplatelets.

Fig. 11a shows a schematic diagram of forming a gate structure.

Fig. 11b shows a schematic view of the structure shown in fig. 11a along the extension direction of the nanoplatelets.

Fig. 12 shows a schematic diagram of the removal of the sacrificial layer and the corresponding nanosheet portion of fig. 11 b.

List of reference numerals

100 stacked full gate nanosheet device 1040 sacrificial layer

101 substrate 105 drain region

102 insulating buried oxide layer 106 gate structure

103 nanosheet 1061 gate dielectric layer

1030 nanosheet layer 1062 gate conductive layer

1031 channel region 1063 gate electrode material layer

1032 drift region 107 rounded corner structure

1033 insulating dielectric layer 110 fin structure

104 source region

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated.

Example one

The present embodiment provides a stacked all-gate nanosheet device, as shown in fig. 1a to 1c, the stacked all-gate nanosheet device includes a substrate 101, a plurality of stacked nanosheets 103 suspended above the substrate, a gate structure 106 surrounding a channel region 1031 of the nanosheets 103, and a source region 104 and a drain region 105 respectively formed at one end of the channel region of the nanosheets and at one end of a drift region 1032. The source region, the drain region, the channel region of the nanosheet and the drift region have the same doping polarity.

The substrate 100 may be selected according to the actual requirements of the device, and may include, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like. Preferably, in this embodiment, the substrate 100 is SOI, that is, as shown in fig. 1b and fig. 1c, an insulating buried oxide layer 102 is further formed above the substrate 101. In an alternative embodiment, the SOI substrate may be formed by Smart Cut technology.

In this embodiment, the nanosheet 103 is a P-type ion doped semiconductor layer. For example, in a preferred embodiment, the nanoplatelets 103 are P-type ion doped silicon. As shown in fig. 1b, nanosheets 103 have a racetrack-shaped cross-sectional shape. The runway-shaped section can form an oxide layer on the surface of the nano sheet through the oxidation nano sheet, then the oxide layer is removed by wet etching, and the oxide layer can be removed by diluted hydrofluoric acid etching. Then high-temperature annealing is carried out in the mixed gas atmosphere of deuterium and hydrogen, the annealing temperature is between 800 and 1200 ℃, and the annealing time is between 5min and 8 h. The surfaces of the annealed nano sheets become smooth, corners of the nano sheets become round corners, and finally the cross section of the nano sheets is in a shape of a runway or a similar waist shape. After the annealing treatment, in the subsequent gate dielectric layer deposition process, deuterium atoms in the nanosheets diffuse and passivate dangling bonds at the interface, so that the reliability of the device is improved.

As shown in fig. 1c, one end of the nanosheets 103 is surrounded by a gate structure, and the other end does not form a gate structure. The end surrounded by the gate structure forms a channel region 1031, while the end not forming the gate structure forms a drift region 1032. The channel region and the drift region are formed by the same nanosheet and have the same doping polarity and doping concentration. The surface of the drift region 1032 is covered with an insulating dielectric layer 1033 to protect the drift region from damage or damage, and the material of the insulating dielectric layer may be oxide or nitride. The gate structure formed outside the channel region 1031 includes a gate dielectric layer 1061 covering and surrounding the outer surface of the channel region; a gate conductive layer 1062 covering and surrounding the gate dielectric layer 1061; and a gate electrode 1063, which completely covers the gate conductive layer and is formed in the gap between adjacent nanosheets, connecting the gate conductive layers outside the channel regions of the stacked nanosheets together to form a shared gate electrode. The gate dielectric layer 1061 may be any of high-k materials such as silicon dioxide, aluminum oxide, silicon oxynitride, silicon oxycarbide, and the like. The gate conductive layer 1062 is made of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiA1), or titanium (Ti). The material of the shared gate electrode 1063 includes any one of aluminum (Al), tungsten (W), and copper (Cu). In a preferred embodiment, after the gate structure is formed, an isolation sidewall is formed on a side surface of the gate decoupling strand to space the gate structure from the source region.

Still referring to fig. 1b and 1c, active regions 104 are formed at the ends of channel regions 1031 of nanosheets 103 at one end, and drain regions are formed at the ends of drift regions 1032 at one end. The source region 104 and the drain region 105 have the same doping polarity as the nanosheets, e.g., semiconductor material that is also P-type doped. In this embodiment, germanium-silicon (SiGe) selective epitaxial growth is performed on the end portion of one end of the channel region 1031 and the end portion of one end of the drift region 1032 of the nanosheet 103, and P-type ion doping is performed on the SiGe to form a P-type SiGe source region and a P-type SiGe drain region. Although not shown in fig. 1c, it is understood that an insulating isolation layer is further disposed between the source region and the gate structure as a sidewall isolation between the source region and the gate structure.

In a preferred embodiment of the present embodiment, the doping concentration of the source region 104 and the drain region 105 is higher than the doping concentration of the nanosheets 103 (i.e., the channel region 1031 and the drift region 1032). The source region 104 and the drain region 105 formed by highly doped silicon germanium may generate stress to the channel, which may enhance carrier mobility.

As described above, in the stacked full-gate nanosheet device of the present embodiment, each field effect transistor includes two or more nanosheets arranged in a longitudinally stacked manner, and each nanosheet includes a channel region and a drift region. An active region is formed on one side of the channel region, a drain region is formed on one side of the drift region, the source region, the drain region and the nanosheets have the same doping polarity, and the doping concentration of the source region and the drain region is greater than that of the nanosheets. Therefore, the device of the embodiment forms a junction-free fully-surrounded gate nanosheet device with a drift region, so that the breakdown voltage of the device can be improved, and the reliability of the device can be improved.

Example two

The embodiment provides a manufacturing method of a stacked all-gate nanosheet device, as shown in fig. 2, the method includes the following steps:

step S101: providing a substrate;

the substrate of the present embodiment may be selected according to actual requirements of a device, and for example, may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like. As shown in fig. 3, in the preferred embodiment of the present embodiment, the substrate 100 is provided as an SOI substrate, and an insulating buried oxide layer 102 is further formed over the substrate 101. In an alternative embodiment, the SOI substrate may be formed by Smart Cut technology.

Step S102: forming a stacked structure in which sacrificial layers and nanosheet layers are alternately arranged on the substrate;

referring also to fig. 3, after the above-described SOI substrate 100 is formed, a sacrificial layer 1040, which may be a silicon germanium layer, may be formed by CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like, is first formed over the substrate 100. The thickness of the sacrificial layer 1040 is preferably 10-200 nm, but may be adjusted or selected according to the actual situation.

A nanosheet layer 1030, which may be any suitable layer of semiconductor material, is then formed over sacrificial layer 1040, as shown in fig. 4. In a preferred embodiment, the nanosheets are formed as a P-type ion doped silicon layer. The silicon epitaxial layer can be formed by adopting the processes of CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like, the thickness of the silicon layer is 10-100 nm, and the thickness can be adjusted or selected according to actual needs. In this embodiment, a tensile strained si layer is formed by forming a si layer on the GeSi layer, which is advantageous for enhancing the mobility of carriers. And then doping P-type ions in the silicon epitaxial layer by an ion implantation technology or an ion diffusion technology, wherein the P-type ions can be boron, boron fluoride or the like. In the preferred embodiment, the implantation concentration of the P-type ions is between 10¹⁵～10¹⁷ions/cm³. The ion implantation is followed by an anneal to activate the doped ions, for example, by annealing the doped silicon layer at 800 ℃.

The same process is used to sequentially form the stacked structure of the sacrificial layers and the nanosheets alternately arranged as shown in fig. 4. In the present embodiment, a stacked structure in which two sacrificial layers and two nanosheets layers are alternately stacked is shown, and it is understood that any number of sacrificial layers and nanosheets layers can be formed, and can be selected according to actual needs.

Step S103: removing part of the sacrificial layer in the stacked structure to form a nano sheet suspended above the substrate, wherein the nano sheet forms a channel region and a drift region in the extending direction of the nano sheet

First, as shown in fig. 5, the stacked structure is etched to form a fin structure 110. The fin structure may be formed using photolithography and etching processes. Forming a photoresist layer above the stacked structure, performing processes such as exposure and development on the photoresist layer to form a patterned photoresist layer with an etching window, then etching the stacked structure through the etching window, for example, dry etching, removing the stacked structure corresponding to the etching window, and stopping etching until the buried oxide layer 102 forms the fin structure shown in fig. 5. Referring to fig. 1a, the formed fin structure extends in the X-direction.

The sacrificial layer 1040 in the fin structure 110 is then etched away to form the stacked nanosheets 103 suspended above the substrate 100 as shown in fig. 6a and 6 b. In order to stably support the nanosheets 103, when the sacrificial layer of the fin structure 110 is etched, partial etching is performed, as shown in fig. 6b, partial sacrificial layers 1040 at two ends in the extending direction of the fin structure 110 are reserved, and the reserved partial sacrificial layers 1040 form a support structure of the nanosheets 103, so that the stability of the structure is ensured. For example, the sacrificial layer 1040 may be removed by forming an etch stop layer at both ends of the fin structure 110 to cover the ends, and forming an etch stop layer on the surface of the nanosheets 103 at the same time. In a preferred embodiment, HF/HNO is used₃/H₂The O solution laterally etches the fin structure 110 and the sacrificial layer in the fin structure is selectively etched away, resulting in the structure shown in fig. 6a and 6 b. Etching of a sacrificial layer of silicon germanium shows that the selective etch rate of the SiGe layer increases with increasing Ge fraction. From the grown samples, there was no change in the etch rate of the SiGe layer annealed at 800 ℃, and there was little diffusion of Ge into Si.

After the formation of the suspended nanosheets 103, the method further comprises a step of subjecting the nanosheets 103 to a rounding treatment. In a preferred embodiment, the nanosheets 103 are first subjected to an oxidation treatment to form an oxide layer on the surface thereof; then, wet etching is carried out to remove the oxide layer, for example, diluted hydrofluoric acid (DHF) solution is adopted for corrosion to remove the oxide layer; and then annealing the nano-sheets, wherein in a preferred embodiment, the nano-sheets are annealed at high temperature in a mixed gas of deuterium and hydrogen, the annealing temperature is between 800 and 1200 ℃, and the annealing time is between 5min and 8 h. After the above process, the surface of the nanosheet becomes smooth, and the corners thereof become smooth, forming a rounded corner structure 107, i.e., making the cross-sectional shape of the nanosheet 103 be racetrack-shaped or kidney-shaped and the like.

After the nanosheets 103 are formed, one end of the nanosheets is defined as a channel region and the other end as a drift region along the extending direction of the nanosheets (i.e., the X-direction shown in fig. 1 c).

S104: forming a gate structure surrounding the channel regions of the nanoplatelets;

this step eventually forms the gate structure shown in fig. 11a and 11 b. First, as shown in fig. 8a and 8b, a gate dielectric layer 1061 is formed on the surface of the nanosheet 103 formed suspended above the substrate, and the gate dielectric layer 1061 may be a high dielectric constant (high-k) material layer, such as any one of silicon dioxide, aluminum oxide, silicon oxynitride, silicon oxycarbide, and the like. The gate dielectric layer can be formed by CVD and ALD processes. As described above, due to the annealing treatment performed on the nanosheets 103, during the deposition of the gate dielectric layer 1061, deuterium atoms inside the Si nanosheets will diffuse and passivate dangling bonds at the interface, thereby improving the reliability of the device.

Then, as shown in fig. 9a and 9b, a gate conductive layer 1062 is formed on the surface of the gate dielectric layer 1061, and the gate conductive layer may be deposited on the surface of the gate dielectric layer 1061 by using CVD or ALD processes. The gate conductive layer 1062 may be made of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiA1), or titanium (Ti).

As shown in fig. 10a and 10b, after forming the gate conductive layer, a layer of gate electrode material 1063 is deposited on the surface of the gate conductive layer, covering the gate conductive layer and filling the voids between the nanoplates and between the nanoplates and the substrate, completely surrounding the nanoplates and connecting the gate conductive material of the stacked nanoplates together. A layer of gate electrode material 1063 may be deposited on the surface of the gate dielectric layer 1061 using PVD (physical vapor deposition), CVD, ALD, etc. The gate electrode material layer 1063 may be made of any one of aluminum (Al), tungsten (W), copper (Cu), and the like.

The gate electrode material layer 1063, the gate conductive layer 1062, and the gate dielectric layer 1061 are then patterned. As shown in fig. 11a and 11b, the gate electrode material layer 1063, the gate conductive layer 1062 and the gate dielectric layer 1061 covering the channel regions 1031 of the nanosheets 103 are remained, and a portion of the above material layers are removed, but the gate dielectric layer 1061 is remained in the drift region to protect the drift region from being damaged, so as to finally form the structure shown in fig. 11 b.

S105: and forming a source region at one end of the channel region of the nano sheet, and forming a drain region at one end of the drift region of the nano sheet.

First, as shown in fig. 12, the sacrificial layer 1040 supporting the nanosheets 103 is removed, and the nanosheet portions corresponding to the sacrificial layer 1040 are removed, so that both end portions of the nanosheets 103 are exposed. While removing the sacrificial layer and the corresponding nanosheet portion, the gate dielectric layer 1061 overlying the surface of the drift region 1032 may be removed at the same time, leaving the drift region exposed. In order to protect the drift region from damage during subsequent processing, an insulating dielectric layer 1033, which may be a deposited oxide or nitride, such as silicon oxide or silicon nitride, is formed on the surface of the drift region.

Then, referring again to fig. 1b and 1c, a sige layer is selectively epitaxially grown at the end of nanosheet 103 on the channel region 1031 side to form a source region 104, and a sige layer is epitaxially grown at the end of nanosheet 103 on the drift region 1032 side to form a drain region 105. And then, carrying out P-type ion doping on the germanium-silicon layers of the source region 104 and the drain region 105 to form a P-type doped source region 104 and a P-type doped drain region 105. In a preferred embodiment, the doping concentration of the source region and the drain region is the same, and is greater than the doping concentration of the P-type ions in the nanosheets. The source region and the drain region of the germanium-silicon material are formed by adopting selective epitaxial growth and are used as tensile strain materials, so that the migration rate of carriers in a channel region can be enhanced.

The present embodiment is described by taking the formation of P-type doped source, drain, channel and drift regions as an example, and it should be understood that the same method can be used to form N-type doped source, drain, channel and drift regions. For example, the channel region and the drift region may be a layer of silicon material doped with N-type ions, which may be phosphorus or arsenic, etc. The source and drain regions are also of N-type ion doped semiconductor material, which may be, for example, N-type ion doped SiC material, and the N-type ions may again be phosphorus or arsenic. Thus forming the N-type junctionless whole gate nanosheet device. Likewise, the doping concentration of the N-doped source and drain regions is greater than the doping concentration of the N-doped channel and drift regions.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A stacked, full-gate nanosheet device, comprising:

a substrate;

a gate structure surrounding the channel region of the nanosheet;

2. The stacked all-gate nanosheet device of claim 1, wherein the material of the channel region and the drift region comprises P-type ion doped silicon.

3. The stacked all-gate nanosheet device of claim 1, wherein the source and drain regions are comprised of P-type ion doped silicon germanium.

4. The stacked all-gate nanosheet device of claim 1, wherein the source region and the drain region have a same first doping concentration and the channel region and the drift region have a same second doping concentration.

5. The stacked full gate nanoplate device of claim 4, wherein the first doping concentration is greater than the second doping concentration.

6. The stacked all-gate nanoplate device of claim 1, wherein the cross-sectional shape of the nanoplate is racetrack shaped.

7. The stacked all-gate nanosheet device of claim 1, wherein an insulating dielectric layer surrounds the outside of the drift region.

8. The stacked all-gate nanoplatelet device of claim 1 wherein the gate structure comprises:

the gate dielectric layer surrounds the channel region of the nanosheet;

the grid conducting layer surrounds the grid dielectric layer;

9. The stacked all-gate nanosheet device of claim 1, wherein a buried insulating layer is disposed over the substrate.

10. A manufacturing method of a stacked full-gate nanosheet device is characterized by comprising the following steps:

providing a substrate;

removing part of the sacrificial layer in the stacked structure to form a nano sheet suspended above the substrate, wherein the nano sheet forms a channel region and a drift region in the extending direction of the nano sheet;

forming a gate structure surrounding the channel regions of the nanoplatelets;

forming a source region at one end of the channel region of the nano sheet, and forming a drain region at one end of the drift region of the nano sheet; wherein the channel region, the drift region, the source region and the drain region have the same doping polarity.

11. The method of manufacturing of claim 10, wherein providing a substrate further comprises: and forming an insulating buried layer above the substrate.

12. The method of manufacturing of claim 10, wherein removing the sacrificial layer in the stacked structure, forming nanoplates suspended over the substrate further comprises:

etching the stacked structure to form a fin structure;

13. The manufacturing method according to claim 10 or 12, wherein after removing the sacrificial layer in the stacked structure to form nanosheets suspended above the substrate, further comprising:

forming an oxide layer on the surface of the nanosheet;

removing the oxide layer by wet etching;

14. The manufacturing method according to claim 10, wherein a source region is formed at one end of the channel region of the nanosheet, and a drain region is formed at one end of the drift region of the nanosheet, and the method further comprises: and forming an insulating medium layer surrounding and covering the drift region.

15. The method of manufacturing of claim 10, wherein the source region and the drain region have a same first doping concentration and the channel region and the drift region have a same second doping concentration.

16. The method of manufacturing of claim 15, wherein the first doping concentration is greater than the second doping concentration.

17. The method of claim 15, wherein the channel region and the drift region are made of P-type ion doped silicon.

18. The method of claim 15, wherein the source region and the drain region are made of P-type ion doped silicon germanium.

19. The manufacturing method according to claim 12, wherein forming a source region at an end of the channel region of the nanosheet and forming a drain region at an end of the drift region of the nanosheet further comprises: