CN114267290A

CN114267290A - Self-adaptive LED ghost elimination and coupling method and circuit

Info

Publication number: CN114267290A
Application number: CN202210196137.3A
Authority: CN
Inventors: 张文文; 戴加良
Original assignee: Shenzhen Injoinic Technology Co Ltd
Current assignee: Shenzhen Injoinic Technology Co Ltd
Priority date: 2022-03-02
Filing date: 2022-03-02
Publication date: 2022-04-01
Anticipated expiration: 2042-03-02
Also published as: CN114267290B; CN116741085A

Abstract

The embodiment of the application provides a method and a circuit for adaptively eliminating LED ghosting and coupling, wherein the method comprises the following steps: the ghost eliminating circuit is used for controlling the discharging speed of the row parasitic capacitor, and the falling edge slope of the row selection signal is increased according to the discharging speed of the row parasitic capacitor, so that the row parasitic capacitor cannot drive the LEDs on the unselected rows, and the ghost phenomenon in the LEDs is eliminated; the charging speed of the column parasitic capacitor is controlled through the coupling elimination circuit, the rising edge slope of the column selection signal is reduced according to the charging speed of the column parasitic capacitor, so that the column parasitic capacitor cannot drive the LED on the unselected column, the coupling phenomenon in the LED is eliminated, and the display effect is improved obviously on the whole.

Description

Self-adaptive LED ghost elimination and coupling method and circuit

Technical Field

The application relates to the technical field of LEDs, in particular to a method and a circuit for adaptively eliminating LED ghosts and coupling.

Background

The current Light Emitting Diode (LED) display array is composed of m rows and n columns of LEDs, and the display is usually performed after the display array is scanned in a dynamic scanning manner. With the higher integration level, more and more pixel points are displayed on each row and each column, so that larger parasitic capacitors are arranged on the row lines and the column lines, and when the on and off of the LED corresponding to a specific row and column are realized through column pull-down control, the charges on the parasitic capacitors can flow through the extinguished LED, so that the LED is slightly conducted, and the ghost phenomenon of the LED is formed. Meanwhile, when the display is controlled to have high contrast brightness, the voltage ratio of the two ends of the high-brightness LED is higher, and the high-brightness LED is coupled to the dark side, so that the column voltage of the dark side is higher, and the coupling phenomenon is caused.

Disclosure of Invention

The embodiment of the application provides a method and a circuit for adaptively eliminating LED ghosts and coupling, which can quickly and effectively eliminate ghosts and coupling in LEDs and improve display effect.

In a first aspect, an embodiment of the present application provides a method for adaptively eliminating LED ghosts and coupling, which is applied to an adaptive elimination LED ghosts and coupling circuit, where the adaptive elimination LED ghosts and coupling circuit includes an LED display array and a driving chip for providing a row selection signal and a column selection signal for the LED display array, the LED display array includes m rows of n columns of LEDs, where m and n are positive integers, each row of LEDs is connected in parallel with a row parasitic capacitor and a series ghost elimination circuit, and each column of LEDs is connected in parallel with a column parasitic capacitor and a series coupling elimination circuit;

the method comprises the following steps:

controlling a first discharging speed through the ghost eliminating circuit, and increasing the slope of a falling edge of the row selection signal according to the first discharging speed so that the row parasitic capacitor cannot drive the LED on the unselected row, wherein the first discharging speed is the discharging speed of the row parasitic capacitor;

and controlling a first charging speed through the coupling elimination circuit, and reducing the rising edge slope of the column selection signal according to the first charging speed so that the column parasitic capacitor cannot drive the LED on the unselected column, wherein the first charging speed is the charging speed of the column parasitic capacitor.

In a second aspect, an embodiment of the present application provides an adaptive LED ghost elimination and coupling circuit, where the adaptive LED ghost elimination and coupling circuit includes an LED display array and a driving chip providing a row selection signal and a column selection signal for the LED display array, the LED display array includes m rows by n columns of LEDs, m and n are positive integers, each row of LEDs is connected in parallel with a row parasitic capacitor and a series ghost elimination circuit, and each column of LEDs is connected in parallel with a column parasitic capacitor and a series coupling elimination circuit;

the ghost eliminating circuit is used for controlling a first discharging speed, increasing the slope of a falling edge of the row selection signal according to the first discharging speed so that the row parasitic capacitor cannot drive the LED on the unselected row, and the first discharging speed is the discharging speed of the row parasitic capacitor;

the coupling elimination circuit is used for controlling a first charging speed, reducing the rising edge slope of the column selection signal according to the first charging speed so that the column parasitic capacitor cannot drive the LED on the unselected column, and the first charging speed is the charging speed of the column parasitic capacitor.

In a third aspect, an embodiment of the present application provides an LED display screen, which includes the adaptive elimination LED ghosting and coupling circuit described in the second aspect.

In a fourth aspect, the present embodiments provide a display device, which includes a processor, a memory, a communication interface, and the LED display screen of the third aspect, where the memory stores one or more programs, and the one or more programs are executed by the processor, and the one or more programs include instructions for executing some or all of the steps described in the method of the first aspect.

In a fifth aspect, the present invention provides a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps described in the method of the first aspect.

In a sixth aspect, embodiments of the present application provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps described in the method according to the first aspect of the embodiments of the present application. The computer program product may be a software installation package.

Therefore, the self-adaptive LED ghost elimination and coupling method provided by the application controls the discharge speed of the row parasitic capacitor through the ghost elimination circuit, increases the falling edge slope of the row selection signal according to the discharge speed of the row parasitic capacitor, so that the row parasitic capacitor cannot drive LEDs on unselected rows, and further eliminates the ghost phenomenon in the LEDs; the charging speed of the column parasitic capacitor is controlled through the coupling elimination circuit, and the rising edge slope of the column selection signal is reduced according to the charging speed of the column parasitic capacitor, so that the column parasitic capacitor cannot drive the LEDs on the unselected columns, the coupling phenomenon in the LEDs is eliminated, and the display effect is improved obviously on the whole.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic diagram of a timing and circuit diagram of an LED display array according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram illustrating a ghost phenomenon according to an embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram illustrating a column-to-column coupling phenomenon according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an adaptive elimination LED ghosting and coupling circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a ghost elimination circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a coupling cancellation circuit according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating a method for adaptively removing LED ghosting and coupling according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram illustrating an effect of controlling a slope of a falling edge of a row selection signal according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram illustrating an effect of controlling a slope of a rising edge of a column select signal according to an embodiment of the present disclosure.

Detailed Description

In order to better understand the technical solutions of the present application, the following description is given for clarity and completeness in conjunction with the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person skilled in the art without making any inventive step on the basis of the description of the embodiments of the present application belong to the protection scope of the present application.

The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, software, product, or apparatus that comprises a list of steps or elements is not limited to those listed but may include other steps or elements not listed or inherent to such process, method, product, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The embodiments of the present application will be described with reference to the drawings, in which a dot at the intersection of intersecting wires indicates that the wires are connected, and a dot-free intersection indicates that the wires are not connected.

At present, the display screen is generally implemented by adopting a scanning mode. As shown in fig. 1, the display array is composed of m rows by n columns of LEDs and a driving chip, the driving chip sends m row selection signals and n column selection signals respectively, the m row selection signals are valid cyclically, and each row selection signal corresponds to n LED control signals within the valid period.

When a plurality of row selection signals (m row selection signals) are circularly effective, if the driving signal of the row 1 is just finished, namely the switch RS1 is switched to the open state from the closed state, and the row selection signal of the row 2 is in the effective period at the moment, namely the switch RS2 is switched to the closed state from the open state, theoretically, no row selection signal exists on the row 1 at the moment, but due to the existence of the parasitic capacitor CR1 in the row 1, when the row selection signal of the row 2 is in the effective period, the parasitic capacitor CR1 discharges to all the LEDs on the row 1, and at the moment, if the column selection signal is effective, the LEDs on the column on the row 1 corresponding to which the column selection signal is effective are slightly lightened, so that a ghost phenomenon appears in display. Similarly, the problem also exists in the switching between other lines, and as shown in fig. 2, the time T2 in the figure is the time when the ghost phenomenon occurs.

Further, after a certain row selection signal is gated, the valid column selection signal will light up the LEDs on the row and valid column selection signals, but because the parasitic capacitance CC still exists between the column selection signals, the column selection signal beside the valid column selection signal will weakly conduct the originally invalid column selection signal through the parasitic capacitance CC to form a short-lived loop due to the existence of the parasitic capacitance CC. For example, as shown in FIG. 3, the Row 2 signal IS asserted, RS2 IS in a closed state, the column select signal for column 2 IS asserted, the LED2-2 IS illuminated when IS2 IS in a closed state, and the column select signal for column 1 IS de-asserted, the IS1 IS in an open state, and the LED2-1 IS in a extinguished state. However, since a parasitic capacitor CC1-2 exists between column 1 and column 2, and the column select signal of column 2 is usually a lower voltage, the end of CC1-2 close to column 2 is also at a low voltage, so the circuit will form a short discharge loop through RS 2- > LED 2-1- > CC1-2, resulting in that LED2-1 is briefly and weakly lit, and thus there is a column-to-column coupling phenomenon in the display.

In order to solve the problem, the application provides a method for adaptively eliminating LED ghosts, wherein a ghost eliminating circuit is connected in series with each row of LEDs, and the slope of the falling edge of a row selection signal is increased through the ghost eliminating circuit, so that the row parasitic capacitance cannot drive the LEDs on unselected rows, and the ghost phenomenon is eliminated; the coupling elimination circuit is connected in series on each column of LEDs, and the rising edge slope of the column selection signal is reduced through the coupling elimination circuit, so that the column parasitic capacitance cannot drive the LEDs on the unselected columns, the coupling phenomenon between the columns is eliminated, and the display effect is effectively improved on the whole.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a circuit for adaptively eliminating LED ghosts and coupling according to an embodiment of the present disclosure. As shown in fig. 4, the adaptive LED ghosting elimination and coupling circuit includes an LED display array 100, a driving chip 200, m row parasitic capacitors CR 300, n column parasitic capacitors CC 400, m ghosting elimination circuits 500, and n coupling elimination circuits 600.

The LED display array 100 includes m rows by n columns of LEDs. The driving chip 200 is used for providing a row selection signal RCTL and a column selection signal CCTL for the LED display array 100. The m ghost elimination circuits 500 are respectively connected in series to each row of LEDs, and the n coupling elimination circuits 600 are respectively connected in series to each column of LEDs. Each row of LEDs is further connected in parallel with a row parasitic capacitor CR 300, and each column of LEDs is further connected in parallel with a column parasitic capacitor CC 400.

In a specific implementation, due to the existence of the row parasitic capacitor CR 300, when the row selection signal RCTL of the ith row is in the valid period, the row parasitic capacitor CR 300 connected in parallel to the (i-1) th row discharges to all the LEDs on the (i-1) th row, so that the LEDs on the columns of the (i-1) th row in which the column selection signal CCTL is in the valid period are weakly turned on, and a ghost phenomenon exists in the display. In order to solve the problem, the ghost eliminating circuit 500 is connected in series to each line of LEDs, and the ghost eliminating circuit 500 can effectively control the discharging speed of the line parasitic capacitor CR 300, that is, the slope of the falling edge of the line selection signal is adjusted according to the discharging speed of the line selection signal CR 300, so that the electric quantity of the line parasitic capacitor CR 300 of the i-1 th line is reduced to be incapable of driving the LEDs of the i-1 th line before the valid period of the line selection signal RCTL of the i-th line, and i is a positive integer less than or equal to M.

When the row selection signal RCTL of the ith row is in the valid period, the column selection signal CTLL of the jth column in the valid period lights the LED of the ith row and the jth column. At this time, the j-1 th column will form a short-term loop through the weak conduction of the column parasitic capacitor CC 400 when the column selection signal CTLL is in the inactive period due to the existence of the column parasitic capacitor CC 400, so that the LED on the j-1 th column in the ith row is briefly and weakly lighted, and a column-to-column coupling phenomenon is formed. In order to solve the problem, the coupling cancellation circuit 600 is connected in series to each column of LEDs, and the coupling cancellation circuit 600 can control the charging speed of the column parasitic capacitor CC 400 and adaptively adjust the slope of the rising edge of the column selection signal CTLL, so that the low-voltage pulse when the column selection signal CTLL of the jth column is in the valid period does not cause the column parasitic capacitor CC 400 of the jth column to enter a fast charging state, and further, the electric quantity of the column parasitic capacitor of the jth column is already reduced to be unable to drive the LEDs of the jth column 1.

For example, please refer to fig. 5, fig. 5 is a schematic structural diagram of a ghost elimination circuit 500 according to an embodiment of the present disclosure. As shown in fig. 5, the ghost elimination circuit 500 includes a first transistor Q1, a second transistor Q2, a first resistor R1, a comparator U1, AND an AND gate AND.

A source of the first transistor Q1 is connected to a power source VLED, a drain of the first transistor Q1 is connected to a forward input terminal of the comparator U1, a drain of the second transistor Q2, one end of the row parasitic capacitor CR, AND an output terminal of the ghost elimination circuit 500, a gate of the first transistor Q1 is connected to an input terminal of the ghost elimination circuit 500 AND a first input terminal of the AND gate AND, an inverting input terminal of the comparator U1 is connected to a reference voltage VREF, an output terminal of the comparator U1 is connected to a second input terminal of the AND gate AND, an output terminal of the AND gate is connected to a gate of the second transistor Q2, a source of the second transistor Q2 is connected to one end of the first resistor R1, AND the other end of the first resistor R1 is connected to the other end of the row parasitic capacitor CR AND grounded.

The ghost elimination circuit 500 of the present application employs a fast current-pulling and clamping principle, wherein the first transistor Q1 is a P-channel MOS transistor for controlling the output voltage Vrout of the ghost elimination circuit 500. The second transistor Q2 is an N-channel MOS transistor for controlling whether to drive a new falling edge for slope adjustment.

Specifically, when the row selection signal RCTL changes from high level to low level, that is, the row selection signal RCTL is at a falling edge, the first transistor Q1 is in a conducting state, the voltage of the positive input terminal of the comparator U1 is Vrout, the negative input terminal of the comparator U1 is connected to a reference voltage VREF lower than the output voltage Vrout, and the output of the comparator U1 is at high level. However, since the row select signal RCTL is low, the AND gate AND output is low, the second transistor Q2 is in the off state, the output voltage Vrout of the ghost elimination circuit 500 is always approximately equal to the power VLED supplying power to the LED display array, AND during this period, the row parasitic capacitor CR is charged. When the row select signal RCTL goes high, the first transistor Q1 is turned off, the row parasitic capacitor CR discharges, and the output voltage Vrout of the ghost elimination circuit 500 is approximately the voltage of the row parasitic capacitor CR. When the output voltage Vrout of the ghost elimination circuit 500 is greater than or equal to the reference voltage VREF, the output of the comparator U1 is high, so the AND gate AND output is high AND drives the second transistor Q2 to be turned on. The row parasitic capacitance CR starts to discharge rapidly through the path of comparator U1- > AND gate AND- > second transistor Q2- > first resistor R1- > ground. The amount of power of the row parasitic capacitor CR continuously decreases, and when the output voltage Vrout of the ghost elimination circuit 500 is smaller than the reference voltage VREF, the comparator U1 outputs a low level, the second transistor Q2 is in a cut-off state, the discharge path of the row parasitic capacitor CR is disconnected, and the row parasitic capacitor CR does not discharge any more.

In the embodiment of the present application, in order to accurately and effectively control the discharging speed of the row parasitic capacitor CR, that is, control the slope of the falling edge of the row selection signal RCTL, the ghost elimination circuit 500 may calculate the preset value of the output voltage Vrout of the ghost elimination circuit 500, and further implement different slopes through the resistance of the first resistor R1.

For example, referring to fig. 6, fig. 6 is a schematic structural diagram of a coupling cancellation circuit 600 according to an embodiment of the present application. As shown in fig. 6, the coupling canceling circuit 600 includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, an adjustable constant current source, a current configuration circuit, and n sixth transistors Q6.

Wherein the gate of the third transistor Q3 is connected to the input terminal of the coupling cancellation circuit 600 and the gate of the fifth transistor Q5, the sources of the third transistor Q3 are connected to VCC and the sources of the n sixth transistors Q6, a drain of the third transistor Q3 is connected to a gate of the fourth transistor Q4, a drain of the fifth transistor Q5, one end of the column parasitic capacitance CC, and drains of the n sixth transistors Q6, respectively, the other end of the column parasitic capacitor CC is grounded, the source of the fourth transistor Q4 is connected to the output terminal of the coupling cancellation circuit 600, the drain of the fourth transistor Q4 is connected to the first output terminal of the adjustable constant current source, the second output terminal of the adjustable constant current source is connected to the source of the fifth transistor Q5 and grounded, the current configuration circuit is respectively connected with the control end of the adjustable constant current source and the gates of the n sixth transistors Q6.

In the application, for better eliminating the ghost phenomenon and the coupling phenomenon in the LED display array, a signal processing mechanism with a variable slope is adopted, the ghost phenomenon and the coupling phenomenon in the LED display array are quickly eliminated by controlling the falling edge slope of the row selection signal RCTL and the rising edge slope of the column selection signal CCTL, and the display effect is improved.

The slope adjustment of the column selection signal CCTL is different from the slope adjustment mode of the line selection signal RCTL. The slope adjustment of the column selection signal CCTL in the present application mainly depends on the weak turn-on of the n sixth transistors Q6 to adjust the rising edge slope of the final column selection signal CCTL. The third transistor Q3 is a P-channel MOS transistor, the fourth transistor is an N-channel MOS transistor, the fifth transistor Q5 is an N-channel MOS transistor, the N sixth transistors Q6 are P-channel MOS transistors, and the N sixth transistors Q6 are weak on, i.e., the turn-on voltages of the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are all much greater than the turn-on voltage of the N sixth transistors Q6.

Specifically, when the column selection signal CCTL is at a high level, the third transistor Q3 and the fourth transistor Q4 are in an off state, and the column parasitic capacitance CC discharges to drive the fifth transistor Q5 in an on state. When the column selection signal CCTL is at a low level, the third transistor Q3 and the fourth transistor Q4 are both in an on state, and a constant current source path is formed and charges the column parasitic capacitor CC, and the constant current source can output current according to the output current capability configured by the current configuration circuit. In this state, the current configuration circuit simultaneously configures different currents to control the conduction of the n sixth transistors Q6, and controls the conduction number of the sixth transistor Q6 according to the configured current, thereby adjusting the charging capability of the column parasitic capacitor CC according to the conduction number of the sixth transistor Q6. As the turn-on number of the sixth transistor Q6 increases, the voltage at the gate of the fourth transistor Q4 also increases gradually, which results in different turn-on degrees of the fourth transistor Q4, and thus different ramp slopes of the rising edge of the column selection signal CCTL.

In the embodiment of the application, the larger the current configured by the current configuration circuit is, the smaller the rising edge slope of the column selection signal CCTL is; the smaller the current of the current configuration circuit is, the larger the rising edge slope of the column selection signal CCTL is, so that the rising edge slope of the column selection signal CCTL can be adaptively adjusted according to the magnitude of the configuration current.

It can be seen that, in the adaptive circuit for eliminating the LED ghosts and coupling provided in the embodiment of the present application, in the LED series ghost elimination circuit 500 in each row and the LED series coupling elimination circuit 600 in each column, the slope of the falling edge of the row selection signal is increased by the ghost elimination circuit 500, so that the row parasitic capacitor CR cannot drive the LEDs in the unselected rows, thereby eliminating the ghost phenomenon; the rising edge slope of the column selection signal is reduced by the coupling elimination circuit 600, so that the column parasitic capacitance CC cannot drive the LEDs on the unselected columns, thereby eliminating the inter-column coupling phenomenon and further effectively improving the display effect as a whole.

Referring to fig. 7, fig. 7 is a schematic flowchart illustrating a method for adaptively removing LED ghosting and coupling according to an embodiment of the present disclosure, applied to the circuits shown in fig. 4 to 6 for adaptively removing LED ghosting and coupling. As shown in fig. 7, the method includes the following steps.

And S710, controlling a first discharging speed through the ghost eliminating circuit, and increasing the slope of the falling edge of the row selection signal according to the first discharging speed so that the row parasitic capacitor cannot drive the LEDs on the unselected rows, wherein the first discharging speed is the discharging speed of the row parasitic capacitor.

When the row selection signal RCTL is cyclically and effectively switched, the LEDs in the selected column of the row are weakly turned on because the parasitic capacitance CR of the row in the unselected row (i.e., the row selection signal is in an inactive state) discharges to the LEDs in the row. Therefore, the falling edge slope of the row selection signal RCTL is increased by controlling the discharging speed of the row selection signal RCTL, so that the row parasitic capacitance can not drive the LEDs on the unselected rows, the ghost phenomenon is eliminated, and the display effect is improved.

Optionally, the controlling, by the ghost elimination circuit, a first discharge speed, and increasing a slope of a falling edge of the row selection signal according to the first discharge speed includes: when the row selection signal is at a low level, the first transistor is in a conducting state through the row selection signal, and the row parasitic capacitor is charged through the power supply; when the row selection signal is at a high level, the first transistor is in a cut-off state through the row selection signal, and the second transistor is driven to be turned on through the discharge of the row parasitic capacitor in a first time, wherein the first time is the time when the electric quantity of the row parasitic capacitor is larger than or equal to the VREF; and determining the falling edge slope of the row selection signal corresponding to the first time according to the mapping relation between the time and the falling edge slope.

When the row selection signal RCTL is changed from high level to low level, that is, the row selection signal RCTL is at a falling edge, the first transistor Q1 is in an on state, the second transistor Q2 is in an off state, the output voltage Vrout of the ghost elimination circuit 500 is always approximately equal to the power source VLED, and the row parasitic capacitor CR is charged during the period. When the row select signal RCTL goes high, the first transistor Q1 is turned off, the output voltage Vrout of the ghost elimination circuit 500 is about the voltage of the row parasitic capacitor CR, and the row parasitic capacitor CR discharges to drive the second transistor Q2 to turn on until the voltage of the row parasitic capacitor CR is less than the reference voltage VREF.

The first time is a discharge time of the row parasitic capacitor CR, and the magnitude of the first time is mapped to a falling slope of the row selection signal RCTL, as shown in fig. 8, the ghost elimination circuit 500 can effectively increase the rising slope and the falling slope of the row selection signal RCTL. Due to the existence of the row parasitic capacitor CR, the rising edge and the falling edge of the row selection signal RCTL become slow and uncertain, so that the slope of the falling edge of the row selection signal RCTL can be effectively increased by selecting an appropriate first resistor, so that when the row selection signal RCTL is changed from a high level to a low level, the row parasitic capacitor CR can be rapidly discharged, and further, the LEDs on the unselected rows cannot be driven.

In the embodiment of the present application, the ghost eliminating circuit 500 controls the slope of the falling edge of the row selection signal RCTL, that is, increases the slope of the falling edge of the row selection signal RCTL, so as to ensure that the power of the row parasitic capacitor CR on the ith row is already reduced to be unable to drive the LEDs on the ith row when the row selection signal RCTL on the ith row is in the valid period.

S720, controlling a first charging speed through the coupling elimination circuit, and reducing the rising edge slope of the column selection signal according to the first charging speed so that the column parasitic capacitor cannot drive the LED on the unselected column, wherein the first charging speed is the charging speed of the column parasitic capacitor.

The low voltage pulse in the column selection signal CCTL of the jth column causes the adjacent column parasitic capacitance CC (the column parasitic capacitance CC on the jth-1 column) to enter a fast charging state, so that the LED that should not be lit on the column near the jth column is suddenly and weakly lit due to the fast charging of the column parasitic capacitance CC, and j is a positive integer smaller than or equal to N. Therefore, the charging rate of the column parasitic capacitance CC is reduced by adjusting the rising edge slope of the column selection signal CCTL, so that the coupling phenomenon between columns is eliminated, and the display effect is improved.

Optionally, the controlling, by the coupling cancellation circuit, a first charging speed, and reducing a rising edge slope of the column selection signal according to the first charging speed includes: when the row selection signal is in a high level, the fifth transistor is in a conducting state through discharging of the column parasitic capacitance; when the column selection signal is at a low level, the third transistor and the fourth transistor are both in a conducting state through the column selection signal, and the column parasitic capacitance is charged through the VCC within a second time, wherein the second time is determined by the number of the conducting sixth transistors in the n sixth transistors; and determining the rising edge slope of the column selection signal corresponding to the second time according to the mapping relation between the time and the rising edge slope.

And the n sixth transistors are all weak conducting transistors.

Specifically, when the column selection signal CCTL is at a low level, the third transistor Q3 and the fourth transistor Q4 are both in an on state, and a constant current source path is formed to charge the column parasitic capacitance CC. In the charging process of the column parasitic capacitor CC, the current configuration circuit may configure different currents to respectively control the turn-on of the n sixth transistors Q6, and may control the turn-on number of the sixth transistors Q6 according to the configured current, and further adjust the charging capability of the column parasitic capacitor CC according to the turn-on number of the sixth transistors Q6. As the turn-on number of the sixth transistor Q6 increases, the voltage at the gate of the fourth transistor Q4 also increases gradually, which results in different turn-on degrees of the fourth transistor Q4, and thus different ramp slopes of the rising edge of the column selection signal CCTL.

Further, the second time is a charging time of the column parasitic capacitor CC, and the second time is mapped to a rising slope of the column selection signal CCTL. As shown in fig. 9, before the slope is not adjusted (left waveform diagram), due to the existence of the column parasitic capacitance CC between the jth column and the j +1 column, when the column selection signal CCTL at the jth column is in the valid period and the column selection signal CCTL at the j +1 column is in the inactive period, a sudden low pulse at the jth column couples the jth column into a short low state through the column parasitic capacitance CC at the j +1 column, so that the LED that should not be lit between the jth column and the j +1 column in the ith row is weakly lit. After the slope is adjusted (right-side waveform), the rising edge of the column selection signal CCTL on the j +1 th column is adjusted slowly, at the moment, because the coupling of the column parasitic capacitance CC between the column j and the column j +1 is slow, the low signal on the column j +1 cannot reach the low level for lighting the j +1 th column LED on the ith row, and is changed into the voltage after the voltage drop of the LED, and therefore the problem of the coupling among the columns is effectively solved.

It can be seen that the application provides a method for adaptively eliminating the LED ghosts and coupling, in which the ghost eliminating circuit 500 is connected in series with LEDs in each row, the LED coupling eliminating circuit 600 is connected in series with LEDs in each column, the slope of the falling edge of the row selection signal RCTL is increased by the ghost eliminating circuit 500, so that the row parasitic capacitor CR cannot drive the LEDs in the unselected rows, thereby eliminating the ghost phenomenon; the rising edge slope of the column selection signal CCTL is reduced by the coupling cancellation circuit 600, so that the column parasitic capacitance CC cannot drive the LEDs on the unselected columns, thereby eliminating the inter-column coupling phenomenon, and further effectively improving the display effect as a whole.

It is to be understood that reference to "at least one" in the embodiments of the present application means one or more, and "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

The embodiment of the present application further provides an LED display screen, which includes the adaptive elimination LED ghosting and coupling circuit shown in fig. 4 to 6.

The embodiment of the present application further provides a display device, which includes a processor, a memory, a communication interface, and the LED display screen, where the memory stores one or more programs, and the one or more programs are executed by the processor, and the one or more programs include instructions for executing part or all of the steps of any of the methods described in the above method embodiments.

Embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the methods as described in the above method embodiments.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed adaptive elimination of LED ghosting and coupling circuits may be implemented in other ways. For example, the adaptive elimination LED ghosting and coupling circuit embodiments described above are merely illustrative, and for example, the components in the above circuits may also adopt other components with the same functions. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, circuits or components, and may be in an electrical or other form.

In addition, each circuit in the embodiments of the present application may be integrated in one circuit board, or each circuit may exist alone, or two or more circuits may be integrated in one circuit board.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application with specific examples, and the above description of the embodiments is only provided to help understand the present application and its core ideas; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in view of the above, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A self-adaptive LED ghost eliminating and coupling method is characterized by being applied to a self-adaptive LED ghost eliminating and coupling circuit, wherein the self-adaptive LED ghost eliminating and coupling circuit comprises an LED display array and a driving chip for providing a row selection signal and a column selection signal for the LED display array, the LED display array comprises m rows and n columns of LEDs, m and n are positive integers, each row of LEDs is connected with a row parasitic capacitor and a series ghost eliminating circuit in parallel, and each column of LEDs is connected with a column parasitic capacitor and a series coupling eliminating circuit in parallel;

the method comprises the following steps:

2. The method of claim 1, wherein the ghost elimination circuit comprises: the circuit comprises a first transistor, a second transistor, a first resistor, a comparator and an AND gate;

the source electrode of the first transistor is connected with a power supply, the drain electrode of the first transistor is respectively connected with the positive input end of the comparator, the drain electrode of the second transistor, one end of the row parasitic capacitor and the output end of the ghost eliminating circuit, the grid electrode of the first transistor is respectively connected with the input end of the ghost eliminating circuit and the first input end of the AND gate, the reverse input end of the comparator is connected with a reference voltage VREF, the output end of the comparator is connected with the second input end of the AND gate, the output end of the AND gate is connected with the grid electrode of the second transistor, the source electrode of the second transistor is connected with one end of the first resistor, and the other end of the first resistor is connected with the other end of the row parasitic capacitor and grounded.

3. The method of claim 1 or 2, wherein the coupling cancellation circuit comprises: the current configuration circuit comprises a third transistor, a fourth transistor, a fifth transistor, an adjustable constant current source, a current configuration circuit and n sixth transistors;

the grid electrode of the third transistor is respectively connected with the input end of the coupling elimination circuit and the grid electrode of the fifth transistor, the sources of the third transistors are respectively connected with VCC and the sources of the n sixth transistors, a drain of the third transistor is connected to a gate of the fourth transistor, a drain of the fifth transistor, one end of the column parasitic capacitance, and drains of the n sixth transistors, respectively, the other end of the column parasitic capacitor is grounded, the source electrode of the fourth transistor is connected with the output end of the coupling elimination circuit, the drain electrode of the fourth transistor is connected with the first output end of the adjustable constant current source, the second output end of the adjustable constant current source is connected with the source electrode of the fifth transistor and is grounded, the current configuration circuit is respectively connected with the control end of the adjustable constant current source and the grid electrodes of the n sixth transistors.

4. The method of claim 2, wherein the controlling a first discharging speed by the ghost eliminating circuit, and increasing the slope of the falling edge of the row selection signal according to the first discharging speed comprises:

when the row selection signal is at a low level, the first transistor is in a conducting state through the row selection signal, and the row parasitic capacitor is charged through the power supply;

when the row selection signal is at a high level, the first transistor is in a cut-off state through the row selection signal, and the second transistor is driven to be turned on through the discharge of the row parasitic capacitor in a first time, wherein the first time is the time when the electric quantity of the row parasitic capacitor is larger than or equal to the VREF;

and determining the falling edge slope of the row selection signal corresponding to the first time according to the mapping relation between the time and the falling edge slope.

5. The method of claim 3, wherein said controlling a first charging speed by said coupling cancellation circuit, and decreasing a rising edge slope of said column select signal according to said first charging speed comprises:

when the row selection signal is in a high level, the fifth transistor is in a conducting state through discharging of the column parasitic capacitance;

when the column selection signal is at a low level, the third transistor and the fourth transistor are both in a conducting state through the column selection signal, and the column parasitic capacitance is charged through the VCC within a second time, wherein the second time is determined by the number of the conducting sixth transistors in the n sixth transistors;

and determining the rising edge slope of the column selection signal corresponding to the second time according to the mapping relation between the time and the rising edge slope.

6. The method of claim 5, wherein the n sixth transistors are all weakly conducting transistors.

7. The circuit is characterized in that the circuit comprises an LED display array and a driving chip for providing a row selection signal and a column selection signal for the LED display array, the LED display array comprises m rows by n columns of LEDs, m and n are positive integers, each row of LEDs is connected with a row parasitic capacitor and a series ghost elimination circuit in parallel, and each column of LEDs is connected with a column parasitic capacitor and a series coupling elimination circuit in parallel;

8. The circuit of claim 7, wherein the ghost elimination circuit comprises: the circuit comprises a first transistor, a second transistor, a first resistor, a comparator and an AND gate;

9. The circuit of claim 7, wherein the coupling cancellation circuit comprises: the current configuration circuit comprises a third transistor, a fourth transistor, a fifth transistor, an adjustable constant current source, a current configuration circuit and n sixth transistors;

10. An LED display screen, characterized in that the LED display screen comprises an adaptive LED ghosting elimination and coupling circuit according to any of claims 7 to 9.

11. A display device, characterized in that the display device comprises a processor, a memory, a communication interface and a LED display screen according to claim 10, the memory storing one or more programs and the one or more programs being executed by the processor, the one or more programs comprising instructions for carrying out the steps in the method according to any one of claims 1-6.

12. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program causes a computer to perform the steps of the method according to any one of claims 1-6.