CN114265701A

CN114265701A - Resource processing method, resource processing device, computer equipment and storage medium

Info

Publication number: CN114265701A
Application number: CN202210189906.7A
Authority: CN
Inventors: 张斌; 刘虹铎; 梁猷强; 钱祎剑; 刘钊含; 何涛; 吕江波; 沈小勇
Original assignee: Suzhou Simou Intelligent Technology Co ltd; Shenzhen Smartmore Technology Co Ltd
Current assignee: Suzhou Simou Intelligent Technology Co ltd; Shenzhen Smartmore Technology Co Ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2022-04-01
Anticipated expiration: 2042-03-01
Also published as: CN114265701B

Abstract

The application relates to a resource processing method, a resource processing device, computer equipment and a storage medium. The method comprises the following steps: obtaining at least one resource structure; determining a binary tree class of each resource structure; determining the number of first resources and second resources in each resource structure according to the binary tree; determining a target resource structure of the at least one resource structure by comparing the number of first resources in each of the resource structures and comparing the number of second resources in each of the resource structures; and the number of the first resources and the second resources in the target resource structure meets a preset condition. By adopting the method, the number of registers and adders in each DSP cascade structure can be counted based on the binary-like tree, the DSP cascade structure with less consumption of resources of the trigger and the lookup table is found, and the consumption of the resources of the trigger and the lookup table is reduced.

Description

Resource processing method, resource processing device, computer equipment and storage medium

Technical Field

The present application relates to the field of digital signal processing technologies, and in particular, to a resource processing method and apparatus, a computer device, and a storage medium.

Background

With the development of the neural network technology, the number of layers of the neural network is continuously increased, the calculation amount required by the algorithm is exponentially increased, the processing speed of the system can be effectively improved by accelerating and optimizing the key layers and the operation of the neural network, and researchers provide a neural network accelerator based on the method.

Because operations such as convolution, matrix multiplication and the like in the neural network which need a large amount of operations can be decomposed into a plurality of operations for obtaining vector inner products, the neural network accelerator can improve the parallelism degree by superposing a plurality of vector inner product operation units, one DSP (Digital Signal Processing) resource on an FPGA (Field Programmable Gate Array) can complete one MAC (multiply-add) operation, and the cascade connection of a plurality of DSPs can complete the inner product operation of two vectors, therefore, when the neural network accelerator is realized by the FPGA, the cascade connection of the DSPs can be used for completing the inner product operation of the two vectors, thereby realizing the reuse of partial sum data. In order to ensure the correctness of the operation, an additional register is usually required to be introduced to buffer data when the DSPs are cascaded, so as to ensure that input data arrives at the input of the DSP at a correct clock, and an additional adder may be required to be introduced to accumulate partial sums. The introduction of the register consumes Flip Flop (FF) resources, and the introduction of the adder consumes Look-Up Table (LUT) resources. On embedded FPGAs, both FF and LUT resources are very limited, and the greater FF and LUT resource consumption, the less friendly it is to place and route. Therefore, resource optimization of the DSP is required when implementing the neural network accelerator.

The current resource optimization method generally considers how to fully utilize DSP resources to increase the computation throughput and how to utilize the DSP surrounding resources for data caching. However, neither the DSP resource nor the peripheral resource is fully utilized, which takes into account the consumption of FF and LUT resources by the system, and thus, the consumption of FF and LUT resources is too high, which is not favorable for the system implementation.

Therefore, the problem of overlarge resource consumption of a trigger and a lookup table exists when the neural network accelerator is realized on the FPGA at present.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a resource processing method, apparatus, computer device and computer readable storage medium capable of reducing the consumption of trigger and lookup table resources.

In a first aspect, the present application provides a resource processing method. The method comprises the following steps:

obtaining at least one resource structure;

determining a binary tree class of each resource structure;

determining the number of first resources and second resources in each resource structure according to the binary tree;

determining a target resource structure of the at least one resource structure by comparing the number of first resources in each of the resource structures and comparing the number of second resources in each of the resource structures; and the number of the first resources and the second resources in the target resource structure meets a preset condition.

In one embodiment, the determining a binary tree class of each resource structure includes:

acquiring the number of third resources in the resource structure;

determining the identifier of the root node of the binary tree class according to the number of the third resources;

and generating a binary tree of the resource structure according to the identifier of the root node.

In one embodiment, the generating a binary tree of the resource structure according to the identifier of the root node includes:

judging whether a left child node and a right child node exist in the root node or not according to the identifier of the root node;

if the binary tree exists, determining a left child node identifier and a right child node identifier, and generating the binary tree according to the left child node identifier and the right child node identifier;

and respectively taking the left child node and the right child node in the binary tree as root nodes, and returning to the step of judging whether the root nodes have the left child node and the right child node according to the identifiers of the root nodes.

In one embodiment, before the step of determining the binary tree class of each resource structure, the method further includes:

acquiring reference identifiers arranged according to a preset sequence and a class binary tree set corresponding to each reference identifier;

generating a binary tree of the resource structure according to the identifier of the root node, further comprising:

selecting a target identifier from the reference identifiers according to the identifier of the root node;

and obtaining the binary tree class of the resource structure according to the binary tree class set corresponding to the target identifier.

In one embodiment, the determining, according to the binary tree class, the number of the first resource and the second resource in each resource structure includes:

acquiring non-leaf nodes in the binary tree class;

determining the height of a left child node and the height of a right child node of each non-leaf node;

obtaining a first resource number corresponding to each non-leaf child node according to the difference between the height of each left child node and the height of each right child node;

and obtaining the number of the first resources in the resource structure according to the sum of the number of the first resources corresponding to each non-leaf node.

In one embodiment, the determining, according to the binary tree class, the number of the first resource and the second resource in each of the resource structures further includes:

acquiring the identifier of the leaf node in the binary tree class;

determining a target node in the leaf nodes according to the identifiers of the leaf nodes;

and obtaining the number of second resources in the resource structure according to the number of the target nodes.

acquiring a left sub-tree and a right sub-tree under the root node of the binary tree;

and obtaining the number of the first resources in the resource structure corresponding to the binary tree-like root node according to the number of the first resources in the resource structure corresponding to the left sub-tree, the number of the first resources in the resource structure corresponding to the right sub-tree, and the height difference between the left sub-tree and the right sub-tree.

In one embodiment, the determining a target resource structure in the at least one resource structure by comparing the number of first resources in each of the resource structures and comparing the number of second resources in each of the resource structures includes:

if the number of the first resources in the at least one resource structure is equal, determining the target resource structure by comparing the number of the second resources in the at least one resource structure;

and if the number of the second resources in the at least one resource structure is equal, determining the target resource structure by comparing the number of the first resources in the at least one resource structure.

In a second aspect, the present application further provides a resource processing apparatus. The device comprises:

a structure obtaining module for obtaining at least one resource structure;

a class binary tree determining module, configured to determine a class binary tree of each resource structure;

the counting module is used for determining the number of the first resources and the second resources in each resource structure according to the binary tree class;

a structure determining module, configured to determine a target resource structure in the at least one resource structure by comparing the number of first resources in each of the resource structures and comparing the number of second resources in each of the resource structures; and the number of the first resources and the second resources in the target resource structure meets a preset condition.

In a third aspect, the present application also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the following steps when executing the computer program:

obtaining at least one resource structure;

determining a binary tree class of each resource structure;

In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of:

obtaining at least one resource structure;

determining a binary tree class of each resource structure;

The resource processing method, the device, the computer equipment and the storage medium can determine the binary-like tree of each resource structure by acquiring at least one resource structure, can abstract the DSP cascade structure into the binary-like tree, is convenient for counting and visually analyzing the resources, can determine the number of the first resources and the second resources in each resource structure according to the binary-like tree, and can determine the target resource structure in at least one resource structure by comparing the number of the first resources in each resource structure and the number of the second resources in each resource structure, can count the number of registers and adders in each DSP cascade structure based on the binary-like tree, wherein the number of the registers reflects the resource consumption degree of a trigger, the number of the adders reflects the resource consumption degree of the lookup table, and can find the DSP cascade structure with less resource consumption of the trigger and the lookup table by comparing the number of the registers and the number of the adders, the use of this structure to implement a neural network accelerator can reduce the consumption of flip-flop and look-up table resources.

Drawings

FIG. 1 is a flow diagram illustrating a resource handling method according to one embodiment;

FIG. 2A is a diagram illustrating a resource structure in one embodiment;

FIG. 2B is a diagram illustrating a resource structure in another embodiment;

FIG. 3A is a diagram of a representation of a resource structure class binary tree in one embodiment;

FIG. 3B is a diagram illustrating a representation of a resource structure class binary tree in another embodiment;

FIG. 4 is a diagram illustrating the results of consuming trigger and lookup table resources by resource structures in one embodiment;

FIG. 5 is a diagram of a binary tree construction of classes in one embodiment;

FIG. 6 is a block diagram showing the structure of a resource processing apparatus according to one embodiment;

FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The resource processing method provided by the embodiment of the application can be applied to a terminal or a server. The terminal can be but not limited to various personal computers, notebook computers, smart phones, tablet computers, internet of things equipment and portable wearable equipment, and the internet of things equipment can be smart sound boxes, smart televisions, smart air conditioners, smart vehicle-mounted equipment and the like. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, and the like. The server may be implemented as a stand-alone server or as a server cluster consisting of a plurality of servers.

In one embodiment, as shown in fig. 1, a resource processing method is provided, which is described by taking the method as an example for being applied to a server, and includes the following steps:

step S110, at least one resource structure is obtained.

The resource structure may be a structure for executing resources of a neural network accelerator on an FPGA, for example, a cascade structure of DSPs constructed by using adders and registers.

In specific implementation, the DSP cascade structures to be examined may be input to the server manually, the number of DSP resources to be cascaded may also be input to the server, and the server may generate all or part of the cascade structures corresponding to the specified number of DSP resources by means of enumeration, graph theory, and the like, and store the cascade structures in the database.

Fig. 2A and 2B provide schematic diagrams of resource structures. According to fig. 2A and 2B, the number of DSP resources that need to be cascaded is 5, and the server may generate two cascade structures in fig. 2A and 2B, where the number of DSP resources in both cascade structures is 5, where the cascade structure in fig. 2A consumes 10 registers (registers) and 0 adders (adders), and the cascade structure in fig. 2B consumes 5 registers and 1 adder.

Step S120, determine a binary tree of the class of each resource structure.

The binary tree-like structure may be a representation of the resource structure in the form of a binary tree.

In the specific implementation, the number of DSP resources in a resource structure may be obtained, the number of DSP resources is used to identify a root node of the binary tree, and each child node under the root node is gradually constructed according to the root node identification, specifically, it may be determined whether the root node has a left child node and a right child node, if the root node has the left child node and the right child node, a left child node identification and a right child node identification may be generated according to the root node identification, and the left child node and the right child node of the binary tree are constructed under the root node, and then, the above process may be repeated, and each child node under the left child node and each child node under the right child node are constructed respectively with the left child node and the right child node as the root node; otherwise, if the root node does not have the left child node and the right child node, the loop can be skipped out, and the structure of the binary tree class is ended.

For example, assuming that the number of DSP resources in the DSP cascade structure is n, n can be used as the identifier of the root node of the binary tree class, since n can be represented as n = i + (n-i), it is determined whether the root node can be divided into a left child node identified as i and a right child node identified as n-i (i ≧ 0, and n-i ≧ 0, and n ≠ 0), and if the number of the sub nodes in the binary tree is larger than the preset value, constructing a left sub node and a right sub node under the root node of the binary tree, and constructing other sub nodes in the binary tree until the constructed binary tree is matched with the DSP cascade structure.

In practical application, the reference identifiers may be set, the reference identifiers are sorted in advance according to a certain order, a binary tree class set corresponding to each reference identifier is constructed, and the correspondence between the reference identifiers and the binary tree class sets is stored in the database. When the binary tree class of the designated resource structure needs to be determined, after the root node identifier is obtained, the reference identifier identical to the root node identifier is searched from the database, the binary tree class set corresponding to the reference identifier is obtained, and the binary tree class matched with the designated resource structure is selected from the binary tree class set.

It should be noted that, in the construction process of the binary tree class set, the binary tree class sets with

root nodes

1 and 2 may be generated first, then respectively selecting one from the class binary tree set with the root node of 1 and the class binary tree set with the root node of 2 as a left subtree and a right subtree to construct a class binary tree set with the root node of 3, since 4 can be expressed as 1+3 or 2+2, the binary tree construction with root node of 4 can have two options (since the left and right subtrees of the switch do not affect the resource usage in the corresponding DSP cascade structure, 1+3 and 3+1 can be regarded as the same option), namely, one of the binary tree class set with the root node of 1 and the binary tree class set with the root node of 3 can be respectively selected as the left and right subtrees, or two (which may be two identical binary tree classes) are selected from the set of binary tree classes with root node 2 as left and right subtrees. By the method, a class binary tree set with root nodes of 1, 2, 3, 4, 5, … … and n arranged from small to large can be constructed in sequence.

Fig. 3A and 3B provide schematic diagrams of a binary tree representation of a resource structure class, where the binary tree class of fig. 3A matches the resource structure of fig. 2A and the binary tree class of fig. 3B matches the resource structure of fig. 2B.

Step S130, determining the number of the first resource and the second resource in each resource structure according to the binary tree.

The first resource may be a cache resource on the FPGA, for example, a register.

The second resource may be an operation resource on the FPGA, such as an adder.

In the specific implementation, the heights of the left child node and the right child node under each non-leaf node in the binary-like tree can be obtained, the height difference between the left child node and the right child node of the non-leaf node is calculated, the number of cache resources corresponding to the non-leaf node can be obtained according to the height difference, and the number of cache resources in the DSP cascade structure corresponding to the binary-like tree can be obtained by counting the sum of the height differences of the left child node and the right child node of all the non-leaf nodes in the binary-like tree. The identification of each leaf node in the binary tree can be obtained, the number of the leaf nodes with the identification of 0 is counted, and the number of the operation resources in the DSP cascade structure corresponding to the binary tree can be obtained by subtracting 1 from the number of the leaf nodes with the identification of 0.

For example, for the binary tree of fig. 3A, the height difference between the left and right subnodes of the node identified as 1 is 0, the height difference between the left and right subnodes of the node identified as 2 is 1, the height difference between the left and right subnodes of the node identified as 3 is 2, the height difference between the left and right subnodes of the node identified as 4 is 3, the height difference between the left and right subnodes of the node identified as 5 is 4, the sum of all the height differences is counted to obtain 0+1+2+3+4=10, and the number of registers in the corresponding DSP cascade structure can be obtained to be 10; the number of leaf nodes labeled 0 is 1, 1-1=0, and it can be found that the number of adders in the DSP cascade structure is 0. For the binary tree of fig. 3B, the height differences between the left and right subnodes of two nodes marked as 1 are 0 and 0, the height differences between the left and right subnodes of two nodes marked as 2 are 1 and 1, the height difference between the left and right subnodes of nodes marked as 3 is 2, the height difference between the left and right subnodes of nodes marked as 5 is 1, the sum of all the height differences is counted to obtain 0+0+1+1+2+1=5, and the number of registers in the corresponding DSP cascade structure can be obtained to be 5; the number of leaf nodes labeled 0 is 2, 2-1=1, and it can be found that the number of adders in the DSP cascade structure is 1.

Step S140, determining a target resource structure in at least one resource structure by comparing the number of first resources in each resource structure and the number of second resources in each resource structure; the number of the first resources and the number of the second resources in the target resource structure meet preset conditions.

The number of the first resources in at least one resource structure is the same, and the number of the second resources is the minimum; when the number of the second resources in the at least one resource structure is the same, the preset condition may be that the number of the first resources is the minimum.

In a specific implementation, it may be determined whether the number of first resources in the at least one resource structure is the same, if so, the number of second resources in the at least one resource structure may be compared, and a structure with the smallest number of second resources may be used as the target resource structure, otherwise, if the number of first resources in the at least one resource structure is different, the target resource structure may not be determined. Similarly, it may also be determined whether the number of the second resources in the at least one resource structure is the same, if so, the number of the first resources in the at least one resource structure may be compared, and the structure with the smallest number of the first resources may be used as the target resource structure, otherwise, if the number of the second resources in the at least one resource structure is different, the target resource structure may not be determined.

In practical application, a two-dimensional coordinate graph can be drawn by taking the first resource number as an abscissa and the second resource number as an ordinate, the first resource number and the second resource number in each resource structure are drawn in the two-dimensional coordinate graph in a point mode, a group of points with the same abscissa are selected in the graph, the ordinates of the points are compared, and the point with the minimum ordinate can be used as a pareto optimal solution. Similarly, it is also possible to select a group of points in the graph whose ordinate is the same and compare the abscissa of these points, and the point whose abscissa is the smallest can be taken as the pareto optimal solution.

FIG. 4 provides a graph of the results of the consumption of trigger and lookup table resources by each resource structure when 9 chips are cascaded. The abscissa represents the number of adders used in different cascade structures, and the ordinate represents the number of registers used in different cascade structures. Wherein, hollow point: (

) Representing a pareto optimal resource structure. According to fig. 4, one cascade structure uses 2 adders and 10 registers, and another cascade structure uses 0 adders and 36 registers, both of which are pareto-optimal, since neither structure is better than the other. That is to say that the design corresponding to all hollow points is optimal. However, 2 are usedThe architecture of adders and 10 registers is superior to the architecture using 2 adders and 11 registers, i.e., (solid point

) The corresponding structure is not optimal because less register or adder resources are used to always find a structure corresponding to a hollow point.

The resource processing method can determine the number of the first resource and the second resource in each resource structure according to the binary-like tree, determine the target resource structure in at least one resource structure by comparing the number of the first resource in each resource structure and the number of the second resource in each resource structure, can count the number of the register and the adder in each DSP cascade structure based on the binary-like tree, the number of the register reflects the resource consumption degree of the trigger, the number of the adder reflects the resource consumption degree of the lookup table, can find the DSP cascade structure with less resource consumption of the trigger and the lookup table by comparing the number of the register and the number of the adder, and realize the neural network accelerator by using the structure, the consumption of flip-flop and look-up table resources can be reduced.

In an embodiment, the step S120 may specifically include:

step S122, acquiring the number of third resources in the resource structure;

step S124, determining the identifier of the root node of the binary tree type according to the number of the third resources;

and step S126, generating a binary tree of the resource structure according to the identifier of the root node.

The third resource may be a DSP resource on the FPGA.

In the specific implementation, the number of the DSP resources in the resource structure may be obtained, the root node of the binary-like tree is identified by the number of the DSP resources, and each child node under the root node is gradually constructed according to the root node identification, so as to obtain the binary-like tree of the resource structure. Specifically, it may be determined whether a left child node and a right child node exist in the root node, and if a left child node and a right child node exist in the root node, a left child node identifier and a right child node identifier may be generated according to the root node identifier, and a left child node and a right child node similar to a binary tree are constructed under the root node, and then the above process may be repeated, and each child node under the left child node and each child node under the right child node are constructed with the left child node and the right child node as the root node, respectively; otherwise, if the root node does not have the left child node and the right child node, the loop can be skipped out, and the structure of the binary tree class is ended. And when the binary tree class of the specified resource structure needs to be determined, the binary tree class set corresponding to the root node identifier can be searched from the database after the root node identifier is acquired, and the binary tree class matched with the specified resource structure is selected from the binary tree class set.

In this embodiment, by obtaining the number of the third resources in the resource structure, determining the identifier of the root node of the binary-like tree according to the number of the third resources, and generating the binary-like tree of the resource structure according to the identifier of the root node, the DSP cascade structure can be abstracted into the binary-like tree, which is convenient for statistics and visual analysis of the resources, and improves the resource processing efficiency.

In an embodiment, the step S126 may specifically include: judging whether a left child node and a right child node exist in the root node or not according to the identifier of the root node; if the binary tree exists, determining a left child node identifier and a right child node identifier, and generating a binary tree according to the left child node identifier and the right child node identifier; and respectively taking the left child node and the right child node in the binary tree as root nodes, and returning to the step of judging whether the root nodes have the left child node and the right child node according to the identifiers of the root nodes.

In the specific implementation, the number of DSP resources in a resource structure may be obtained, the number of DSP resources is used to identify a root node of the binary tree, and it is determined whether a left child node and a right child node exist in the root node, if a left child node and a right child node exist, a left child node identification and a right child node identification may be generated according to the root node identification, and a left child node and a right child node of the binary tree are constructed under the root node, and then the above process may be repeated, and each child node under the left child node and each child node under the right child node are constructed with the left child node and the right child node as the root node, respectively; otherwise, if the root node does not have the left child node and the right child node, the loop can be skipped out, and the structure of the binary tree class is ended.

In practical application, assuming that the number of DSP resources in the DSP cascade structure is n, n can be used as an identifier of a root node of a binary tree class, since n can be represented as n = i + (n-i), it is determined whether the root node can be divided into a left child node identified as i and a right child node identified as n-i (i ≧ 0, and n-i ≧ 0, and n ≠ 0), and if the number of the sub nodes in the binary tree is larger than the preset value, constructing a left sub node and a right sub node under the root node of the binary tree, and constructing other sub nodes in the binary tree until the constructed binary tree is matched with the DSP cascade structure.

For example, for the resource structure shown in fig. 2A, where the number of DSP resources is 5, when a binary tree class needs to be determined, 5 may be used as a root node identifier, according to fig. 2A, i =4 may be determined, it is determined whether the root node may be divided into a left child node and a right child node with identifiers of 4 and 1, respectively, if yes, a left child node and a right child node under the root node may be generated, and the left child node and the right child node are used as root nodes, respectively, and the above method is repeated to continue to construct other child nodes until a binary tree class shown in fig. 3A is obtained.

In this embodiment, whether the root node has the left child node and the right child node is determined according to the identifier of the root node, if yes, the identifier of the left child node and the identifier of the right child node are determined, the binary-like tree is generated according to the identifier of the left child node and the identifier of the right child node, the left child node and the right child node in the binary-like tree are respectively used as the root node, and the step of determining whether the root node has the left child node and the right child node is returned, so that the generation efficiency of the binary-like tree can be improved, and the resource processing efficiency is improved.

In an embodiment, before the step S120, the method further includes: acquiring the reference identifiers arranged according to the preset order and the class binary tree set corresponding to each reference identifier, where step S126 may further include: selecting a target identifier from the reference identifiers according to the identifier of the root node; and obtaining a binary tree class of the resource structure according to the binary tree class set corresponding to the target identifier.

In a specific implementation, the reference identifiers may be sorted in advance according to a certain order, a binary tree set of a class corresponding to each reference identifier is constructed, and a correspondence between the reference identifiers and the binary tree set of the class is stored in the database. When the binary tree class of the designated resource structure needs to be determined, after the root node identifier is obtained, the reference identifier identical to the root node identifier is searched from the database, the binary tree class set corresponding to the reference identifier is obtained, and the binary tree class matched with the designated resource structure is selected from the binary tree class set.

For example, for the resource structure shown in fig. 2A, where the number of DSP resources is 5, when the binary class tree needs to be determined, the root node identifier may be obtained as 5, the binary class tree set R corresponding to the reference identifier 5 is searched from the database, the binary class tree matched with fig. 2A is selected from R, and the binary class tree shown in fig. 3A may be obtained.

root nodes

In this embodiment, the reference identifiers arranged according to the preset order and the binary tree like sets corresponding to the reference identifiers are obtained, the target identifier is selected from the reference identifiers according to the identifier of the root node, and the binary tree like set of the resource structure is obtained according to the binary tree like set corresponding to the target identifier, so that the generation efficiency of the binary tree like set can be improved, and the resource processing efficiency is further improved.

In an embodiment, the step S130 may specifically include: acquiring non-leaf nodes in the class binary tree; determining the height of a left child node and the height of a right child node of each non-leaf node; obtaining the number of first resources corresponding to each non-leaf child node according to the difference between the height of each left child node and the height of each right child node; and obtaining the number of the first resources in the resource structure according to the sum of the number of the first resources corresponding to each non-leaf node.

Wherein, the non-leaf node can be a node which is not a leaf node in the binary tree class.

The height of the left child node may be the height of a binary tree using the left child node as a root node. The right child node height may be the height of a binary tree with the right child node as the root node.

In the specific implementation, the heights of the lower left child node and the lower right child node of each non-leaf node in the binary-like tree can be obtained, the height difference between the left child node and the right child node of the non-leaf node is calculated, the number of cache resources (for example, registers) corresponding to the non-leaf node can be obtained according to the height difference, and the number of the cache resources in the DSP cascade structure corresponding to the binary-like tree can be obtained by counting the sum of the height differences of the left child node and the right child node of all the non-leaf nodes in the binary-like tree.

In this embodiment, the non-leaf nodes in the binary tree class are obtained, the left child node height and the right child node height of each non-leaf node are determined, the first resource number corresponding to each non-leaf node is obtained according to the difference between each left child node height and each right child node height, the number of registers used at each level in the DSP cascade structure can be efficiently and accurately obtained, the number of first resources in the resource structure is obtained according to the sum of the first resource numbers corresponding to each non-leaf node, the total number of registers used in the DSP cascade structure can be counted, and the efficiency and accuracy of counting the total number of registers are improved.

In an embodiment, the step S130 may further include: acquiring the identifier of a leaf node in a binary tree class; determining a target node in the leaf nodes according to the identifiers of the leaf nodes; and obtaining the number of the second resources in the resource structure according to the number of the target nodes.

In a specific implementation, the identifier of each leaf node in the binary tree class may be obtained, where the identifier of the leaf node may be 0 or 1, the node identified as 0 is searched for in each leaf node, and is determined as a target node, the number of the target nodes is counted, and the number of the target nodes is subtracted by 1, so that the number of the second resources can be obtained.

For example, the identifier of each leaf node in the class binary tree may be obtained, the number of leaf nodes with an identifier of 0 is counted, and the counted number is denoted as S, and then S-1 may be used as the number of operation resources (e.g., adders) in the DSP cascade structure corresponding to the class binary tree.

In the embodiment, the identification of the leaf node in the binary tree is obtained; determining a target node in the leaf nodes according to the identifiers of the leaf nodes; the number of the second resources in the resource structure is obtained according to the number of the target nodes, the number of adders used by the DSP cascade structure can be counted, and the counting efficiency and accuracy of the adders are improved.

In an embodiment, the step S130 may further include: acquiring a left sub-tree and a right sub-tree under a root node of the binary tree; and obtaining the number of the first resources in the resource structure corresponding to the root node of the binary-like tree according to the number of the first resources in the resource structure corresponding to the left sub-tree, the number of the first resources in the resource structure corresponding to the right sub-tree and the height difference between the left sub-tree and the right sub-tree.

In a specific implementation, the server may store the number of registers in the DSP cascade structure corresponding to each sub-tree and the height of each sub-tree in the database in advance. When the number of registers in the specified DSP cascade structure needs to be determined according to the binary-like tree, a left sub-tree and a right sub-tree under a root node of the binary-like tree can be obtained, the number of the registers in the DSP cascade structure corresponding to the left sub-tree and the number of the registers in the DSP cascade structure corresponding to the right sub-tree are searched in a database, the height difference between the left sub-tree and the right sub-tree is calculated according to the heights of the left sub-tree and the right sub-tree, and the number of the registers in the DSP cascade structure corresponding to the binary-like tree can be obtained by counting the sum of the numbers of the registers in the DSP cascade structure corresponding to the left sub-tree, the numbers of the registers in the DSP cascade structure corresponding to the right sub-tree and the height difference between the left sub-tree and the right sub-tree.

In practical application, the number of registers can be obtained according to the following formula:

。

wherein,ta root node is represented as a root node,t ₁a left child node is shown, which is,t ₂the right child node is represented by a right child node,f _b(t) Representing a root node astThe binary tree of (a) corresponds to the number of registers in the DSP cascade structure,f _h(t) Representing a root node astIs the height of the binary tree.

In this embodiment, by obtaining the left sub-tree and the right sub-tree under the root node of the binary-like tree, and according to the number of the first resources in the resource structure corresponding to the left sub-tree, the number of the first resources in the resource structure corresponding to the right sub-tree, and the height difference between the left sub-tree and the right sub-tree, the number of the first resources in the resource structure corresponding to the root node of the binary-like tree is obtained, so that the efficiency and accuracy of register statistics in the DSP cascade structure can be further improved.

In an embodiment, the step S140 may specifically include: if the number of the first resources in the at least one resource structure is equal, determining a target resource structure by comparing the number of the second resources in the at least one resource structure; and if the number of the second resources in the at least one resource structure is equal, determining a target resource structure by comparing the number of the first resources in the at least one resource structure.

) Representing a pareto optimal resource structure. According to fig. 4, one cascade structure uses 2 adders and 10 registers, and another cascade structure uses 0 adders and 36 registers, both of which are provided in stagesThe linkage structures are pareto optimal because none of the structures are better than the other. That is to say that the design corresponding to all hollow points is optimal. However, the architecture using 2 adders and 10 registers is superior to the architecture using 2 adders and 11 registers, i.e., (solid point

In this embodiment, if the number of the first resources in the at least one resource structure is equal, the target resource structure is determined by comparing the number of the second resources in the at least one resource structure; if the number of the second resources in at least one resource structure is equal, the number of the first resources in at least one resource structure is compared to determine a target resource structure, the numbers of the registers and the adders in the DSP cascade structure can be compared to find the DSP cascade structure with relatively less registers or adders, the resource consumption of the structure trigger or the lookup table is relatively less, and the resource consumption of the trigger or the lookup table in the neural network accelerator can be reduced.

To facilitate a thorough understanding of the embodiments of the present application by those skilled in the art, the following description will be given with reference to a specific example.

When a neural network accelerator is implemented by an FPGA, an inner product of two vectors is usually implemented by using DSP cascade, and an additional register and an adder are introduced in the cascade process to ensure the correctness of the operation. For the vector inner product operation units formed by n cascaded DSPs, there are multiple cascading modes, and the number of registers and adders introduced by different cascading modes is different, and when the neural network accelerator includes multiple vector inner product operation units, the different cascading modes can cause great difference in FF (trigger, a programmable resource in FPGA) and LUT (look-up table, a programmable resource in FPGA) resources consumed by final design. Optimizing the resource usage of a single vector inner product arithmetic unit is crucial to optimizing the use of the final designed FF and LUT. The less the resource consumption, the more beneficial to the layout and wiring of the physical implementation stage of the FPGA, the easier the high-frequency design is realized, and the integral performance of the accelerator is improved.

In general, optimizing the use of registers and optimizing the use of adders are two conflicting objectives, and thus there is no way to find a design that optimizes the use of registers and adders, but only a few pareto-optimal designs. The pareto optimal refers to an ideal state of resource allocation. For example, given an inherent population of people and allocable resources, if at least one person is made better in a change from one allocation state to another without worsening any person's situation, this is a pareto improvement. The pareto optimal situation is a situation where no further improvement of pareto is possible, i.e. it is not possible to improve the situation of some persons without damaging anyone else.

To evaluate the use of register and adder resources and find a pareto optimal design, the cascaded structure of DSPs can be represented by a binary tree-like structure. The binary tree structure and the DSP cascade mode are in one-to-one correspondence, and the resource utilization condition corresponding to the DSP cascade mode can be obtained by evaluating the property of the binary tree structure. Therefore, the search problem of the DSP cascading mode can be converted into the construction problem of the binary tree. The class binary tree corresponding to one DSP may be considered first, and then the class binary trees corresponding to the two DSP cascade structures may be considered, because three DSPs may be considered as one DSP and then obtained by cascading 2 DSPs, the corresponding class binary tree may also be considered as two small class binary trees which are respectively obtained as left and right subtrees.

The specific resource optimization method comprises the following steps:

step 1, abstracting the DSP cascade structure into a binary tree of a kind. Fig. 2A and 2B show two different DSP cascade approaches, both consuming 5 DSPs. However, the cascade shown in fig. 2A consumes 10 registers and 0 adders, and the cascade shown in fig. 2B consumes 5 registers and 1 adder.

FIGS. 3A and 3B show binary tree-like representations of the two DSP cascading approaches of FIGS. 2A and 2B. The number n in a node represents that the results of n multiplications already in the current node are accumulated. The resource consumption of the corresponding DSP cascade structure is known from the representation of the binary tree-like. The sum of the height differences of the left and right child nodes of all non-leaf nodes in the binary-like tree represents the consumption of registers in the corresponding DSP cascade structure. The consumption of the adder in the corresponding DSP cascade structure can be obtained by subtracting 1 from the number of all leaf nodes labeled 0. For example, in the left binary tree, the height difference between the left and right child nodes of the node labeled 2 is 1, the height difference between the left and right child nodes of the node labeled 3 is 2, the height difference between the left and right child nodes of the node labeled 4 is 3, and the height difference between the left and right child nodes of the node labeled 5 is 4, so that the consumption of the register in the corresponding DSP cascade structure is 1+2+3+4=10, and the consumption of the adder is 1-1= 0; in the right binary tree, there are two leaf nodes labeled 0, so the consumption of the corresponding registers in the DSP cascade structure is 1+2+1+1=5, and the consumption of the adder is 2-1= 1.

And 2, carrying out quantitative relation between the binary-like tree and the characteristics of the left subtree and the right subtree. A large binary tree structure can be constructed by two small binary trees as left and right subtrees respectively. For example, the root node in FIG. 5 ist ₁+t ₂May be composed of root nodes ast ₁And the root node ist ₂The binary tree of the class is constructed as a left subtree and a right subtree respectively. If it is usedf _o(t) Representing a root node astThe number of leaf nodes labeled 0 in the binary tree of the class (c),f _a(t) Representing a root node astThe class of binary tree of (a) corresponds to the number of adders consumed in the DSP cascade structure,f _h(t) Representing a root node astIs the height of the binary tree of the class,f _b(t) Representing a root node astThe binary tree of the class corresponds to the number of consumed registers in the DSP cascade structure, and then the binary tree of the class and the left and right subtrees thereof have the following relations:

the formula (1) represents that the number of leaf nodes with the label of 0 in the large binary tree is the sum of the number of leaf nodes with the label of 0 in the left subtree and the right subtree; formula (2) shows that the consumption of the adder in the corresponding DSP cascade structure is obtained by subtracting 1 from the number of all leaf nodes labeled with 0 in the binary-like tree; formula (3) shows that in the process of constructing a large binary tree from a small binary tree, the height of the tree is increased by 1 on the basis of the maximum height in the left and right subtrees; formula (4) shows that the height difference of the left and right child nodes of all non-leaf nodes in the binary-like tree is derived from the difference of the heights of the left and right child nodes of the non-leaf nodes in the left and right subtrees, and also derived from the height difference of the left and right subtrees.

And 3, constructing a class binary tree with the root node being n. Since n can be represented as n = i + (n-i), the binary class tree with the root node n can be obtained by left and right subtrees of the binary class tree with the root node i and the binary class tree with the root node n-i respectively. Firstly, the representation of the binary tree classes with the root nodes of 1 and 2 can be obtained respectively, and then one binary tree class with the root node of 3 is constructed by selecting one binary tree class from the set of binary tree classes with the root node of 1 and the root node of 2 as a left sub-tree and a right sub-tree respectively. Since 4 can be expressed as 1+3, or 2+2, there are two options for constructing the binary tree of the class with root node 4 (since the left and right subtrees are exchanged without affecting the resource usage in the corresponding DSP cascade structure, we consider 1+3 and 3+1 as the same option). This in turn results in a representation of a binary tree of the kind with

root nodes

4, 5, …, n and its properties.

And 4, constructing the binary-like tree from bottom to top by adopting the mode described in the step 3, and obtaining the representation of the binary-like tree with the root node of n, thereby obtaining the cascading mode of n DSPs and the number of consumed registers and adders thereof. The use of these design registers and adders are then compared to find a pareto optimal design. Fig. 4 shows consumption of adders and registers corresponding to different cascade modes when 9 DSPs are cascaded, where an abscissa shows consumption of the adders, an ordinate shows consumption of the registers, and open dots show pareto optimal designs. As can be seen, one cascade consumes 2 adders and 10 registers, and the other cascade consumes 0 adders and 36 registers. Both of these cascading approaches are pareto optimal, as none is better than the other. That is to say that the design corresponding to all hollow points is optimal. But designs that consume 2 adders and 10 registers are preferred over designs that consume 2 adders and 11 registers. I.e., solid point correspondences, are not optimal because finding a design corresponding to a hollow point always consumes less register or adder resources.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present application further provides a resource processing apparatus for implementing the above-mentioned resource processing method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so specific limitations in one or more embodiments of the resource processing device provided below may refer to the limitations on the resource processing method in the foregoing, and details are not described here.

In one embodiment, as shown in fig. 6, there is provided a resource processing apparatus 600, comprising: structure obtaining module 610, binary tree class determining module 620, counting module 630 and structure determining module 640, wherein:

a structure obtaining module 610, configured to obtain at least one resource structure;

a binary tree class determining module 620, configured to determine a binary tree class of each resource structure;

a counting module 630, configured to determine, according to the binary tree class, the number of the first resource and the number of the second resource in each resource structure;

a structure determining module 640, configured to determine a target resource structure in the at least one resource structure by comparing the number of first resources in each of the resource structures and comparing the number of second resources in each of the resource structures; and the number of the first resources and the second resources in the target resource structure meets a preset condition.

In an embodiment, the binary tree-like determining module 620 further includes:

a third resource number obtaining module, configured to obtain the number of third resources in the resource structure;

a root node identifier determining module, configured to determine, according to the number of the third resources, an identifier of a root node of the binary tree-like tree;

and the generating module is used for generating a binary tree of the resource structure according to the identifier of the root node.

In an embodiment, the generating module is further configured to determine whether a left child node and a right child node exist in the root node according to the identifier of the root node; if the binary tree exists, determining a left child node identifier and a right child node identifier, and generating the binary tree according to the left child node identifier and the right child node identifier; and respectively taking the left child node and the right child node in the binary tree as root nodes, and returning to the step of judging whether the root nodes have the left child node and the right child node according to the identifiers of the root nodes.

In one embodiment, the resource processing apparatus further includes: the device comprises a set acquisition module, a binary tree classification module and a binary tree classification module, wherein the set acquisition module is used for acquiring reference identifiers which are arranged according to a preset sequence and a class binary tree set corresponding to each reference identifier; the generating module is further configured to select a target identifier from the reference identifiers according to the identifier of the root node; and obtaining the binary tree class of the resource structure according to the binary tree class set corresponding to the target identifier.

In an embodiment, the statistical module 630 is further configured to obtain a non-leaf node in the binary tree class; determining the height of a left child node and the height of a right child node of each non-leaf node; obtaining a first resource number corresponding to each non-leaf child node according to the difference between the height of each left child node and the height of each right child node; and obtaining the number of the first resources in the resource structure according to the sum of the number of the first resources corresponding to each non-leaf node.

In an embodiment, the statistical module 630 is further configured to obtain an identifier of a leaf node in the binary tree class; determining a target node in the leaf nodes according to the identifiers of the leaf nodes; and obtaining the number of second resources in the resource structure according to the number of the target nodes.

In an embodiment, the statistical module 630 is further configured to obtain a left sub-tree and a right sub-tree below a root node of the binary tree-like; and obtaining the number of the first resources in the resource structure corresponding to the binary tree-like root node according to the number of the first resources in the resource structure corresponding to the left sub-tree, the number of the first resources in the resource structure corresponding to the right sub-tree, and the height difference between the left sub-tree and the right sub-tree.

In an embodiment, the structure determining module 640 is further configured to determine the target resource structure by comparing the number of second resources in the at least one resource structure if the number of first resources in the at least one resource structure is equal to the number of second resources in the at least one resource structure; and if the number of the second resources in the at least one resource structure is equal, determining the target resource structure by comparing the number of the first resources in the at least one resource structure.

The modules in the resource processing device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 7. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing resource processing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a resource handling method.

Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is further provided, which includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

It should be noted that, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A method for processing resources, the method comprising:

obtaining at least one resource structure;

determining a binary tree class of each resource structure;

2. The method of claim 1, wherein determining the binary tree class for each of the resource structures comprises:

acquiring the number of third resources in the resource structure;

3. The method of claim 2, wherein generating the binary tree of classes of the resource structure based on the identity of the root node comprises:

4. The method of claim 2, wherein said step of determining a binary tree of the class for each of said resource structures is preceded by the steps of:

5. The method of claim 1, wherein the determining the number of the first resource and the second resource in each of the resource structures according to the binary tree-like tree comprises:

acquiring non-leaf nodes in the binary tree class;

6. The method of claim 1, wherein the determining the number of the first resource and the second resource in each of the resource structures according to the binary tree-like tree further comprises:

acquiring the identifier of the leaf node in the binary tree class;

7. The method of claim 1, wherein the determining the number of the first resource and the second resource in each of the resource structures according to the binary tree-like tree further comprises:

8. The method of claim 1, wherein determining the target resource structure of the at least one resource structure by comparing a number of first resources in each of the resource structures and comparing a number of second resources in each of the resource structures comprises:

9. An apparatus for resource handling, the apparatus comprising:

a structure obtaining module for obtaining at least one resource structure;

10. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 8.

11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 8.