CN114257221B - Signal edge detection delay circuit - Google Patents
Signal edge detection delay circuit Download PDFInfo
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- CN114257221B CN114257221B CN202210189113.5A CN202210189113A CN114257221B CN 114257221 B CN114257221 B CN 114257221B CN 202210189113 A CN202210189113 A CN 202210189113A CN 114257221 B CN114257221 B CN 114257221B
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- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
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Abstract
The invention discloses a signal edge detection delay circuit, which comprises an edge selection unit, a delay unit and an output unit; the edge selection unit is used for selectively applying a rising edge or a falling edge to the digital input signal, generating a rising edge signal or a falling edge signal and sending the rising edge signal or the falling edge signal to the delay unit; the delay unit is used for adding delay to the rising edge signal or the falling edge signal to generate an edge detection signal and sending the edge detection signal to the output unit; the output unit is used for receiving and outputting the edge detection signal. The invention can realize the edge detection function through a simple circuit structure and realize the edge detection of the EEPROM; the depletion type third NMOS transistor MN03 is connected into a diode structure to control the transmission delay of the digital signal, the diode structure effectively controls the leakage current, the back-stage charge can be discharged to zero, and therefore the edge detection signal is generated, and the structure is simple.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a signal edge detection delay circuit.
Background
Signal edge detection is widely used in the field of electronic circuit technology. For example, in an EEPROM (Electrically Erasable Programmable read only memory) of an SPI (Serial Peripheral Interface) Interface, a plurality of edge detection circuits are required. Referring to fig. 1, a circuit structure for implementing signal edge detection in a digital manner in the prior art is shown, where at least two stages of D flip-flops and a plurality of logic gates are required, and at the same time, more than 40 transistors are required, the circuit structure is very complex, and the hardware cost is high.
Disclosure of Invention
The invention aims to provide a signal edge detection delay circuit, which is used for solving the technical problems of complex circuit and higher hardware cost of the signal edge detection circuit in the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a signal edge detection delay circuit, which comprises an edge selection unit, a delay unit and an output unit;
the input end of the edge selection unit is connected with a digital input signal, the output end of the edge selection unit is connected with the input end of the delay unit, the output end of the delay unit is connected with the input end of the output unit, and the output end of the output unit outputs an edge detection signal;
the edge selection unit is used for selecting to apply a rising edge or a falling edge to the digital input signal, generating a rising edge signal or a falling edge signal and sending the rising edge signal or the falling edge signal to the delay unit; the delay unit is used for adding delay to the rising edge signal or the falling edge signal to generate the edge detection signal and sending the edge detection signal to the output unit; the output unit is used for receiving and outputting the edge detection signal.
In one possible design, when selecting to apply a falling edge to the digital input signal, the edge selection unit includes a first inverter INV1, the first inverter INV1 including a first PMOS transistor MP01 and a first NMOS transistor MN 01;
the source electrode and the substrate of the first PMOS tube MP01 are connected with a power supply, the grid electrode of the first PMOS tube MP01 is connected with the grid electrode of the first NMOS tube MN01 and then is accessed to the digital input signal, the drain electrode of the first PMOS tube MP01 is connected with the drain electrode of the first NMOS tube MN01 and then outputs the falling edge signal, and the source electrode and the substrate of the first NMOS tube MN01 are grounded.
In one possible design, the edge selection unit includes a conductor connected to the delay unit when a rising edge is selected to be applied to the digital input signal.
In one possible design, the delay unit includes a second PMOS transistor MP02, a second NMOS transistor MN02, a third NMOS transistor MN03, and a fourth NMOS transistor MN 04;
the source electrode and the substrate of the second PMOS transistor MP02 are connected to a power supply, the gate electrode of the second PMOS transistor MP02 is connected to the gate electrode of the second NMOS transistor MN02 and then receives the rising edge signal or the falling edge signal, and the drain electrode of the second PMOS transistor MP02 and the drain electrode of the third NMOS transistor MN03 are connected to the gate electrode of the fourth NMOS transistor MN04 respectively and then output the edge detection signal;
the source electrode and the substrate of the second NMOS transistor MN02 are grounded, the drain electrode of the second NMOS transistor MN02 is connected to the gate electrode of the third NMOS transistor MN03 and the source electrode of the third NMOS transistor MN03, respectively, and the substrate of the third NMOS transistor MN03 is grounded;
the source electrode, the drain electrode and the substrate of the fourth NMOS transistor MN04 are grounded after being connected.
In one possible design, when the rising edge signal or the falling edge signal transitions from high to low, the power supply charges the fourth NMOS transistor MN04 through the second PMOS transistor MP 02;
when the rising edge signal or the falling edge signal jumps from low level to high level, the third NMOS transistor MN03 and the second NMOS transistor MN02 drain the charge at the gate of the fourth NMOS transistor MN04 to ground.
In one possible design, the delay applied by the delay unit is calculated by the formula:
wherein the content of the first and second substances,
the delay is indicated as being the time of flight,
the dielectric constant is shown, W, L and tox respectively show the width, the length and the gate oxide thickness of the fourth NMOS tube MN04,
represents the equivalent resistance of the third NMOS transistor MN 03.
In one possible design, the output unit includes a second inverter INV2 or a NAND gate NAND 1.
In one possible design, the NAND gate NAND1 includes a third PMOS transistor MP03, a fourth PMOS transistor MP04, a fifth NMOS transistor MN05, and a sixth NMOS transistor MN 06;
the source electrode and the substrate of the third PMOS transistor MP03 are connected to a power supply, the gate electrode of the third PMOS transistor MP03 is connected to the gate electrode of the fifth NMOS transistor MN05 and then receives a rising edge detection signal, and the drain electrode of the third PMOS transistor MP03 is connected to the drain electrode of the fourth PMOS transistor MP04 and the drain electrode of the sixth NMOS transistor MN06 respectively and then outputs the rising edge detection signal;
a source and a substrate of the fourth PMOS transistor MP04 are connected to a power supply, a gate of the fourth PMOS transistor MP04 is connected to a gate of the sixth NMOS transistor MN06 and then receives a falling edge detection signal, and a drain of the fourth PMOS transistor MP04 is connected to a drain of the sixth NMOS transistor MN 06;
the source electrode of the sixth NMOS transistor MN06 is connected to the drain electrode of the fifth NMOS transistor MN05, the substrate of the sixth NMOS transistor MN06 is grounded, and the source electrode and the substrate of the fifth NMOS transistor MN05 are grounded.
Has the advantages that:
according to the invention, the edge selection unit selects to apply a rising edge or a falling edge to a digital input signal, a rising edge signal or a falling edge signal is generated, and the rising edge signal or the falling edge signal is sent to the delay unit; adding delay to the rising edge signal or the falling edge signal through a delay unit to generate an edge detection signal, and sending the edge detection signal to an output unit; and receiving and outputting the edge detection signal through an output unit. The invention can realize the edge detection function through a simple circuit structure, can be applied to the EEPROM of the SPI interface and realizes the edge detection of the EEPROM; this application connects depletion type third NMOS pipe MN03 into diode structure and controls digital signal's transmission delay, and this diode structure effective control bleeder current can make back level charge discharge to zero to generate border detected signal, simple structure has reduced the hardware cost.
Drawings
FIG. 1 is a schematic diagram of an edge detection circuit in the prior art;
fig. 2 is a block diagram of a signal edge detection delay circuit in the present embodiment;
FIG. 3 is a circuit configuration diagram along the selection unit in the present embodiment;
fig. 4 is a circuit configuration diagram of a delay unit in the present embodiment;
fig. 5 is a circuit configuration diagram of an output unit in the present embodiment;
FIG. 6 is a schematic diagram of a falling edge detection circuit in the present embodiment;
FIG. 7 is a signal timing diagram of a falling edge detection circuit in the present embodiment;
FIG. 8 is a schematic diagram of a rising edge detection circuit according to the present embodiment;
FIG. 9 is a signal timing diagram of the rising edge detection circuit in the present embodiment;
FIG. 10 is a schematic diagram of another falling edge detection circuit in the present embodiment;
FIG. 11 is a timing diagram of another falling edge delay circuit in the present embodiment;
FIG. 12 is a schematic diagram of another rising edge delay circuit in the present embodiment;
fig. 13 is a signal timing diagram of another rising edge delay circuit in this embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments in the present description, belong to the protection scope of the present invention.
Examples
In order to solve the technical problems that an edge detection circuit structure in the prior art needs at least two stages of D triggers and a plurality of logic gates and needs more than 40 transistors, the circuit structure is very complex and the hardware cost is high, the embodiment of the application provides a signal edge detection delay circuit, the circuit can realize an edge detection function through a simple circuit structure, and can be applied to an EEPROM (electrically erasable programmable read-only memory) of an SPI (serial peripheral interface) to realize the edge detection of the EEPROM.
As shown in fig. 2 to 13, the present invention provides a signal edge detection delay circuit, which includes an edge selection unit, a delay unit and an output unit;
the input end of the edge selection unit is connected with a digital input signal, the output end of the edge selection unit is connected with the input end of the delay unit, the output end of the delay unit is connected with the input end of the output unit, and the output end of the output unit outputs an edge detection signal;
the edge selection unit is used for selecting to apply a rising edge or a falling edge to the digital input signal, generating a rising edge signal or a falling edge signal and sending the rising edge signal or the falling edge signal to the delay unit; the delay unit is used for adding delay to the rising edge signal or the falling edge signal to generate the edge detection signal and sending the edge detection signal to the output unit; the output unit is used for receiving and outputting the edge detection signal.
As shown IN fig. 2, a digital input signal enters from an input terminal IN of the edge selection unit, a rising edge or a falling edge is applied to the digital input signal through the edge selection unit to generate a rising edge signal or a falling edge signal, such as a signal at a point a IN the figure, then the signal at the point a is sent from an output terminal of the edge selection unit to the delay unit, after a delay is added to the rising edge signal or the falling edge signal by the delay unit, an edge detection signal is generated, such as a signal at a point B IN the figure, and then the signal at the point B is output from the output unit.
Based on the above disclosure, the edge detection function can be realized through a simple circuit structure in the embodiment, and the edge detection function can be applied to the EEPROM of the SPI interface, so that the edge detection of the EEPROM is realized, and the hardware cost of circuit design is reduced.
In a specific embodiment, when selecting to apply a falling edge to the digital input signal, as shown in fig. 3, 6 and 10, the edge selection unit includes a first inverter INV1, the first inverter INV1 including a first PMOS transistor MP01 and a first NMOS transistor MN 01;
the source electrode and the substrate of the first PMOS tube MP01 are connected with a power supply, the grid electrode of the first PMOS tube MP01 is connected with the grid electrode of the first NMOS tube MN01 and then is accessed to the digital input signal through an input end IN, the drain electrode of the first PMOS tube MP01 is connected with the drain electrode of the first NMOS tube MN01 and then outputs the falling edge signal, if the signal at the point A IN the figure is the falling edge signal, the source electrode and the substrate of the first NMOS tube MN01 are grounded.
IN a specific embodiment, as shown IN fig. 8 and 12, when the rising edge is selected to be applied to the digital input signal, the edge selection unit includes a wire connected to the delay unit, that is, without processing the digital input signal, the digital input signal is directly input to the delay unit through the wire through the input terminal IN, where the digital input signal is a rising edge signal, such as a signal at a point IN the figure.
Referring to fig. 4, 6, 8, 10 and 12, in a specific embodiment, the delay unit includes a second PMOS transistor MP02, a second NMOS transistor MN02, a third NMOS transistor MN03 and a fourth NMOS transistor MN 04;
the source and the substrate of the second PMOS transistor MP02 are connected to a power supply, the gate of the second PMOS transistor MP02 is connected to the gate of the second NMOS transistor MN02 and then receives the rising edge signal or the falling edge signal, such as a signal at a point a in the figure, and the drain of the second PMOS transistor MP02 and the drain of the third NMOS transistor MN03 are connected to the gate of the fourth NMOS transistor MN04 respectively and then output the edge detection signal, such as a signal at a point B in the figure;
the source electrode and the substrate of the second NMOS transistor MN02 are grounded, the drain electrode of the second NMOS transistor MN02 is connected to the gate electrode of the third NMOS transistor MN03 and the source electrode of the third NMOS transistor MN03, respectively, and the substrate of the third NMOS transistor MN03 is grounded;
the source electrode, the drain electrode and the substrate of the fourth NMOS transistor MN04 are grounded after being connected.
In a specific embodiment, when the rising edge signal or the falling edge signal jumps from high level to low level, the power supply charges the fourth NMOS transistor MN04 through the second PMOS transistor MP 02;
when the rising edge signal or the falling edge signal jumps from low level to high level, the third NMOS transistor MN03 and the second NMOS transistor MN02 drain the charge at the gate of the fourth NMOS transistor MN04 to ground.
As shown IN fig. 6 to 13, by providing the delay unit, a pulse width of
When the signal at the point a changes from high to low, the power supply VDD charges the fourth NMOS transistor MN04, which is applied as a capacitor at the point B, through the second PMOS transistor MP 02; when the signal at the point A jumps from low level to high level, the charge of the gate of the fourth NMOS transistor MN04 at the point B is discharged to the ground through the depletion type third NMOS transistor MN03 and the enhancement type second NMOS transistor MN 02. Since the depletion type third NMOS transistor MN03 is connected to form a diode structure, the structure can control the leakage current well, and also can make the charge at the B point leak to zero. Due to the existence of the third NMOS tube MN03, when the signal at the point A jumps from low to high, the bleeder current is controlled, so that delay is generated
。
Wherein, the calculation formula of the delay applied by the delay unit is as follows:
wherein the content of the first and second substances,
the delay is indicated as being the time of flight,
the dielectric constant is shown, W, L and tox respectively show the width, the length and the gate oxide thickness of the fourth NMOS tube MN04,
represents the equivalent resistance of the third NMOS transistor MN03, wherein,
depending on the characteristics of the depletion mode device provided by the process.
As shown in fig. 6, 8, 10 and 12, in a specific embodiment, the output unit includes a second inverter INV2 or a NAND gate NAND1, so that the edge detection signal in this embodiment, such as the signal at point B in the figure, can be output through the NAND gate NAND1 or through the second inverter INV 2. When the output is performed through a NAND gate NAND1, the gate of the second PMOS transistor MP02, the drain of the second PMOS transistor MP02, the drain of the third NMOS transistor MN03, and the gate of the fourth NMOS transistor MN04 are respectively connected to the input end of the NAND gate NAND 1. When the output is performed through the second inverter INV2, the drain of the second PMOS transistor MP02, the drain of the third NMOS transistor MN03, and the gate of the fourth NMOS transistor MN04 are respectively connected to the input end of the second inverter INV 2.
The second inverter INV2 has a conventional inverter structure, and the specific circuit structure is not described herein again.
In a specific embodiment, as shown in fig. 5, the NAND gate NAND1 includes a third PMOS transistor MP03, a fourth PMOS transistor MP04, a fifth NMOS transistor MN05, and a sixth NMOS transistor MN 06;
a source electrode and a substrate of the third PMOS transistor MP03 are connected to a power supply, a gate electrode of the third PMOS transistor MP03 is connected to a gate electrode of the fifth NMOS transistor MN05 and then receives a rising edge detection signal, such as a signal at a point B in the figure, and a drain electrode of the third PMOS transistor MP03 is connected to a drain electrode of the fourth PMOS transistor MP04 and a drain electrode of the sixth NMOS transistor MN06, respectively, and then outputs the rising edge detection signal, such as a signal at a point B in the figure;
the source electrode and the substrate of the fourth PMOS transistor MP04 are connected to a power supply, the gate electrode of the fourth PMOS transistor MP04 is connected to the gate electrode of the sixth NMOS transistor MN06 and then receives a falling edge detection signal, such as a signal at point B in the figure, and the drain electrode of the fourth PMOS transistor MP04 is connected to the drain electrode of the sixth NMOS transistor MN 06;
the source electrode of the sixth NMOS tube MN06 is connected with the drain electrode of the fifth NMOS tube MN05, the substrate of the sixth NMOS tube MN06 is grounded, and the source electrode and the substrate of the fifth NMOS tube MN05 are grounded.
The working principle of the signal edge detection delay circuit in the embodiment is as follows:
first, a digital input signal enters from an input terminal IN of an edge selection unit, a rising edge or a falling edge is applied to the digital input signal through the edge selection unit to generate a rising edge signal or a falling edge signal, such as a signal at a point a IN the figure, then the rising edge signal or the falling edge signal is sent to a delay unit from an output terminal of the edge selection unit, after delay is added to the rising edge signal or the falling edge signal by the delay unit, an edge detection signal is generated, such as a signal at a point B IN the figure, and then the signal at the point B is output from an output unit.
Then, a pulse width of
When the signal at the point a changes from high to low, the power supply VDD charges the fourth NMOS transistor MN04, which is applied as a capacitor at the point B, through the second PMOS transistor MP 02; when the signal at the point A jumps from low level to high level, the charge of the gate of the fourth NMOS transistor MN04 at the point B is discharged to the ground through the depletion type third NMOS transistor MN03 and the enhancement type second NMOS transistor MN 02. Because the depletion type third NMOS transistor MN03 is connected to form a diode structure, the structure can well control the leakage current, and can also make the charge at the B point leak to zero. Due to the existence of the third NMOS tube MN03, when the signal at the point A jumps from low to high, the bleeder current is controlled, so that delay is generated
And generating a rising edge detection signal or a falling edge detection signal.
And finally, outputting the rising edge detection signal or the falling edge detection signal through an output unit, wherein the rising edge detection signal or the falling edge detection signal can be used for detecting edge signals in an EEPROM of an SPI interface.
Based on the above disclosure, the present embodiment generates a rising edge signal or a falling edge signal by applying a rising edge or a falling edge to a digital input signal through the edge selection unit, and sends the rising edge signal or the falling edge signal to the delay unit; adding delay to the rising edge signal or the falling edge signal through a delay unit to generate an edge detection signal, and sending the edge detection signal to an output unit; and receiving and outputting the edge detection signal through an output unit. The invention can realize the edge detection function through a simple circuit structure, can be applied to the EEPROM of the SPI interface and realizes the edge detection of the EEPROM; this application connects depletion type third NMOS pipe MN03 into diode structure and controls digital signal's transmission delay, and this diode structure effective control bleeder current can make back level charge discharge to zero to generate border detected signal, simple structure has reduced the hardware cost.
Finally, it should be noted that: the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A signal edge detection delay circuit is characterized by comprising an edge selection unit, a delay unit and an output unit;
the input end of the edge selection unit is connected with a digital input signal, the output end of the edge selection unit is connected with the input end of the delay unit, the output end of the delay unit is connected with the input end of the output unit, and the output end of the output unit outputs an edge detection signal;
the edge selection unit is used for selecting to apply a rising edge or a falling edge to the digital input signal, generating a rising edge signal or a falling edge signal and sending the rising edge signal or the falling edge signal to the delay unit; the delay unit is used for adding delay to the rising edge signal or the falling edge signal to generate the edge detection signal and sending the edge detection signal to the output unit; the output unit is used for receiving and outputting the edge detection signal;
when the digital input signal is selected to be applied with a rising edge, the edge selection unit comprises a wire connected with the delay unit;
the delay unit comprises a second PMOS tube MP02, a second NMOS tube MN02, a third NMOS tube MN03 and a fourth NMOS tube MN 04;
the source electrode and the substrate of the second PMOS transistor MP02 are connected to a power supply, the gate electrode of the second PMOS transistor MP02 is connected to the gate electrode of the second NMOS transistor MN02 and then receives the rising edge signal or the falling edge signal, and the drain electrode of the second PMOS transistor MP02 and the drain electrode of the third NMOS transistor MN03 are connected to the gate electrode of the fourth NMOS transistor MN04 respectively and then output the edge detection signal;
the source electrode and the substrate of the second NMOS transistor MN02 are grounded, the drain electrode of the second NMOS transistor MN02 is connected to the gate electrode of the third NMOS transistor MN03 and the source electrode of the third NMOS transistor MN03, and the substrate of the third NMOS transistor MN03 is grounded;
the source electrode, the drain electrode and the substrate of the fourth NMOS transistor MN04 are grounded after being connected;
the output unit includes a second inverter INV2 or a NAND gate NAND 1;
the NAND gate NAND1 comprises a third PMOS transistor MP03, a fourth PMOS transistor MP04, a fifth NMOS transistor MN05 and a sixth NMOS transistor MN 06;
the source electrode and the substrate of the third PMOS transistor MP03 are connected to a power supply, the gate electrode of the third PMOS transistor MP03 is connected to the gate electrode of the fifth NMOS transistor MN05 and then receives a rising edge detection signal, and the drain electrode of the third PMOS transistor MP03 is connected to the drain electrode of the fourth PMOS transistor MP04 and the drain electrode of the sixth NMOS transistor MN06 respectively and then outputs the rising edge detection signal;
the source electrode and the substrate of the fourth PMOS transistor MP04 are connected to a power supply, the gate electrode of the fourth PMOS transistor MP04 is connected to the gate electrode of the sixth NMOS transistor MN06 and then receives a falling edge detection signal, and the drain electrode of the fourth PMOS transistor MP04 is connected to the drain electrode of the sixth NMOS transistor MN 06;
the source electrode of the sixth NMOS transistor MN06 is connected to the drain electrode of the fifth NMOS transistor MN05, the substrate of the sixth NMOS transistor MN06 is grounded, and the source electrode and the substrate of the fifth NMOS transistor MN05 are grounded.
2. The signal edge detection delay circuit of claim 1, wherein when selecting to apply a falling edge to the digital input signal, the edge selection unit comprises a first inverter INV1, the first inverter INV1 comprising a first PMOS transistor MP01 and a first NMOS transistor MN 01;
the source electrode and the substrate of the first PMOS tube MP01 are connected with a power supply, the grid electrode of the first PMOS tube MP01 is connected with the grid electrode of the first NMOS tube MN01 and then is accessed to the digital input signal, the drain electrode of the first PMOS tube MP01 is connected with the drain electrode of the first NMOS tube MN01 and then outputs the falling edge signal, and the source electrode and the substrate of the first NMOS tube MN01 are grounded.
3. The signal edge detection delay circuit of claim 1, wherein when the rising edge signal or the falling edge signal transitions from high to low, a power supply charges the fourth NMOS transistor MN04 through the second PMOS transistor MP 02;
when the rising edge signal or the falling edge signal jumps from low level to high level, the third NMOS transistor MN03 and the second NMOS transistor MN02 drain the charge at the gate of the fourth NMOS transistor MN04 to ground.
4. The signal edge detection delay circuit of claim 1, wherein the delay applied by the delay unit is calculated by the equation:
wherein the content of the first and second substances,
which is indicative of the delay of the transmission of the signal,
to representThe dielectric constants W, L and tox respectively represent the width, the length and the gate oxide thickness of the fourth NMOS tube MN04,
represents the equivalent resistance of the third NMOS transistor MN 03.
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