CN114257082A - Control method of charge pump circuit applicable to thin gate oxide layer process - Google Patents

Control method of charge pump circuit applicable to thin gate oxide layer process Download PDF

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Publication number
CN114257082A
CN114257082A CN202110224520.0A CN202110224520A CN114257082A CN 114257082 A CN114257082 A CN 114257082A CN 202110224520 A CN202110224520 A CN 202110224520A CN 114257082 A CN114257082 A CN 114257082A
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effect transistor
field effect
diode
charge pump
fet
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Chinese (zh)
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黄洪伟
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Shenzhen Injoinic Technology Co Ltd
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Shenzhen Injoinic Technology Co Ltd
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Priority to CN202110224520.0A priority Critical patent/CN114257082A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

Abstract

The application discloses a control method of a charge pump circuit applicable to a thin gate oxide layer process, which comprises the following steps: the charge pump auxiliary circuit outputs high level voltage and provides a driving signal for the driving circuit; the charge pump circuit outputs a driving voltage suitable for a thin gate oxide layer process to drive the N-type power tube. By adopting the embodiment of the application, the driving voltage suitable for the thin gate oxide layer process can be output to drive the N-type power tube, so that the cost is lower and the reliability is high.

Description

Control method of charge pump circuit applicable to thin gate oxide layer process
Technical Field
The present disclosure relates to the field of charge pump circuits, and particularly to a control method for a charge pump circuit applicable to a thin gate oxide process.
Background
The charge pump circuit is often applied to a power-level analog integrated circuit, and in some systems, the source voltage of an N-type power transistor is the highest power supply voltage of the system, and when the N-type power transistor is driven, a voltage signal higher than the highest power supply voltage of the system is required. However, the conventional charge pump circuit usually employs an off-chip large capacitor, which is costly and consumes one more pin.
Disclosure of Invention
The embodiment of the application provides a charge pump circuit, a control method of the charge pump circuit, a chip and an electronic device.
In a first aspect, an embodiment of the present application provides a charge pump circuit, which includes a charge pump auxiliary module, a driving module, a charge pump module, an N-type power transistor, a diode Z2, and a diode Z3;
the charge pump auxiliary module is connected with the driving module, the driving module is connected with the charge pump module, the charge pump module is connected with the grid electrode of the N-type power tube, the cathode of the diode Z2 is connected between the charge pump module and the grid electrode of the N-type power tube, the anode of the diode Z2 is connected with the cathode of the diode Z3, and the anode of the diode Z3 is connected with the source electrode of the N-type power tube;
the charge pump auxiliary module is used for outputting high level voltage and providing a driving signal for the driving module;
the charge pump module is used for outputting a driving voltage suitable for a thin gate oxide layer process so as to drive the N-type power tube.
In one implementation, the charge pump auxiliary module includes a fet M1, a fet M2, a fet M3, a fet M4, a fet M5, a fet M6, a fet M7, a fet M8, a fet M9, a fet M10, a fet M11, a fet M12, a diode Z1, a resistor R1, a resistor R2, a resistor R3, an inverter I1, a diode D1, a diode D2, and a diode D3;
the drain of the field effect transistor M1 is connected to a signal VM, the drain of the field effect transistor M3 is connected to a power supply VCC, the gate of the field effect transistor M4 is connected to a signal COMP via the inverter I1, the gate of the field effect transistor M8 and the gate of the field effect transistor M9 are connected between the signal COMP and the inverter I1, the gate of the field effect transistor M1 is connected in series with the gate of the field effect transistor M2 and then connected to the drain of the field effect transistor M11, the gate of the field effect transistor M3 is connected to the drain of the field effect transistor M4, the source of the field effect transistor M4 is connected to one end of a resistor R2, the gate of the field effect transistor M6 is connected to the gate of the field effect transistor M7, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M8, the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M10, and the gate of the field effect transistor M10 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M11 is connected to the drain of the field effect transistor M9, the source of the field effect transistor M9 is connected to one end of the resistor R2 and the source of the field effect transistor M4, the other end of the resistor R2 is connected to the drain of the field effect transistor M5, the source of the field effect transistor M12 is connected to the node B, the gate and the drain of the field effect transistor M12 are connected to the drain of the field effect transistor M2 and the node a after being connected, the resistor R3 is connected in parallel between the source and the drain of the field effect transistor M11, one end of the diode Z1 is connected to the node a, and the other end of the diode Z1 is connected to the drain of the field effect transistor M6;
the diode D1 is connected in parallel to the FET M1, the diode D2 is connected in parallel to the FET M3, and the diode D3 is connected in parallel to the FET M2;
the diode D1, the diode D2 and the diode D3 are all independent diodes or anti-parallel diodes carried in the field effect tube.
In one implementation, the field effect transistor M6 and the field effect transistor M7 are connected to form a current mirror structure, and the width-to-length ratio is 1: 1;
the field effect transistor M10 and the field effect transistor M11 are connected to form a current mirror structure, and the width-to-length ratio is 1: N.
In an implementation manner, when the voltage of the signal VM is lower than the voltage of the power source VCC, the voltage of the signal COMP is a low level, the fet M3 is in an on state, the fets M1 and M2 are in an off state, and the voltage of the node B is:
VB＝VCC-VDS3-VGS12；
wherein, the VBIs the voltage of node B, VCC is the voltage of power VCC, VDS3Is the voltage difference between the source and the drain of the field effect transistor M3, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12.
In an implementation manner, when the voltage of the signal VM is higher than the voltage of the power source VCC, the voltage of the signal COMP is a high level, the fet M3 is in an off state, the fets M1 and M2 are in an on state, and the voltage of the node B is:
VB＝VZ-VGS6-VGS12；
wherein, the VBIs the voltage of the node B, the VZFor diode reverse breakdown voltage, said VGS6Is the voltage difference between the gate and the source of the field effect transistor M6, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12.
In an implementation, the driving module includes an inverter I2, an inverter I3, an inverter I4, and an inverter I5;
the input end of the inverter I2 is connected with a clock signal CLK, the output end of the inverter I2 is connected with the input end of the inverter I3, the output end of the inverter I3 is connected with the input end of the inverter I4, the output end of the inverter I4 is connected with the input end of the inverter I5, and the output end of the inverter I5 is connected with a node D.
In one implementation, the charge pump module includes a capacitor C1, a capacitor C2, a field effect transistor M13, a field effect transistor M14, a field effect transistor M15 and a field effect transistor M16, a diode D4, a diode D5, a diode D6 and a diode D7;
the field effect transistor M13 is cross-coupled with the field effect transistor M14, the field effect transistor M15 is cross-coupled with the field effect transistor M16, one end of the capacitor C1 is connected with a node E, the other end of the capacitor C1 is connected with the node C, one end of the capacitor C2 is connected with a node F, and the other end of the capacitor C2 is connected with a node D;
the charge pump module further comprises a diode D4, a diode D5, a diode D6, and a diode D7;
the diode D4 is connected in parallel to the FET M13, the diode D5 is connected in parallel to the FET M14, the diode D6 is connected in parallel to the FET M15, and the diode D7 is connected in parallel to the FET M16;
the diode D4, the diode D5, the diode D6 and the diode D7 are all independent diodes or anti-parallel diodes carried in a field effect tube.
In one implementation, the fet M13, fet M14, fet M15 and fet M16 are all charge pump switches;
the FET M13, FET M14, FET M15 and FET M16 turn on or off as determined by the voltages at the node E and the node F;
the width-length ratios of the field effect transistor M13 and the field effect transistor M14 are the same, and the width-length ratios of the field effect transistor M15 and the field effect transistor M16 are the same.
In one implementation, the driving voltage of the N-type power transistor is:
VGS17＝VZ+VGS6-VGS12-VDS13,14-VD+VDS17；
wherein, the VGS17Is the driving voltage of the N-type power tube, VZFor diode reverse breakdown voltage, said VGS6Is the voltage difference between the gate and the source of the field effect transistor M6, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12, the VDS13,14The voltage difference between drain and source of the FET M13 and the FET M14 is VDIs the voltage of node D, VDS17The voltage difference between the drain electrode and the source electrode of the N-type power tube is obtained.
In a second aspect, embodiments of the present application provide a control method for a charge pump circuit, where the charge pump circuit includes a charge pump auxiliary module, a driving module, a charge pump module, an N-type power transistor, a diode Z2, and a diode Z3;
the charge pump auxiliary module is connected with the driving module, the driving module is connected with the charge pump module, the charge pump module is connected with the grid electrode of the N-type power tube, the cathode of the diode Z2 is connected between the charge pump module and the grid electrode of the N-type power tube, the anode of the diode Z2 is connected with the cathode of the diode Z3, and the anode of the diode Z3 is connected with the source electrode of the N-type power tube; the method comprises the following steps:
the charge pump auxiliary module outputs high level voltage and provides a driving signal for the driving module;
the charge pump module outputs a driving voltage suitable for a thin gate oxide layer process to drive the N-type power tube.
In one implementation, the method further comprises:
if the voltage of the signal VM is lower than the voltage of the power supply VCC and the voltage of the signal COMP is at a low level, the charge pump auxiliary module controls the field-effect transistor M3 to be in an on state and controls the field-effect transistor M1 and the field-effect transistor M2 to be in an off state;
if the voltage of the signal VM is higher than the voltage of the power supply VCC and the voltage of the signal COMP is at a high level, the charge pump auxiliary module controls the field-effect transistor M3 to be in a closed state, and the field-effect transistor M1 and the field-effect transistor M2 are in an open state.
In a third aspect, an embodiment of the present application provides a chip including the charge pump circuit as described in the first aspect.
In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the charge pump circuit as described in the first aspect.
It can be seen that, in the embodiment of the present application, a driving voltage suitable for a thin gate oxide layer process can be output without using an off-chip large capacitor manner, so as to drive the N-type power transistor, which is low in cost and high in reliability.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a charge pump circuit according to an embodiment of the present disclosure;
fig. 2 is a flowchart illustrating a control method of a charge pump circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The term "and/or" in this application is only one kind of association relationship describing the associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein indicates that the former and latter related objects are in an "or" relationship.
The "plurality" appearing in the embodiments of the present application means two or more. The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application. The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application.
Referring to fig. 1, fig. 1 is a schematic circuit diagram of a charge pump circuit according to an embodiment of the present disclosure, where the charge pump circuit includes a charge pump auxiliary module 10, a driving module 20, a charge pump module 30, an N-type power transistor M17, a diode Z2, and a diode Z3;
the charge pump auxiliary module 10 is connected to the driving module 20, the driving module 20 is connected to the charge pump module 30, the charge pump module 30 is connected to the gate of the N-type power transistor, the cathode of the diode Z2 is connected between the charge pump module and the gate of the N-type power transistor, the anode of the diode Z2 is connected to the cathode of the diode Z3, and the anode of the diode Z3 is connected to the source of the N-type power transistor;
the charge pump auxiliary module is used for outputting high level voltage and providing a driving signal for the driving module;
the charge pump module is used for outputting a driving voltage suitable for a thin gate oxide layer process so as to drive the N-type power tube M17.
Wherein, the diode Z2 and the diode Z3 are Zener diodes. The diode Z3 and the diode Z3 are connected in a back-to-back mode, and the voltage difference between the gate and the source of the N-type power tube M17 can be limited, so that the gate-source breakdown of the N-type power tube M17 is avoided.
The charge pump circuit further comprises a diode D8, the diode D8 is connected in parallel to the N-type power tube M17, and the output signal OUT is obtained after the positive electrode of the diode Z3 is intersected with the source electrode of the N-type power tube.
In an implementation manner of the present application, the charge pump auxiliary module includes a fet M1, a fet M2, a fet M3, a fet M4, a fet M5, a fet M6, a fet M7, a fet M8, a fet M9, a fet M10, a fet M11, a fet M12, a diode Z1, a resistor R1, a resistor R2, a resistor R3, and an inverter I1;
the drain of the field effect transistor M1 is connected to a signal VM, the drain of the field effect transistor M3 is connected to a power supply VCC, the gate of the field effect transistor M4 is connected to a signal COMP via the inverter I1, the gate of the field effect transistor M8 and the gate of the field effect transistor M9 are connected between the signal COMP and the inverter I1, the gate of the field effect transistor M1 is connected in series with the gate of the field effect transistor M2 and then connected to the drain of the field effect transistor M11, the gate of the field effect transistor M3 is connected to the drain of the field effect transistor M4, the source of the field effect transistor M4 is connected to one end of a resistor R2, the gate of the field effect transistor M6 is connected to the gate of the field effect transistor M7, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M8, the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M10, and the gate of the field effect transistor M10 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M11 is connected to the drain of the field effect transistor M9, the source of the field effect transistor M9 is connected to one end of the resistor R2 and the source of the field effect transistor M4, the other end of the resistor R2 is connected to the drain of the field effect transistor M5, the source of the field effect transistor M12 is connected to the node B, the gate and the drain of the field effect transistor M12 are connected to the drain of the field effect transistor M2 and the node a after being connected, the resistor R3 is connected in parallel between the source and the drain of the field effect transistor M11, one end of the diode Z1 is connected to the node a, and the other end of the diode Z1 is connected to the drain of the field effect transistor M6.
In one implementation of the present application, the charge pump assist module further includes a diode D1, a diode D2, and a diode D3;
the diode D1 is connected in parallel to the FET M1, the diode D2 is connected in parallel to the FET M3, and the diode D3 is connected in parallel to the FET M2;
the diode D1, the diode D2 and the diode D3 are all independent diodes or anti-parallel diodes carried in the field effect tube.
The diode D1 and the diode D3 are two reverse diodes connected in series to avoid the signal VM from passing through the diodes to the node a.
The signal COMP is a voltage comparison signal between the signal VM and the power supply VCC, and is at a high level when the voltage of the signal VM is greater than the voltage of the voltage VCC, and at a low level when the voltage of the signal VM is less than the voltage of the voltage VCC. Fet M4, fet M8, and fet M9 are switching transistors associated with signal COMP.
The gate of the field effect transistor M5 is connected to a signal EN, the signal EN is an enable signal, and the field effect transistor M5 is a switching transistor related to the signal EN.
The resistor R2 is a voltage dividing resistor.
Wherein, the diode Z1 is a zener diode for stabilizing the voltage at the node a.
The field effect transistor M12 is a transistor with a shorted gate and a shorted drain, and is used for adjusting the voltage drop between the node a and the node B.
In one implementation of the present application, the fet M6 and the fet M7 are connected to form a current mirror structure, and the width-to-length ratio is 1: 1;
the field effect transistor M10 and the field effect transistor M11 are connected to form a current mirror structure, and the width-to-length ratio is 1: N.
Wherein, N is 1 or other values, for example.
In an implementation manner of the present application, when the voltage of the signal VM is lower than the voltage of the power VCC, the voltage of the signal COMP is a low level, the fet M3 is in an on state, the fets M1 and M2 are in an off state, and the voltage of the node B is:
VB＝VCC-VDS3-VGS12；
wherein, the VBIs the voltage of node B, VCC is the voltage of power VCC, VDS3Is the voltage difference between the source and the drain of the field effect transistor M3, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12.
In an implementation manner of the present application, when the voltage of the signal VM is higher than the voltage of the power VCC, the voltage of the signal COMP is high level, the fet M3 is in an off state, the fet M1 and the fet M2 are in an on state (at this time, the voltage of the node a is clamped by the diode Z1, and the voltage of the signal VM is higher than the voltage stabilized by the diode Z1), and the voltage of the node B is:
VB＝VZ-VGS6-VGS12；
wherein, the VBIs the voltage of the node B, the VZIs the reverse breakdown voltage of Zener diode, VGS6Is the voltage difference between the gate and the source of the field effect transistor M6, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12.
It can be seen that the voltage at node B is selected according to the voltage of signal VM and the voltage of power VCC, and is supplied to the driving module 20 as a high level voltage, where the voltages at nodes C and D are at an amplitude VBTwo opposite phase voltages. From VBIt can be seen that the magnitude of the voltage at node B can be adjusted by changing the width-to-length ratio of the fet M12 for zener diodes with different reverse breakdown voltages.
In one implementation of the present application, the driving module includes an inverter I2, an inverter I3, an inverter I4, and an inverter I5;
the input end of the inverter I2 is connected with a clock signal CLK, the output end of the inverter I2 is connected with the input end of the inverter I3, the output end of the inverter I3 is connected with the input end of the inverter I4, the output end of the inverter I4 is connected with the input end of the inverter I5, and the output end of the inverter I5 is connected with a node D.
In one implementation of the present application, the charge pump module includes a capacitor C1, a capacitor C2, a fet M13, a fet M14, fets M15 and M16, a diode D4, a diode D5, a diode D6 and a diode D7;
the field effect transistor M13 is cross-coupled with the field effect transistor M14, the field effect transistor M15 is cross-coupled with the field effect transistor M16, one end of the capacitor C1 is connected with a node E, the other end of the capacitor C1 is connected with the node C, one end of the capacitor C2 is connected with a node F, and the other end of the capacitor C2 is connected with a node D;
the charge pump module further comprises a diode D4, a diode D5, a diode D6, and a diode D7;
the diode D4 is connected in parallel to the FET M13, the diode D5 is connected in parallel to the FET M14, the diode D6 is connected in parallel to the FET M15, and the diode D7 is connected in parallel to the FET M16;
the diode D4, the diode D5, the diode D6 and the diode D7 are all independent diodes or anti-parallel diodes carried in a field effect tube.
The capacitor C1 and the capacitor C2 are MIM capacitors of the same type and have the same capacitance value.
In one implementation of the present application, the fet M13, the fet M14, the fet M15, and the fet M16 are all charge pump switching transistors;
the FET M13, FET M14, FET M15 and FET M16 turn on or off as determined by the voltages at the node E and the node F;
the width-length ratios of the field effect transistor M13 and the field effect transistor M14 are the same, and the width-length ratios of the field effect transistor M15 and the field effect transistor M16 are the same.
In an implementation manner of the present application, when the charge pump circuit is started, a voltage difference between two plates of a capacitor C1 and a capacitor C2 is 0, because a voltage of a signal VM is greater than a voltage of a node B, the signal VM charges the capacitor C1 through a diode D4, the signal VM charges the capacitor C2 through a diode D5, after a plurality of cycles, voltages between two plates of the capacitor C1 and the capacitor C2 gradually increase, and when voltages at two ends of the capacitor C1 and the capacitor C2 satisfy formula 1, the signal VM charges the capacitor C1 and the capacitor C2 through the fet M13 and the fet M14;
VC1,C2＞VM-VB+VTH13,14 (1)
wherein, the VC1,C2Is the voltage across the capacitor C1 or the capacitor C2, the VM is the voltage of the access signal VM, VTH13,14Is the threshold voltage of the fet M13 or the fet M14.
After the charging of the capacitor C1 and the capacitor C2 is completed, the voltages across the capacitor C1 and the capacitor C2 satisfy formula 2;
VC1＝VC2＝VM-VDS13,14 (2)
wherein, the VC1Is the voltage across the capacitor C1, the VC2Is the voltage across the capacitor C2, the VDS13,14Is the drain and source voltage difference of the field effect transistor M13 or the field effect transistor M14.
When the voltage at the two ends of the capacitor gradually increases to the maximum voltage, the voltage at the node C is at a low level, and the voltage at the node D is at a high level, the voltage at the node F is:
VF＝VC2+VB (3)
wherein, the VFIs the voltage of the node F.
When the voltage of the node C is at a high level and the voltage of the node D is at a low level, the voltage of the node E is:
VE＝VC1+VB (4)
wherein VF is the voltage of the node F.
Combining equations 1, 2, and 3, it can be seen that after the charge pump system is stabilized, the voltage at node G is:
VG＝VB+VM-VDS13,14-VD (5)
wherein, VDFor diode forward voltage drop, when charge pump system normally works, the voltage of signal VM is greater than the voltage of power VCC, and the driving voltage of N type power tube at this moment is:
VGS17＝VZ+VGS6-VGS12-VDS13,14-VD+VDS17 (6)
wherein, the VGS17Is the driving voltage of the N-type power tube, VGS6Is the voltage difference between the gate and the source of the field effect transistor M6, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12, VDS17The voltage difference between the drain electrode and the source electrode of the N-type power tube is obtained.
As can be seen from equation 6, the driving voltage of the power transistor is independent of the voltage amplitude of the signal VM. When the voltage of the signal VM is larger, the driving voltage suitable for the thin gate oxide layer process can be output through the charge pump circuit to drive the N-type power tube.
It can be seen that, in the embodiment of the present application, a driving voltage suitable for a thin gate oxide layer process can be output without using an off-chip large capacitor manner, so as to drive the N-type power transistor, which is low in cost and high in reliability.
Referring to fig. 2, fig. 2 is a schematic flowchart of a control method of a charge pump circuit according to an embodiment of the present disclosure, where the charge pump circuit is shown in fig. 1, and the control method includes the following steps:
step 201: the charge pump auxiliary module outputs high level voltage to provide a driving signal for the driving module.
Step 202: the charge pump module outputs a driving voltage suitable for a thin gate oxide layer process to drive the N-type power tube.
In an implementation manner of the present application, the method further includes:
if the voltage of the signal VM is lower than the voltage of the power source VCC and the voltage of the signal COMP is at a low level, the charge pump auxiliary module controls the field-effect transistor M3 to be in an on state and controls the field-effect transistor M1 and the field-effect transistor M2 to be in an off state.
In this embodiment, the voltage of the node B is:
VB＝VCC-VDS3-VGS12；
wherein, the VBIs the voltage of node B, VCC is the voltage of power VCC, VDS3Is the voltage difference between the source and the drain of the field effect transistor M3, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12.
Optionally, the method further comprises:
if the voltage of the signal VM is higher than the voltage of the power supply VCC and the voltage of the signal COMP is at a high level, the charge pump auxiliary module controls the field-effect transistor M3 to be in a closed state, and the field-effect transistor M1 and the field-effect transistor M2 are in an open state.
In this embodiment, the voltage of the node B is:
VB＝VZ-VGS6-VGS12；
wherein, the VBIs the voltage of the node B, the VZIs the reverse breakdown voltage of Zener diode, VGS6Is the voltage difference between the gate and the source of the field effect transistor M6, the VGS12Is the voltage difference between the gate and the source of the field effect transistor M12.
In an implementation manner of the present application, when the charge pump system works normally, the voltage of the signal VM is greater than the voltage of the power VCC, and at this time, the driving voltage of the N-type power transistor is:
VGS17＝VZ+VGS6-VGS12-VDS13,14-VD+VDS17 (6)
wherein, the VGS17Is the driving voltage of the N-type power tube, VGS6Is the voltage difference between the gate and the source of the field effect transistor M6, the VDS13,14The voltage difference between drain and source of the FET M13 or the FET M14, VGS12Is the voltage difference between the gate and the source of the field effect transistor M12, VDS17The voltage difference between the drain electrode and the source electrode of the N-type power tube is obtained.
It can be seen that, in the embodiment of the present application, a driving voltage suitable for a thin gate oxide layer process can be output without using an off-chip large capacitor manner, so as to drive the N-type power transistor, which is low in cost and high in reliability.
The embodiment of the present application further provides a chip, which includes the aforementioned charge pump circuit. Alternatively, the chip may be a fast-charge chip.
An embodiment of the present application further provides an electronic device, where the electronic device includes the foregoing charge pump circuit.
The electronic device can be a mobile phone, a tablet computer, a notebook computer and other terminals, and the electronic device can also be a charging adapter and the like. Optionally, the electronic device further includes other elements, and the embodiments of the present application are not limited.
It should be noted that the above is only a preferred embodiment of the present application, but the design concept of the invention is not limited thereto, and any insubstantial modifications made to the present application by using the design concept also fall within the scope of the present application.

Claims (4)

1. A method of controlling a charge pump circuit, the method comprising:
the charge pump circuit outputs a high-level voltage so as to provide a driving signal for the driving circuit;
the charge pump circuit outputs a driving voltage suitable for a thin gate oxide layer process so as to drive an N-type power tube in the charge pump circuit.
2. The method of claim 1,
the charge pump circuit includes: the charge pump auxiliary circuit, the drive circuit, the charge pump circuit, the N-type power tube, the diode Z2 and the diode Z3;
the charge pump auxiliary circuit is connected with the drive circuit, the drive circuit is connected with the charge pump circuit, the charge pump circuit is connected with the grid electrode of the N-type power tube,
the cathode of the diode Z2 is connected between the charge pump circuit and the gate of the N-type power tube, the anode of the diode Z2 is connected with the cathode of the diode Z3, and the anode of the diode Z3 is connected with the source of the N-type power tube.
3. The charge pump circuit according to claim 2, wherein the charge pump auxiliary module comprises a fet M1, fet M2, fet M3, fet M4, fet M5, fet M6, fet M7, fet M8, fet M9, fet M10, fet M11, fet M12, diode Z1, resistor R1, resistor R2, resistor R3, inverter I1, diode D1, diode D2, and diode D3;
the drain of the field effect transistor M1 is connected to a signal VM, the drain of the field effect transistor M3 is connected to a power supply VCC, the gate of the field effect transistor M4 is connected to a signal COMP via the inverter I1, the gate of the field effect transistor M8 and the gate of the field effect transistor M9 are connected between the signal COMP and the inverter I1, the gate of the field effect transistor M1 is connected in series with the gate of the field effect transistor M2 and then connected to the drain of the field effect transistor M11, the gate of the field effect transistor M3 is connected to the drain of the field effect transistor M4, the source of the field effect transistor M4 is connected to one end of a resistor R2, the gate of the field effect transistor M6 is connected to the gate of the field effect transistor M7, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M8, the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M10, and the gate of the field effect transistor M10 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M11 is connected to the drain of the field effect transistor M9, the source of the field effect transistor M9 is connected to one end of the resistor R2 and the source of the field effect transistor M4, the other end of the resistor R2 is connected to the drain of the field effect transistor M5, the source of the field effect transistor M12 is connected to the node B, the gate and the drain of the field effect transistor M12 are connected to the drain of the field effect transistor M2 and the node a after being connected, the resistor R3 is connected in parallel between the source and the drain of the field effect transistor M11, one end of the diode Z1 is connected to the node a, and the other end of the diode Z1 is connected to the drain of the field effect transistor M6;
the diode D1 is connected in parallel to the FET M1, the diode D2 is connected in parallel to the FET M3, and the diode D3 is connected in parallel to the FET M2;
the diode D1, the diode D2 and the diode D3 are all independent diodes or anti-parallel diodes carried in the field effect tube.
4. The method according to claim 1, 2 or 3,
the method further comprises the following steps: if the voltage of the signal VM is lower than the voltage of the power supply VCC and the voltage of the signal COMP is at a low level, the charge pump auxiliary module controls the field-effect transistor M3 to be in an on state and controls the field-effect transistor M1 and the field-effect transistor M2 to be in an off state;
if the voltage of the signal VM is higher than the voltage of the power supply VCC and the voltage of the signal COMP is at a high level, the charge pump auxiliary module controls the field-effect transistor M3 to be in a closed state, and the field-effect transistor M1 and the field-effect transistor M2 are in an open state.
CN202110224520.0A 2020-09-24 2020-09-24 Control method of charge pump circuit applicable to thin gate oxide layer process Pending CN114257082A (en)

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US6028780A (en) * 1998-03-12 2000-02-22 Eon Silicon Devices, Inc. Two-phase clock charge pump with power regulation
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CN105576967B (en) * 2014-10-11 2018-07-24 中芯国际集成电路制造(上海)有限公司 Voltage up converting circuit
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