CN114256376B - Avalanche photodetector and preparation method thereof - Google Patents
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Avalanche photodetectors and methods of making are provided. The detector comprises: a substrate, a surface of which includes a first semiconductor layer; a second semiconductor layer on the substrate, the first semiconductor layer including a first, a second, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type and a first N-type doped region sequentially arranged in a first direction, the concentrations of the first to third P-type and the first to third N-type doped regions decreasing sequentially, the first intrinsic region, the third N-type doped region, a portion of the second P-type doped region adjacent to the third N-type, a portion of the third P-type doped region adjacent to the first intrinsic region having a first height H in a vertical direction 1 Is not equal to the second height H of other areas of the layer 2 The method comprises the steps of carrying out a first treatment on the surface of the The second semiconductor layer sequentially covers H of the second P-type doped region along the first direction 2 H of the second P-type doped region 1 H of the third N-type doped region, the first intrinsic region and the third P-type doped region 1 And H of the third P-type doped region 2 Is a part of the same.
Description
Technical Field
The invention relates to the technical field of photon integrated chip detection, in particular to an avalanche photodetector and a preparation method thereof.
Background
The avalanche photodetector is used as one of the core devices of the silicon photon architecture, has the function of converting low-power optical signals into electric signals, and has the working principle that photon-generated carriers (hole electron pairs) generated by photoelectric effect are rapidly accelerated when moving in a high electric field area, one or more collisions possibly occur in the moving process, and secondary and tertiary new hole electron pairs are generated by collision ionization effect to generate avalanche multiplication effect, so that the number of carriers is rapidly increased, and a relatively large optical signal current is formed.
At present, a germanium-silicon material compatible with a CMOS process is widely adopted in a silicon photon integrated chip to realize avalanche photoelectric detection, wherein the silicon material is used as an optical waveguide and also used as an avalanche gain region (also called a multiplication region), and the germanium material absorbs photons. The defects of the existing germanium-silicon avalanche photodetector structure are as follows: firstly, an epitaxial monocrystalline silicon process is needed, and the manufacture is relatively complex; secondly, the absorption region is usually doped by P or N type, and the doping can cause light absorption loss, so that the quantum efficiency of the detector is reduced; and thirdly, the absorption region and the multiplication region are not easy to adjust independently, the concentration precision of the doped region is too high, the process tolerance is low, and the gain bandwidth is easy to be unsatisfactory. Thus avalanche photodetectors employing silicon germanium materials are in need of further improvement.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides an avalanche photodetector and a method for manufacturing the same, which solve at least one of the problems in the background art.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
in one aspect, an embodiment of the present invention provides an avalanche photodetector, including:
a substrate, a surface of which includes a first semiconductor layer;
a second semiconductor layer located over the first semiconductor layer, the second semiconductor layer having a material different from a material of the first semiconductor layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first semiconductor layer comprises a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged in a first direction, the dopant concentrations of the first P-type doped region, the second P-type doped region and the third P-type doped region are sequentially decreased, the dopant concentrations of the first N-type doped region, the second N-type doped region and the third N-type doped region are sequentially decreased, and the first direction is the electron flow direction of the avalanche photodetector;
And wherein the first intrinsic region, the third N-type doped region, a portion of the second P-type doped region immediately adjacent to the third N-type doped region, a portion of the third P-type doped region immediately adjacent to the first intrinsic region in the first semiconductor layer have a first height H in a direction perpendicular to the substrate 1 Other regions in the first semiconductor layer have a second height H 2 ；H 1 Not equal to H 2 ；
The second semiconductor layer sequentially covers the second P-type doped region along the first direction and has the second height H 2 The second P-type doped region having the first height H 1 The third N-type doped region, the first intrinsic region and the third P-type doped region have the first height H 1 The third P-type doped region having the second height H 2 Is a part of the area of (2);
the first N-type doped region is connected with a first electrode; the third P-type doped region is connected with a second electrode; the first P-type doped region is connected with a third electrode.
In the above scheme, H 1 Greater than H 2 。
In the above scheme, H 1 Less than H 2 。
In the above scheme, a first reverse bias voltage V is arranged between the first electrode and the third electrode 1 And a second reverse bias voltage V is arranged between the first electrode and the second electrode 2 。
In the above scheme, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, a germanium-silicon alloy, a III-V material, and an alloy thereof.
In the above scheme, the dopant concentration of the first P-type doped region or the first N-type doped region is 1×10 20 /cm 3 ～5×10 20 /cm 3 The second P-type doped region or the second P-type doped regionThe dopant concentration of the second N-type doped region is 2×10 17 /cm 3 ～5×10 18 /cm 3 The dopant concentration of the third P-type doped region or the third N-type doped region is 1.2X10 17 ～4×10 17 /cm 3 。
In the above scheme, the second intrinsic region has a size of 50nm to 800nm in the first direction.
In the above aspect, the second semiconductor layer has a dimension in the first direction of 150nm to 1500nm, a dimension in the second direction of 1 μm to 100 μm, and a dimension in the third direction of 150nm to 600nm, wherein the third direction is a direction perpendicular to the substrate, and the second direction is perpendicular to the third direction and to the first direction.
The embodiment of the invention also provides a preparation method of the avalanche photodetector, which comprises the following steps:
providing a substrate, wherein the surface of the substrate comprises a first semiconductor layer;
Performing a selective doping process to form a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged along a first direction on the first semiconductor layer, wherein the dopant concentrations of the first P-type doped region, the second P-type doped region and the third P-type doped region are sequentially decreased, and the dopant concentrations of the first N-type doped region, the second N-type doped region and the third N-type doped region are sequentially decreased; before the selective doping process is performed, forming a height which is different from other regions in the first semiconductor layer in a direction perpendicular to the substrate in a region in which the partial region of the second P-type doped region, the partial region of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed;
forming a second semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer, and part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region are sequentially covered in the first direction;
Forming a first electrode, a second electrode and a third electrode which are arranged in the direction perpendicular to the plane of the substrate, wherein the first electrode is electrically connected with the first N-type doped region; the second electrode is electrically connected with the third P-type doped region, and the third electrode is electrically connected with the first P-type doped region;
the first direction is an electron flow direction of the avalanche photodetector.
In the above solution, before the performing the selective doping process, forming a height different from that of other regions in the first semiconductor layer in a direction perpendicular to the substrate in the region where the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region are to be formed includes:
a height H formed in a direction perpendicular to the substrate in a region where the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region are to be formed 1 Height H greater than other regions in the first semiconductor layer 2 。
In the above solution, before the performing the selective doping process, forming a height different from that of other regions in the first semiconductor layer in a direction perpendicular to the substrate in the region where the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region are to be formed includes:
A height H formed in a direction perpendicular to the substrate in a region where the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region are to be formed 1 Height H less than other regions in the first semiconductor layer 2 。
In the above scheme, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, a germanium-silicon alloy, a III-V material, and an alloy thereof.
In the above scheme, the dopant concentration of the first P-type doped region or the first N-type doped region is 1×10 20 /cm 3 ～5×10 20 /cm 3 The dopant concentration of the second P-type doped region or the second N-type doped region is 2×10 17 /cm 3 ～5×10 18 /cm 3 The dopant concentration of the third P-type doped region or the third N-type doped region is 1.2X10 17 ～4×10 17 /cm 3 。
In the above aspect, the forming the first electrode, the second electrode, and the third electrode disposed perpendicular to the planar direction of the substrate includes:
forming a cover layer covering the first semiconductor layer and the second semiconductor layer;
forming a first window, a second window and a third window at one end of the first N-type doped region, the third P-type doped region and the first P-type doped region along the second direction respectively so as to expose partial surfaces of the first P-type doped region, the third P-type doped region and the first N-type doped region;
And filling metal in the first window, the second window and the third window to form the first electrode, the second electrode and the third electrode.
The avalanche photodetector provided by the embodiment of the invention comprises the following components: a substrate, a surface of which includes a first semiconductor layer; a second semiconductor layer located over the first semiconductor layer, the second semiconductor layer having a material different from a material of the first semiconductor layer; the first semiconductor layer comprises a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged in a first direction, wherein the dopant concentrations of the first to third P-type doped regions are sequentially decreased, the dopant concentrations of the first to third N-type doped regions are sequentially decreased, and the first direction is the electron flow direction of the avalanche photodetector; and wherein the first intrinsic region, the firstThe three N-type doped regions, the portion of the second P-type doped region immediately adjacent to the third N-type doped region, and the portion of the third P-type doped region immediately adjacent to the first intrinsic region have a first height H in a direction perpendicular to the substrate 1 Other regions in the first semiconductor layer have a second height H 2 ；H 1 Not equal to H 2 The method comprises the steps of carrying out a first treatment on the surface of the The second semiconductor layer sequentially covers the second height H of the second P-type doped region along the first direction 2 A first height H of the second P-type doped region 1 A first height H of the third N-type doped region, the first intrinsic region and the third P-type doped region 1 And a second height H of the third P-type doped region 2 The first N-type doped region is connected with a first electrode; the third P-type doped region is connected with a second electrode; the first P-type doped region is connected with a third electrode. Because the doped charge regions and the second intrinsic region serving as the avalanche region are both in the first semiconductor layer, the single crystal silicon does not need to be manufactured by additional epitaxy, the manufacture is relatively simple, and the cost is reduced; in addition, since part of the second P-type doped region, part of the third P-type doped region, the first intrinsic region and the third N-type doped region have different heights in the direction perpendicular to the substrate from other regions in the first semiconductor layer, the second semiconductor layer sequentially covers the second height H of the second P-type doped region along the first direction 2 A first height H of the second P-type doped region 1 A third N-type doped region, a first intrinsic region, and a first height H of a third P-type doped region 1 Second height H of the region of the third P-type doped region 2 Therefore, the second semiconductor layer, the second P-type doped region and the third P-type doped region have larger contact areas, and the transmission efficiency of electrons participating in the avalanche effect can be improved. Finally, since the first N-type doped region is connected with the first electrode, the third P-type doped region is connected with the second electrode, and the first P-type doped region is connected with the third electrode, the bias voltage can be independently applied to the three electrodes, so that the second semiconductor layer serving as the absorption region and the second semiconductor layer serving as snow can be formedThe electric field of the second intrinsic region of the collapse region can be independently regulated, the tolerance to the concentration precision of the doped region is good, and the realization of low noise and high gain bandwidth is facilitated.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is an isometric view of an avalanche photodetector according to an embodiment of the present invention;
FIG. 2 is a schematic top view of an avalanche photodetector according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an avalanche photodetector along a Y direction according to an embodiment of the present invention;
FIG. 4 is an isometric view of yet another avalanche photodetector provided in an embodiment of the present invention;
FIG. 5 is a schematic top view of yet another avalanche photodetector provided in an embodiment of the present invention;
FIG. 6 is a schematic view of an avalanche photodetector along the Y direction according to another embodiment of the present invention;
fig. 7 is a schematic flow chart of a method for manufacturing an avalanche photodetector according to an embodiment of the present invention;
fig. 8a to 8e are cross-sectional views of a device structure in a process of manufacturing an avalanche photodetector according to an embodiment of the present invention.
Detailed Description
In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the technical scheme of the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments of the present invention.
In embodiments of the present invention, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
In embodiments of the present invention, unless explicitly specified and limited otherwise, the "upper" or "lower" relationship between two layers in a semiconductor structure may be either direct contact between the two layers or indirect contact between the two layers through intervening layers.
In embodiments of the present invention, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. Also, a layer may include a plurality of sub-layers.
Spatially relative terms, such as "under", "below", "lower", "above", "upper", "upward", "downward", and the like, may be used herein for ease of description in embodiments of the present invention to describe one element or feature's relationship to another element(s) or feature(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Silicon photonics is a new generation of technology for optical device development and integration using existing Complementary Metal Oxide Semiconductor (CMOS) processes based on silicon and silicon-based substrate materials (e.g., siGe/Si, silicon-on-insulator, etc.). The silicon photon technology combines the characteristics of ultra-large scale and ultra-high precision manufacture of integrated circuit technology and the advantages of ultra-high speed and ultra-low power consumption of photon technology, and is a subversion technology for coping with the failure of moore's law. Such a combination benefits from the scalability of semiconductor wafer fabrication, and thus can reduce costs. The photoelectric detector is used as one of core devices of a silicon photon architecture and has the function of converting optical signals into electric signals. The defects of the existing germanium-silicon avalanche photodetector structure are as follows: firstly, an epitaxial monocrystalline silicon process is needed, and the manufacture is relatively complex; secondly, the absorption region is usually doped by P or N type, and the doping can cause light absorption loss, so that the quantum efficiency of the detector is reduced; and thirdly, the absorption region and the avalanche region (also called multiplication region) are not easy to adjust independently, the concentration precision of the doped region is too high, the process tolerance is low, and the gain bandwidth is easy to be non-ideal.
Based on this, the following technical solutions of the embodiments of the present application are proposed.
The embodiment of the invention provides an avalanche photodetector, which comprises the following components:
a substrate, a surface of which includes a first semiconductor layer;
a second semiconductor layer located over the first semiconductor layer, the second semiconductor layer having a material different from a material of the first semiconductor layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first semiconductor layer comprises a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged in a first direction, the dopant concentrations of the first to third P-type doped regions are sequentially decreased, the dopant concentrations of the first to third N-type doped regions are sequentially decreased, and the first direction is the electron flow direction of the avalanche photodetector;
and wherein the first intrinsic region, the third N-type doped region, the portion of the second P-type doped region immediately adjacent to the third N-type doped region, the portion of the third P-type doped region immediately adjacent to the first intrinsic region, in the direction perpendicular to the substrate, have a first height H 1 Other regions in the first semiconductor layer have a second height H 2 ；H 1 Not equal to H 2 ；
The second semiconductor layer sequentially covers the second height H of the second P-type doped region along the first direction 2 A first height H of the second P-type doped region 1 A first height H of the third N-type doped region, the first intrinsic region and the third P-type doped region 1 And a second height H of the third P-type doped region 2 Is a part of the area of (2);
the first N-type doped region is connected with a first electrode; the third P-type doped region is connected with a second electrode; the first P-type doped region is connected with a third electrode.
In some embodiments, a portion of the second P-type doped region, a portion of the third P-type doped region, the first intrinsic region, and the third N-type doped region in the first semiconductor layer have a height H in a direction perpendicular to the substrate 1 Height H greater than other regions in the first semiconductor layer 2 。
In this case, please refer to fig. 1 to 3, wherein fig. 1 is an isometric view of an avalanche photodetector according to an embodiment of the present invention; FIG. 2 is a schematic top view of an avalanche photodetector according to an embodiment of the present invention; fig. 3 is a schematic diagram of an avalanche photodetector along a Y direction according to an embodiment of the present invention.
In other embodiments, a portion of the second P-type doped region, a portion of the third P-type doped region, the first intrinsic region, and the third N-type doped region in the first semiconductor layer have a height H in a direction perpendicular to the substrate 1 A height H smaller than other regions in the first semiconductor layer 2 。
In this case, please refer to fig. 4 to fig. 6 in particular, wherein fig. 4 is an isometric view of another avalanche photodetector according to an embodiment of the present invention; FIG. 5 is a schematic top view of another avalanche photodetector according to an embodiment of the present invention; fig. 6 is a schematic diagram of another avalanche photodetector according to an embodiment of the present invention along the Y direction.
Hereinafter, the structure of an avalanche photodetector will be described by taking a first type of avalanche photodetector as an example and referring to fig. 1 to 3, the avalanche photodetector comprising:
a substrate 10 including a first semiconductor layer 300; an avalanche region of the avalanche photodetector is formed in the first semiconductor layer 300 to achieve an avalanche effect;
the second semiconductor layer 400 is made of a material different from that of the first semiconductor layer 300.
Here, the substrate may be a multi-layered structure in which a first semiconductor layer is on top of the substrate, and an insulating layer composed of an elemental semiconductor material (e.g., silicon (Si), germanium (Ge), etc.), a composite semiconductor material (e.g., silicon germanium (SiGe), etc.), and an oxide thereof may be included under the substrate. In this example, the substrate 10 may be silicon-on-insulator (SOI) or germanium-on-insulator (GeOI), or the like.
The embodiments of the present application will be described with reference to SOI as an example of a layer below the surface of the substrate. It is understood that the first semiconductor layer 300 is positioned on top of the inventive substrate 10.
In some embodiments, the material of the first semiconductor layer 300 includes silicon. The layers under the first semiconductor layer 300 sequentially include the insulating layer 200 and the underlying layer 100.
In practical applications, the bottom layer 100 may be a silicon wafer, or may be a wafer formed of other materials. The material of the bottom layer 100 may be silicon, germanium, or sapphire, etc.
In some embodiments, the material of the bottom layer 100 is silicon, and correspondingly, the material of the insulating layer 200 may be an oxide of silicon, such as silicon dioxide
The underlayer 100 may have a thicker thickness than the first semiconductor layer 300. It should be understood that, in order to clearly show each layer structure in the drawings, dimensional proportion relation of each layer structure may be different from that of the actual structure.
It should be noted that, for convenience of description, as shown in fig. 1, the embodiment of the present invention is described by means of a first direction (X), a second direction (Y), and a third direction (Z) (see fig. 1).
Here, the substrate 10 may include a top surface at the front surface and a bottom surface at the back surface opposite to the front surface; the direction perpendicular to the top and bottom surfaces of the substrate is defined as the third direction (Z) with the flatness of the top and bottom surfaces ignored. The third direction Z is also the stacking direction of the subsequent deposition of the various layer structures on the substrate, or the height direction of the device. The plane on which the top surface and the bottom surface of the substrate are located, or strictly speaking, the center plane in the thickness direction of the substrate is defined as the substrate plane. Two first directions (X) and second directions (Y) intersecting each other (e.g., perpendicular to each other) are defined in the substrate plane direction. In this embodiment, the first direction X is an electron flow direction; the second direction Y is the propagation direction of the optical signal.
Since, in theory, any semiconductor material may be used as the material of the first semiconductor layer 300 in the avalanche photodetector, the material of the first semiconductor layer 300 is not strictly limited here. In embodiments where the substrate 10 includes a bottom layer 100 of elemental Si, the material of the first semiconductor layer 300 is Si.
In order for the avalanche photodetector to achieve the avalanche effect, the different regions of the first semiconductor layer 300 of the avalanche photodetector are formed with different doped regions, including doped P-type dopants, N-type dopants, and undoped regions (intrinsic regions).
The structure of the first semiconductor layer 300 of the avalanche photodetector according to the embodiment of the present disclosure will be described in detail below. In some embodiments, the first semiconductor layer 300 in the avalanche photodetector includes a first P-type doped region 301, a second P-type doped region 302, a third N-type doped region 303, a first intrinsic region 304, a third P-type doped region 305, a second intrinsic region 306, a second N-type doped region 307, and a first N-type doped region 308, which are sequentially arranged in the first direction X. The P-type doping agent concentration of the first P-type doping region, the second P-type doping region and the third P-type doping region is gradually decreased, and the N-type doping agent concentration of the first N-type doping region, the second N-type doping region and the third N-type doping region is gradually decreased.
In some embodiments, the P-type dopant may be boron (B), and the N-type dopant may be phosphorus (P) or arsenic (As).
In some embodiments, the dopant concentration of the first P-type doped region 301 or the first N-type doped region 308 is 1×10 20 /cm 3 ～5×10 20 /cm 3 The dopant concentration of the second P-type doped region 302 or the second N-type doped region 307 is 2×10 17 /cm 3 ～5×10 18 /cm 3 The dopant concentration of the third P-type doped region 305 or the third N-type doped region 303 is 1.2x10 17 ～4×10 17 /cm 3 。
In practical applications, since the intrinsic region is undoped or lightly doped, its concentration is generally less than a predetermined value, e.g.,less than 1X 10 17 /cm 3 。
The dopant concentrations of the first P-type doped region and the first N-type doped region may be the same or different, so long as their dopant concentrations are within the above-described ranges.
Similarly, the dopant concentrations of the second P-type doped region and the second N-type doped region, and the third P-type doped region and the third N-type doped region, respectively, may be the same or different.
For the intrinsic region, it may be an undoped or lightly doped first semiconductor layer. Wherein the intrinsic region is the region where impact ionization specifically occurs to generate electron-hole pairs.
In the first semiconductor layer 300 in the avalanche photodetector of the present invention, the avalanche region may be the second intrinsic region 306.
It should be appreciated that avalanche photodetectors are based on the application of a voltage between avalanche regions, creating an electric field, whereby photo-generated carriers are extracted by the electric field to form an electric current. Specifically, bias voltages are applied to two sides of the avalanche region along the first direction, so that photoelectric detection is realized.
In some embodiments of the present invention, referring to fig. 1 and 3, a portion of the second P-type doped region 302, a portion of the third P-type doped region 305, the first intrinsic region 304, and a height H of the third N-type doped region 303 in a direction perpendicular to the substrate (Z direction) in the first semiconductor layer 300 1 Height H greater than other regions in the first semiconductor layer 2 。
It will be appreciated that portions of the second P-type doped region 302, portions of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 are raised relative to other regions in the first semiconductor layer. From the view point of the Y direction, part of the second P-type doped region 302, part of the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 are in an inverted U shape.
In other embodiments of the present invention, referring to fig. 4 and 6, a portion of the second P-type doped region 302-1, a portion of the third P-type doped region 305-1, the first intrinsic region 304-1, and the third N-type doped region 303-1 in the first semiconductor layer 300-1 are perpendicular to the substrate Height H in the direction (Z direction) 1 Less than the height H of other regions in the first semiconductor layer 300-1 2 。
It will be appreciated that portions of the second P-type doped region 302-1, portions of the third P-type doped region 305-1, the first intrinsic region 304-1, and the third N-type doped region 303-1 are recessed relative to other regions in the first semiconductor layer 300-1. From the view point of the Y direction, part of the second P-type doped region 302-1, part of the third P-type doped region 305-1, the first intrinsic region 304-1, and the third N-type doped region 303-1 are U-shaped.
In an embodiment of the present invention, the first semiconductor layer 300 includes a second semiconductor layer 400 thereon, and the material of the second semiconductor layer 400 is different from that of the first semiconductor layer.
In some embodiments, the material of the first semiconductor layer 300 is silicon and the material of the second semiconductor layer 400 is germanium, a germanium-silicon alloy, a group III-V material, and alloys thereof.
In a further embodiment, the material of the first semiconductor layer 300 is silicon and the material of the second semiconductor layer is germanium. The avalanche photodetector thus formed is a silicon germanium photodetector.
Here, since the second semiconductor layer 400 as the absorption region in the avalanche photodetector provided by the present invention is not doped with P or N type and does not involve ohmic contact, light absorption loss can be reduced as much as possible, which is advantageous in improving quantum absorption efficiency.
In some embodiments, referring to fig. 1 and 3, the second semiconductor layer 400 of the avalanche photodetector of the present invention sequentially covers a portion of the second P-type doped region 302, the third N-type doped region 303, the first intrinsic region 304, and a portion of the third P-type doped region 305 along the first direction X, and the portion of the second P-type doped region 302, a portion of the third P-type doped region 305, the first intrinsic region 304, and a portion of the third N-type doped region 303 in the first semiconductor layer 300 have a height H in the direction perpendicular to the substrate (Z direction) 1 Height H greater than other regions in the first semiconductor layer 2 In the case of (a), the second semiconductor layer 400 is in spatial and complementary relation to them. The second semiconductor layer 400 is formed as an absorption region of the avalanche photodetector.
In some embodiments, referring to fig. 4 and 6, the second semiconductor layer 400-1 of the avalanche photodetector of the present embodiment sequentially covers a portion of the second P-type doped region 302-1, the third N-type doped region 303-1, the first intrinsic region 304-1, and a portion of the third P-type doped region 305-1 along the first direction X, and the height H of the portion of the second P-type doped region 302-1, the portion of the third P-type doped region 305-1, the first intrinsic region 304-1, and the third N-type doped region 303-1 in the first semiconductor layer 300-1 in the direction perpendicular to the substrate (Z direction) 1 Less than the height H of other regions in the first semiconductor layer 300-1 2 The second semiconductor layer 400-1 is in spatial and complementary relation to them. The second semiconductor layer 400-1 is formed as an absorption region of an avalanche photodetector.
In the above two cases, since part of the second P-type doped region, part of the third P-type doped region, the first intrinsic region, and the third N-type doped region have different heights in the direction perpendicular to the substrate from other regions in the first semiconductor layer, and the second semiconductor layer sequentially covers the second height H of the second P-type doped region along the first direction 2 A first height H of the second P-type doped region 1 A third N-type doped region, a first intrinsic region, and a first height H of a third P-type doped region 1 Second height H of the region of the third P-type doped region 2 Therefore, the second semiconductor layer, the second P-type doped region and the third P-type doped region have larger contact areas, and the transmission efficiency of electrons participating in the avalanche effect can be improved.
Taking one of the avalanche photodetectors as an example, referring to fig. 1 to 3, when an optical signal is applied in the Y direction of the avalanche photodetector, the second semiconductor layer 400 absorbs photons in the optical signal. The photoelectric effect proposed by einstein is known to be that one photon generates one photogenerated electron. Accordingly, the second semiconductor layer 400 absorbs photons and generates electrons, i.e., photo-generated electrons.
With continued reference to fig. 1-3, the second semiconductor layer 400 covers a portion of the second P-type doped region 302 and a portion of the third P-type doped region 305, thereby bridging the second P-type doped region 302 and the third P-type doped region 305 to form a carrier path. The photo-generated electrons can move from the second P-type doped region 302 to the third P-type doped region 305 under the action of the electric field.
With continued reference to fig. 1-3, the avalanche photodetector of the present embodiment further includes a first electrode 501, a second electrode 502, and a third electrode 503. The first electrode 501 is electrically connected to the first N-type doped region 308; the second electrode 502 is electrically connected to the third P-type doped region 305, and the third electrode 503 is electrically connected to the first P-type doped region 301.
The first electrode 501, the second electrode 502, and the third electrode 503 electrically connected to the first N-type doped region 308, the third P-type doped region 305, and the first P-type doped region 301 can be formed by providing a first bias voltage V between the first electrode 501 and the third electrode 503 1 Thereby providing a first bias voltage V between the first N-type doped region 308 and the first P-type doped region 301 1 While by providing a second bias voltage V between the first electrode 501 and the second electrode 502 2 Thereby providing an applied second bias voltage V between the first N-type doped region 308 and the third P-type doped region 305 2 。
As described above, the second semiconductor layer 400 as an absorption region connects the second P-type doped region 302 and the third P-type doped region 305 to form a path of carriers. Thus, by applying an electric field between the first N-type doped region 308 and the first P-type doped region 301 (i.e., by a first bias voltage V 1 ) In this case, the energy of the photo-generated electrons can be adjusted.
While for providing a second bias voltage V between the third P-type doped region 305 and the first N-type doped region 308 2 Since it is located at both ends of the second intrinsic region 306, the second intrinsic region 306 functions as an avalanche region, and thus the second bias voltage V 2 The electric field distribution of the avalanche region can be regulated. The avalanche region of an avalanche photodetector refers to a region where carrier (here, electron) multiplication occurs, and thus may also be referred to as a multiplication region. The absorption region of the avalanche photodetector is capable of converting an incident optical signal into a plurality of electrons, and the electrons flow under the action of an electric field to form photocurrent; the avalanche region can absorb by the avalanche effectA small amount of electrons formed in the collecting region are further excited to form a large amount of electrons so as to realize the amplifying effect; and finally, conducting photocurrent through a pair of metal electrodes to realize photoelectric detection.
The photo-generated electrons are generated in the presence of an electric field (due to a first bias voltage V applied to the avalanche photodetector 1 ) These photo-generated electrons are accelerated to the second intrinsic region 306 for multiplication. As the photogenerated electrons pass through the second intrinsic region 306, they collide with other carriers incorporated in the semiconductor atomic lattice, thereby generating more free carriers through a process known as "impact ionization". These new free carriers are also accelerated by the applied electric field and generate more free carriers.
In addition, the arrangement of the three regions of the third N-type doped region 303, the first intrinsic region 304, and the third P-type doped region 305, and the concentration ranges of the respective dopants of the third N-type doped region 303 and the third P-type doped region 305 of the avalanche photodetector according to the embodiment of the present invention are advantageous for the electric field distribution in the second semiconductor layer 400 as the absorption region. Due to the presence of the first intrinsic region 304, even at a first bias voltage V 1 Electrons cannot pass through the first intrinsic region 304, and the first intrinsic region 304 plays a role of blocking. Electrons from the second P-type doped region 302 may pass through the third N-type doped region 303, through the second semiconductor layer 400, and then through the third P-type doped region 305 to the avalanche region.
In order to achieve the above avalanche effect, the existing avalanche photodetector only applies bias voltages at two ends of an avalanche region, which has some disadvantages, for example, the absorption region and the avalanche region (also called multiplication region) are not easy to be independently adjusted, the concentration precision of the doped region is too high, the process tolerance is low, and the gain bandwidth is easy to be non-ideal. For this purpose, the invention sets a bias voltage at both ends of the absorption region and the avalanche region of the avalanche photodetector, i.e. a first bias voltage V is provided between the first P-type doped region 301 and the first N-type doped region 308 1 And a second bias voltage V is provided between the first N-type doped region 308 and the third P-type doped region 305 2 . Thereby, the absorption region and avalanche region pair is realizedIndependent adjustment of the applied electric field and further increases the gain bandwidth.
The first bias voltage V 1 And the bias voltage V 2 Is relatively independent, a first bias voltage V 1 Acts on the absorption zone and can have a value of 1 to 4 volts. And a second bias voltage V 2 The avalanche region is acted upon and may have a value of 3 to 20 volts.
In some embodiments, the second intrinsic region 306 has a dimension in the first direction X of 50nm to 800nm, that is to say the width of the second intrinsic region 306 is within the above-mentioned interval. Thereby, a large bandwidth is realized while realizing a higher gain. Since the second intrinsic region 306 is the avalanche region of the avalanche photodetector of the embodiment of the present invention, the second intrinsic region 306 is not necessarily too small in the first direction X. For example, when the wavelength is less than 50nm, electrons moving from the absorption region have insufficient avalanche space, cannot be absorbed effectively, and the multiplication effect is poor. The size of the electron detector is not too large, otherwise, the voltage requirements on the two ends of the avalanche region are too high, the time for electron avalanche is too long, the response is reduced, and the detection effect is affected.
In some embodiments, the second semiconductor layer 400 has a dimension in the first direction X of 150nm to 1500nm, a dimension in the second direction Y of 1 μm to 100 μm, and a dimension in the third direction Z of 150nm to 600nm. The size of the second semiconductor layer in the embodiment of the invention is limited in the above range, and the generation of dark current can be reduced while noise can be reduced.
Here, in describing the size of the second semiconductor layer, the difference in size of the upper and lower surfaces of the second semiconductor layer during epitaxial growth may not be taken into consideration.
It should be noted that the second semiconductor layer 400 may be regular rectangular in shape parallel to the substrate 10, see fig. 1 and 2 and fig. 4 and 5. It is also possible to have a trapezoid with a chamfer of a certain size along said first direction X.
The avalanche photodetector of the present invention may further comprise a cover layer 600 (see fig. 8 e) covering said first semiconductor layer 300, second semiconductor layer 400, first electrode 501, second electrode 502 and third electrode 503.
It should be noted that, the structure of the avalanche photodetector of the present invention may also be a mirror image structure of itself, for example, referring to fig. 3, the first direction X of the mirror image structure is from right to left in the embodiment of the present invention. Therefore, the avalanche photodetector and the mirror image structure thereof provided by the embodiment of the invention are all within the protection scope of the invention.
The avalanche photodetector provided by the embodiment of the invention comprises the following components: a substrate, a surface of which includes a first semiconductor layer; a second semiconductor layer located over the first semiconductor layer, the second semiconductor layer having a material different from a material of the first semiconductor layer; the first semiconductor layer comprises a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged in a first direction, wherein the dopant concentrations of the first to third P-type doped regions are sequentially decreased, the dopant concentrations of the first to third N-type doped regions are sequentially decreased, and the first direction is the electron flow direction of the avalanche photodetector; and wherein the first intrinsic region, the third N-type doped region, the portion of the second P-type doped region immediately adjacent to the third N-type doped region, the portion of the third P-type doped region immediately adjacent to the first intrinsic region, in the direction perpendicular to the substrate, have a first height H 1 Other regions in the first semiconductor layer have a second height H 2 ；H 1 Not equal to H 2 The method comprises the steps of carrying out a first treatment on the surface of the The second semiconductor layer sequentially covers the second height H of the second P-type doped region along the first direction 2 A first height H of the second P-type doped region 1 A first height H of the third N-type doped region, the first intrinsic region and the third P-type doped region 1 And a second height H of the third P-type doped region 2 The first N-type doped region is connected with a first electrode; the third P-type doped region is connected with a second electrode; the saidThe first P-type doped region is connected with a third electrode. Because the doped charge regions and the second intrinsic region serving as the avalanche region are both in the first semiconductor layer, the single crystal silicon does not need to be manufactured by additional epitaxy, the manufacture is relatively simple, and the cost is reduced; in addition, since part of the second P-type doped region, part of the third P-type doped region, the first intrinsic region and the third N-type doped region have different heights in the direction perpendicular to the substrate from other regions in the first semiconductor layer, the second semiconductor layer sequentially covers the second height H of the second P-type doped region along the first direction 2 A first height H of the second P-type doped region 1 A third N-type doped region, a first intrinsic region, and a first height H of a third P-type doped region 1 Second height H of the region of the third P-type doped region 2 Therefore, the second semiconductor layer, the second P-type doped region and the third P-type doped region have larger contact areas, and the transmission efficiency of electrons participating in the avalanche effect can be improved. Finally, as the first N-type doped region is connected with the first electrode, the third P-type doped region is connected with the second electrode, and the first P-type doped region is connected with the third electrode, bias voltages can be independently applied to the three electrodes later, so that electric fields of the second semiconductor layer serving as an absorption region and the second intrinsic region serving as an avalanche region can be independently regulated, the tolerance on the concentration precision of the doped region is good, and low noise and high gain bandwidth can be realized.
The embodiment of the invention also provides a preparation method of the avalanche photodetector; referring specifically to fig. 7. As shown, the method comprises the steps of:
step 201: providing a substrate, wherein the surface of the substrate comprises a first semiconductor layer;
step 202: performing a selective doping process to form a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region, which are sequentially arranged along a first direction, on the first semiconductor layer; before the selective doping process is executed, forming a height which is different from other areas in the first semiconductor layer in the direction vertical to the substrate in the partial area of the second P type doped area, the partial area of the third P type doped area, the first intrinsic area and the area of the third N type doped area to be formed;
Step 203: forming a second semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer, and part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region are sequentially covered in the first direction;
step 204: forming a first electrode, a second electrode and a third electrode which are arranged in the direction perpendicular to the plane of the substrate, wherein the first electrode is electrically connected with the first N-type doped region; the second electrode is electrically connected with the third P-type doped region, and the third electrode is electrically connected with the first P-type doped region.
The first direction is an electron flow direction of the avalanche photodetector.
Next, the avalanche photodetector and the method for manufacturing the same according to the embodiments of the present invention will be described in further detail with reference to cross-sectional views of device structures during the manufacturing process of the avalanche photodetector in fig. 8a to 8 e.
Here, since the part of the second P-type doped region, the part of the third P-type doped region, the first intrinsic region and the third N-type doped region in the first semiconductor layer of the two avalanche photodetectors have different heights in the direction perpendicular to the substrate from the other regions in the first semiconductor layer, correspondingly, the heights of the second semiconductor layer covering the part of the second P-type doped region, the part of the third P-type doped region, the first intrinsic region and the third N-type doped region are correspondingly different, and other parts of the two avalanche photodetectors are identical, the heights H of the part of the second P-type doped region, the part of the third P-type doped region, the first intrinsic region and the third N-type doped region in the direction perpendicular to the substrate will be representatively used herein 1 Height H greater than other regions in the first semiconductor layer 2 To illustrate the snow provided by the embodiment of the inventionA preparation method of a photoelectric detector is provided.
First, step 201 is performed. A substrate is provided that includes a first semiconductor layer.
Referring to fig. 8a, a substrate 10 is provided; the substrate 10 may comprise a multi-layer structure upon which the functional layer is further grown. Accordingly, the substrate 10 of the present invention may include a multi-layered structure in which the surface of the substrate 10 includes the first semiconductor layer 300, and the layer located under the surface may include an insulating layer composed of an elemental semiconductor material (e.g., silicon (Si), germanium (Ge), etc.), a composite semiconductor material (e.g., silicon germanium (SiGe), etc.), and an oxide thereof, and thus, the substrate 10 may be either silicon-on-insulator (SOI) or germanium-on-insulator (GeOI), etc.
The embodiment of the present application will be described with reference to the substrate 10 being SOI. It is understood that the first semiconductor layer 300 is located on the surface of the substrate 10 of the present invention.
The substrate 10 further comprises an intermediate layer 200 (which may be an insulating layer in practical use) and a bottom layer 100 (which may be a silicon layer in practical use) under the first semiconductor layer 300. The insulating layer 200 is, for example, a silicon dioxide layer, which can be obtained directly by thermal oxidation of the underlayer 100. The bottom layer 100 may have a thicker thickness than the first semiconductor layer 300.
Next, step 202 is performed. Here, refer to fig. 8b. A selective doping process is performed to form a first P-type doped region 301, a second P-type doped region 302, a third N-type doped region 303, a first intrinsic region 304, a third P-type doped region 305, a second intrinsic region 306, a second N-type doped region 307, and a first N-type doped region 308, which are sequentially arranged in the first direction, on the first semiconductor layer 300.
In the actual process, a mask photoetching process can be utilized to sequentially window the region needing doping. Ion implantation is then performed in the window to form doped regions having different doping concentrations as described above.
Specifically, the doping concentration of the first P-type doped region or the first N-type doped region is 1×10 20 /cm 3 ～5×10 20 /cm 3 The second P-type doped regionOr the doping concentration of the second N-type doped region is 2×10 17 /cm 3 ～5×10 18 /cm 3 The doping concentration of the third P-type doping region or the third N-type doping region is 1.2X10 17 ～4×10 17 /cm 3 . In some embodiments, the dopant in the first P-type doped region 301, the second P-type doped region 302, and the third P-type doped region 305 is boron (B); and the dopants of the first N-type doped region 308, the second N-type doped region 307, and the third N-type doped region 303 are phosphorus (P) element or arsenic (As) element.
Here, before the selective doping process is performed, a different height from other regions in the first semiconductor layer 300 is formed in a direction (Z direction) perpendicular to the substrate among the partial region where the second P-type doped region 302, the partial region where the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 are to be formed, and in practical applications, a combination of processes such as photolithography, etching, and the like may be used to achieve the different heights of the different regions. The method comprises the following steps: a height H formed in a direction perpendicular to the substrate in a region where the second P-type doped region 302, a region where the third P-type doped region 305, the first intrinsic region 304, and the third N-type doped region 303 are to be formed 1 Height H greater than other regions in the first semiconductor layer 2 。
Next, step 203 is performed. Referring to fig. 8c, a second semiconductor layer 400 is formed and covers the first intrinsic region 304 and the third N-type doped region 303 and part of the second P-type doped region 302 and the third P-type doped region 305 in the first direction X.
In some embodiments, an initial second semiconductor layer 400 '(not shown) is first formed to cover the first semiconductor layer 300, and then the initial second semiconductor layer 400' is etched using a patterned photoresist layer to form the second semiconductor layer 400, and then the photoresist layer is removed.
Here, the second semiconductor layer 400 is formed in a rectangular shape (the shape of which may refer to the second semiconductor layer 400 in fig. 1 or 3), and a trapezoidal shape may be used.
In some embodiments, the material of the first semiconductor layer is different from the material of the second semiconductor layer. For example, in the case where the material of the first semiconductor layer is Si, the material of the second semiconductor layer is germanium, a germanium-silicon alloy, a group III-V material, and an alloy thereof.
In a specific embodiment of the avalanche photodetector of the embodiment of the present invention, the material of the first semiconductor layer is silicon, and the material of the second semiconductor layer is germanium, in other words, the avalanche photodetector of the embodiment of the present invention is a germanium-silicon avalanche photodetector.
The second semiconductor layer may be formed by epitaxially growing a high quality poly-germanium material using a molecular beam epitaxial growth process or the like.
Step 204 is next performed. Reference is made to fig. 8d. Forming a first electrode 501, a second electrode 502 and a third electrode 503 which are arranged perpendicular to the plane direction of the substrate, wherein the first electrode 501 is electrically connected with the first N-type doped region 308; the second electrode 502 is electrically connected to the third P-type doped region 305, and the third electrode 503 is electrically connected to the first P-type doped region 301.
In some embodiments, the forming the first electrode 501, the second electrode 502, and the third electrode 503 disposed perpendicular to the substrate plane direction includes:
forming a cover layer 600 covering the first semiconductor layer 300 and the second semiconductor layer 400;
forming a first window, a second window, and a third window over the first N-type doped region 308, the third P-type doped region 305, and the first N-type doped region 308, respectively;
and filling a metal material in the first, second and third windows to form a first electrode 501, a second electrode 502 and a third electrode 503.
In one embodiment, the cover layer 600 may be formed directly from an insulating material. Referring to fig. 8e, a capping layer 600 may be first formed using an insulating material, such as silicon dioxide, to cover the doped first semiconductor layer 300 and the second semiconductor layer 400. Then, windows are formed on the cover layer by photolithography and inductive plasma etching to form a first window, a second window and a third window to expose the surfaces of the first N-type doped region 308, the third P-type doped region 305 and the first P-type doped region 301 in the first semiconductor layer 300, and then, metal materials are deposited in the first window, the second window and the third window by, for example, magnetron sputtering process to form the first electrode 501, the second electrode 502 and the third electrode 503 electrically connected to the first N-type doped region 308, the third P-type doped region 305 and the first P-type doped region 301, respectively.
After the electrode is formed, a planarization step may be further performed on the upper surface of the cover layer 600, and a Chemical Mechanical Polishing (CMP) process may be specifically used. In this manner, different voltages may be applied between the first electrode 501 and the second electrode 502, and between the first electrode and the third electrode 503 through the external leads, thereby providing bias voltages between the first electrode 501 and the third electrode 503, and between the second electrode 502 and the third electrode 503.
It should be noted that the embodiment of the avalanche photodetector provided by the invention and the embodiment of the preparation method of the avalanche photodetector belong to the same conception; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict. However, it should be further explained that the technical characteristics of the avalanche photodetector provided by the embodiment of the present invention can be combined to solve the technical problems to be solved by the present invention; therefore, the avalanche photodetector provided by the embodiment of the invention can be free from the limitation of the preparation method of the avalanche photodetector provided by the embodiment of the invention, and any avalanche photodetector prepared by the preparation method capable of forming the avalanche photodetector structure provided by the embodiment of the invention is within the protection scope of the invention.
The above description is not intended to limit the scope of the invention, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the invention.
Claims (14)
1. An avalanche photodetector, comprising:
a substrate, a surface of which includes a first semiconductor layer;
a second semiconductor layer located over the first semiconductor layer, the second semiconductor layer having a material different from a material of the first semiconductor layer; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first semiconductor layer comprises a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged in a first direction, the dopant concentrations of the first P-type doped region, the second P-type doped region and the third P-type doped region are sequentially decreased, the dopant concentrations of the first N-type doped region, the second N-type doped region and the third N-type doped region are sequentially decreased, and the first direction is the electron flow direction of the avalanche photodetector;
And wherein the first intrinsic region, the third N-type doped region, a portion of the second P-type doped region immediately adjacent to the third N-type doped region, a portion of the third P-type doped region immediately adjacent to the first intrinsic region in the first semiconductor layer have a first height H in a direction perpendicular to the substrate 1 Other regions in the first semiconductor layer have a second height H 2 ；H 1 Not equal to H 2 ；
The second semiconductor layer sequentially covers the second P-type doped region along the first direction and has the second height H 2 The second P-type doped region having the first height H 1 The third N-type doped region, the first intrinsic region, and the third P-type doped region have the first height H 1 The third P-type doped region having the second height H 2 Is a part of the area of (2);
the first N-type doped region is connected with a first electrode; the third P-type doped region is connected with a second electrode; the first P-type doped region is connected with a third electrode.
2. The avalanche photodetector according to claim 1 wherein H 1 Greater than H 2 。
3. The avalanche photodetector according to claim 1 wherein H 1 Less than H 2 。
4. The avalanche photodetector according to claim 1, wherein a first reverse bias voltage V is provided between said first electrode and said third electrode 1 And a second reverse bias voltage V is arranged between the first electrode and the second electrode 2 。
5. The avalanche photodetector according to claim 1 wherein said first semiconductor layer is silicon and said second semiconductor layer is germanium, a germanium-silicon alloy, a III-V material and alloys thereof.
6. The avalanche photodetector of claim 1 wherein said first P-type doped region or said first N-type doped region has a dopant concentration of 1 x 10 20 /cm 3 ～5×10 20 /cm 3 The dopant concentration of the second P-type doped region or the second N-type doped region is 2×10 17 /cm 3 ～5×10 18 /cm 3 The dopant concentration of the third P-type doped region or the third N-type doped region is 1.2X10 17 ～4×10 17 /cm 3 。
7. The avalanche photodetector according to claim 1 wherein said second intrinsic region has a dimension in said first direction of 50nm to 800nm.
8. The avalanche photodetector according to claim 1 or 2, wherein a dimension of the second semiconductor layer in the first direction is 150nm to 1500nm, a dimension in a second direction is 1 μm to 100 μm, and a dimension in a third direction is 150nm to 600nm, wherein the third direction is a direction perpendicular to the substrate, and the second direction is perpendicular to the third direction and to the first direction.
9. A method of making an avalanche photodetector comprising:
providing a substrate, wherein the surface of the substrate comprises a first semiconductor layer;
performing a selective doping process to form a first P-type doped region, a second P-type doped region, a third N-type doped region, a first intrinsic region, a third P-type doped region, a second intrinsic region, a second N-type doped region and a first N-type doped region which are sequentially arranged along a first direction on the first semiconductor layer, wherein the dopant concentrations of the first P-type doped region, the second P-type doped region and the third P-type doped region are sequentially decreased, and the dopant concentrations of the first N-type doped region, the second N-type doped region and the third N-type doped region are sequentially decreased; before the selective doping process is performed, forming a height which is different from other regions in the first semiconductor layer in a direction perpendicular to the substrate in a region in which the partial region of the second P-type doped region, the partial region of the third P-type doped region, the first intrinsic region and the third N-type doped region are to be formed;
forming a second semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer, and part of the second P-type doped region, the third N-type doped region, the first intrinsic region and part of the third P-type doped region are sequentially covered in the first direction;
Forming a first electrode, a second electrode and a third electrode which are arranged in the direction perpendicular to the plane of the substrate, wherein the first electrode is electrically connected with the first N-type doped region; the second electrode is electrically connected with the third P-type doped region, and the third electrode is electrically connected with the first P-type doped region;
the first direction is an electron flow direction of the avalanche photodetector.
10. The method of claim 9, wherein forming a different height in a direction perpendicular to the substrate in the regions of the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region than other regions in the first semiconductor layer before performing the selective doping process comprises:
a height H formed in a direction perpendicular to the substrate in a region where the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region are to be formed 1 Height H greater than other regions in the first semiconductor layer 2 。
11. The method of claim 9, wherein forming a different height in a direction perpendicular to the substrate in the regions of the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region than other regions in the first semiconductor layer before performing the selective doping process comprises:
A height H formed in a direction perpendicular to the substrate in a region where the second P-type doped region, the third P-type doped region, the first intrinsic region, and the third N-type doped region are to be formed 1 Height H less than other regions in the first semiconductor layer 2 。
12. The method of claim 9, wherein the material of the first semiconductor layer is silicon and the material of the second semiconductor layer is germanium, a germanium-silicon alloy, a group III-V material, and alloys thereof.
13. The method of claim 9, wherein a dopant concentration of the first P-type doped region or the first N-type doped region is 1 x 10 20 /cm 3 ～5×10 20 /cm 3 The dopant concentration of the second P-type doped region or the second N-type doped region is 2×10 17 /cm 3 ～5×10 18 /cm 3 The dopant concentration of the third P-type doped region or the third N-type doped region is 1.2X10 17 ～4×10 17 /cm 3 。
14. The method of claim 9, wherein forming the first, second, and third electrodes disposed perpendicular to the planar direction of the substrate comprises:
forming a cover layer covering the first semiconductor layer and the second semiconductor layer;
forming a first window, a second window and a third window at one end of the first N-type doped region, the third P-type doped region and the first P-type doped region along the second direction respectively so as to expose partial surfaces of the first P-type doped region, the third P-type doped region and the first N-type doped region;
And filling metal in the first window, the second window and the third window to form the first electrode, the second electrode and the third electrode.
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