CN114256203A

CN114256203A - Semiconductor package and method of manufacturing the same

Info

Publication number: CN114256203A
Application number: CN202111037391.0A
Authority: CN
Inventors: 大卫·锡纳乐; 麦克·凯利; 拉诺德·胡莫勒; 莫印苏; 李相亨; 杜旺朱; 金进勇
Original assignee: Anrely Technology Singapore Holdings Pte Ltd
Current assignee: Anrely Technology Singapore Holdings Pte Ltd
Priority date: 2020-09-22
Filing date: 2021-09-06
Publication date: 2022-03-29
Also published as: TW202234598A; KR20220039574A

Abstract

Semiconductor packages and methods of manufacturing the same. An electronic device includes: a Signal Redistribution Structure (SRS) comprising an SRS top side, an SRS bottom side, and a plurality of SRS lateral sides, wherein the signal redistribution structure is coreless; a Lower Electronic Component (LEC) comprising a LEC top side, a LEC bottom side, and a plurality of LEC lateral sides, wherein the LEC top side is coupled to the SRS bottom side; a vertical interconnect structure coupled to the SRS bottom side at a location laterally offset from the lower electronic component; an LEC interconnect structure coupled to the LEC top side and the SRS bottom side such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure; a semiconductor die comprising a die top side, a die bottom side, and a plurality of die lateral sides; a first die interconnect structure coupled to the SRS top side and the die bottom side such that the semiconductor die is electrically coupled to the vertical interconnect structure; and a second die interconnect structure coupled to the SRS top side and the die bottom side such that the semiconductor die is electrically coupled to the lower electronic component.

Description

Semiconductor package and method of manufacturing the same

CROSS-REFERENCE TO/INCORPORATION OF RELATED APPLICATIONS

This application was filed on 2.12.2019 and is entitled "SEMICONDUCTOR package and METHOD of manufacturing the same" (SEMICONDUCTOR package PACKAGE AND manufacturing METHOD) and is intended as a partial continuation of U.S. patent application No. 16/700,592 issued as U.S. patent nos. __, ___, ___; a continuation of U.S. patent application No. 16/213,769 (now U.S. patent No. 10,497,674), filed 2018, 12, 7, and entitled SEMICONDUCTOR package and METHOD of manufacturing the same (SEMICONDUCTOR device PACKAGE AND screening METHOD), each of which is hereby incorporated by reference herein in its entirety.

This application is related to the following applications: us patent application No. 14/686,725 entitled "SEMICONDUCTOR package with high layout density die (SEMICONDUCTOR PACKAGE WITH HIGH ROUTING DENSITY PATCH)" filed on 14/4/2015; us patent application No. 14/823,689 (now us patent No. 9,543,242), filed on 11/8/2015 and entitled "SEMICONDUCTOR package and METHOD of manufacturing the same" (SEMICONDUCTOR package PACKAGE AND family METHOD); U.S. patent application No. 15/400,041 entitled SEMICONDUCTOR package and METHOD of manufacturing the same (SEMICONDUCTOR package PACKAGE AND rubbing METHOD) filed on 6.1.2017; and U.S. patent application No. 15/066,724, filed 3/10/2016 and entitled SEMICONDUCTOR package and METHOD of MANUFACTURING the same (SEMICONDUCTOR device PACKAGE AND SEMICONDUCTOR METHOD), each of which is hereby incorporated by reference herein in its entirety.

Technical Field

The present invention relates to a semiconductor package structure and a method for manufacturing a semiconductor package.

Background

Current semiconductor packages and methods for forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, or oversized packages. Further limitations and disadvantages of such approaches will become apparent to one of skill in the art, through comparison of conventional and traditional approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

Various aspects of the present disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present disclosure provide various semiconductor package structures including a connecting die that routes electrical signals between a plurality of other semiconductor dies, and methods of manufacturing the same.

According to one embodiment of the present invention, an electronic apparatus includes: a Signal Redistribution Structure (SRS) comprising an SRS top side, an SRS bottom side, and a plurality of SRS lateral sides, wherein the signal redistribution structure is coreless; a Lower Electronic Component (LEC) comprising a LEC top side, a LEC bottom side, and a plurality of LEC lateral sides, wherein the LEC top side is coupled to the SRS bottom side; a vertical interconnect structure coupled to the SRS bottom side at a location laterally offset from the lower electronic component; an LEC interconnect structure coupled to the LEC top side and the SRS bottom side such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure; a semiconductor die comprising a die top side, a die bottom side, and a plurality of die lateral sides; a first die interconnect structure coupled to the SRS top side and the die bottom side such that the semiconductor die is electrically coupled to the vertical interconnect structure; and a second die interconnect structure coupled to the SRS top side and the die bottom side such that the semiconductor die is electrically coupled to the lower electronic component.

In the electronic device in the example, the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; and the semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the LEC interconnect structure.

In the electronic device in the example, the LEC interconnect structure includes a metal pillar.

In the electronic device in the example, the vertical interconnect structure vertically spans the lower electronic component and the LEC interconnect structure.

The electronic device in the example includes a first encapsulant material laterally surrounding the lower electronic component, the LEC interconnect structure, and the vertical interconnect structure.

In the electronic device in the example, the LEC bottom side is exposed from the first encapsulant material, and the electronic device further comprises a layer of material contacting and covering the LEC bottom side.

The electronic device in the example includes a second encapsulant laterally surrounding the semiconductor die separate from the first encapsulant.

In the electronic device in the example, the Lower Electronic Component (LEC) includes an LEC substrate and an LEC encapsulant over the LEC substrate.

In the electronic device in the example, the lower electronic component includes a connecting die.

In the electronic device in the example, a first portion of the lower electronic component is positioned within a footprint of the semiconductor die and a second portion of the lower electronic component is positioned outside the footprint of the semiconductor die.

According to another embodiment of the present invention, an electronic apparatus includes: a first signal redistribution structure (SRS1) including an SRS1 first side and an SRS1 second side opposite the SRS1 first side; vertical interconnect structures on a first side of the SRS 1; a connection die on a first side of the SRS1, including: a Connected Die Signal Redistribution Structure (CDSRS) including a CDSRS first side facing away from the first signal redistribution structure, and a CDSRS second side facing toward the first signal redistribution structure; connecting die interconnects coupled to the CDSRS second side and the SRS1 first side; and a connection die encapsulation that encapsulates the connection die interconnects and the CDSRS second side; and a second signal redistribution structure (SRS2) on the vertical interconnect structure and on the CDSRS first side, the second signal redistribution structure (SRS2) including an SRS2 first side facing away from the connecting die and an SRS2 second side facing toward the connecting die.

The electronic device in the other example includes a first semiconductor die coupled to a second side of the SRS1, and a second semiconductor die coupled to a second side of the SRS 1.

The electronic device in the other example includes an encapsulation material that encapsulates the vertical interconnect structure, the connecting die, the SRS1 first side, and the SRS2 second side.

In the electronic device in the another example, the encapsulant material includes a side that is coplanar with a side of the connection die encapsulant.

The electronic device in the other example includes an adhesive layer coupling the CDSRS first side to the SRS2 second side.

According to still another embodiment of the present invention, a method of manufacturing an electronic device includes: providing a Signal Redistribution Structure (SRS) comprising an SRS top side, an SRS bottom side, and a plurality of SRS lateral sides, wherein the signal redistribution structure is coreless; providing a Lower Electronic Component (LEC) comprising a LEC top side, a LEC bottom side, and a plurality of LEC lateral sides, wherein the LEC top side is coupled to the SRS bottom side; providing a vertical interconnect structure coupled to the SRS underside at a location laterally offset from the lower electronic component; providing a LEC interconnect structure coupled to the LEC top side and the SRS bottom side such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the LEC interconnect structure; providing a semiconductor die comprising a die top side, a die bottom side, and a plurality of die lateral sides; providing a first die interconnect structure coupled to the SRS top side and the die bottom side such that the semiconductor die is electrically coupled to the vertical interconnect structure; and providing a second die interconnect structure coupled to the SRS top side and the die bottom side such that the semiconductor die is electrically coupled to the lower electronic component.

In the method in the further example, the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; and the semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the LEC interconnect structure.

The method in the further example further comprises: providing a first encapsulant material laterally surrounding the lower electronic components, the LEC interconnect structures, and the vertical interconnect structures, wherein the LEC bottom side is exposed from the first encapsulant material; and providing a layer of material contacting and covering the underside of the LECs.

The method in the further example further comprises: providing a first encapsulant material laterally surrounding the lower electronic components, the LEC interconnect structures, and the vertical interconnect structures, wherein the LEC bottom side is exposed from the first encapsulant material; and providing a second encapsulant laterally surrounding the semiconductor die separate from the first encapsulant, wherein each of the SRS lateral sides is coplanar with a respective lateral side of the first encapsulant and coplanar with a respective lateral side of the second encapsulant.

In the method in the further example, the Lower Electronic Component (LEC) includes an LEC substrate and an LEC encapsulant over the LEC substrate.

Drawings

Fig. 1 shows a flow diagram of an example method of manufacturing an electronic device, in accordance with various aspects of the present disclosure.

Fig. 2A-2Q show cross-sectional views illustrating an example electronic device and an example method of manufacturing an example electronic device, in accordance with various aspects of the present disclosure.

Fig. 3 shows a flow diagram of an example method of manufacturing an electronic device, in accordance with various aspects of the present disclosure.

Fig. 4A-4N show cross-sectional views illustrating example electronic devices and example methods of manufacturing example electronic devices, in accordance with various aspects of the present disclosure.

Fig. 5 shows a flow diagram of an example method of manufacturing an electronic device, in accordance with various aspects of the present disclosure.

Fig. 6A-6M show cross-sectional views illustrating example electronic devices and example methods of manufacturing example electronic devices, in accordance with various aspects of the present disclosure.

Fig. 7 shows a flow diagram of an example method of manufacturing an electronic device, in accordance with various aspects of the present disclosure.

Fig. 8A-8N show cross-sectional views illustrating example electronic devices and example methods of manufacturing example electronic devices, in accordance with various aspects of the present disclosure.

Fig. 9 shows a top view of an example electronic device, according to various aspects of the present disclosure.

Fig. 10 shows a top view of an example electronic device, according to various aspects of the present disclosure.

Fig. 11 shows cross-sectional views illustrating an example electronic device, connecting dies, and electronic assembly, in accordance with various aspects of the present disclosure.

Fig. 12A-12E show cross-sectional views illustrating an example method of fabricating an example connected die, in accordance with various aspects of the present disclosure.

Fig. 13A-13K show cross-sectional views of an example method of manufacturing an example electronic device and an example electronic assembly, in accordance with various aspects of the present disclosure.

Fig. 14 shows cross-sectional views illustrating an example electronic device, connecting dies, and electronic assembly, in accordance with various aspects of the present disclosure.

Fig. 15A-15J show cross-sectional views of an example method of manufacturing an example electronic device and an example electronic assembly, in accordance with various aspects of the present disclosure.

Detailed Description

The following discussion presents various aspects of the present disclosure by providing examples. Such examples are non-limiting, and thus the scope of various aspects of the disclosure should not necessarily be limited by any particular characteristics of the examples provided. In the following discussion, the phrases "by way of example," "such as," and "exemplary" are non-limiting and are generally synonymous with "by way of example and not limitation," "by way of example and not limitation," and the like.

As used herein, "and/or" means any one or more of the items in the list joined by "and/or". As an example, "x and/or y" means any element in the three-element set { (x), (y), (x, y) }. In other words, "x and/or y" means "one or both of x and y". As another example, "x, y, and/or z" means any element of the seven-element set { (x), (y), (z), (x, y), (x, z), (y, z), (x, y, z) }. In other words, "x, y, and/or z" means "one or more of x, y, and z. Similarly, as used herein, "and/or" means any one or more of the items in the list joined by "or".

The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, component, or section discussed below could be termed a second element, component, or section without departing from the teachings of the present disclosure. Similarly, various spatial terms, such as "upper," "lower," "side," and the like may be used to distinguish one element from another element in a relative manner. However, it should be understood that the components may be oriented differently, for example, the semiconductor device or package may be turned sideways so that its "top" surface faces horizontally and its "side" surfaces face vertically without departing from the teachings of the present disclosure.

Various aspects of the present disclosure provide a semiconductor device or package and a method of manufacturing the same that may reduce cost, increase reliability, and/or improve manufacturability of the semiconductor device or package.

The above and other aspects of the present disclosure will be described in and be apparent from the following description of various example embodiments. Various aspects of the present disclosure will now be presented with reference to the drawings, so that those skilled in the art can readily practice the various aspects.

Fig. 1 shows a flow diagram of an example method 100 of manufacturing an electronic device (e.g., a semiconductor package, etc.). The example method 100 may, for example, share any or all characteristics with any other example methods discussed herein (e.g., the example method 300 of fig. 3, the example method 500 of fig. 5, the example method 700 of fig. 7, etc.). Fig. 2A-2Q show cross-sectional views illustrating an example electronic device (e.g., semiconductor package, etc.) and an example method of manufacturing the example electronic device, in accordance with various aspects of the present disclosure. Fig. 2A-2Q may illustrate example electronic devices, e.g., in various blocks (or steps) of method 100 of fig. 1. Fig. 1 and 2A-2Q will now be discussed together. It should be noted that the order of the example blocks of the method 100 may be varied without departing from the scope of the present disclosure.

The example method 100 may begin execution at block 105. The method 100 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, method 100 may begin executing automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to signals from a central manufacturing line controller, upon arrival of components and/or manufacturing materials used during execution of method 100, and so forth. As another example, the method 100 may begin execution in response to an operator command starting. Additionally, for example, the method 100 may begin execution in response to receiving an execution stream from any other method block (or step) discussed herein.

Example method 100 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 110. Block 110 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 110 may share any or all of the characteristics with any of the functional die receiving, manufacturing, and/or preparation operations discussed herein. Various example aspects of block 110 are presented in FIG. 2A.

Block 110 may, for example, include receiving multiple functional dies (or any portion thereof) from an upstream manufacturing process at the same facility or geographic location. Block 110 may also include, for example, receiving the functional die (or any portion thereof) from a vendor (e.g., from a foundry, etc.).

The received, fabricated, and/or prepared functional die may include any of a variety of characteristics. For example, although not shown, the received die may include a plurality of different dies on the same wafer (e.g., a multi-project wafer (MPW)). An example of such a configuration is shown in example 210A of fig. 2A of U.S. patent application No. 15/594,313, which is hereby incorporated by reference in its entirety for all purposes. In such MPW configurations, the wafer may contain a plurality of different types of functional dies. For example, the first die may include a processor and the second die may include a memory chip. For another example, the first die may include a processor and the second die may include a co-processor. Additionally, for example, the first die and the second die may each include a memory chip. In general, a die may include active semiconductor circuitry. Although the various examples presented herein typically place or attach singulated and cut functional die, such die may also be connected to each other prior to placement (e.g., as part of the same semiconductor wafer, as part of a reconstituted wafer, etc.).

Block 110 may, for example, include receiving functional die in one or more respective wafers dedicated to a single type of die. For example, as shown in FIG. 2A, example 200A-1 shows a wafer dedicated to an entire wafer of die 1, an example die of which is shown at 211, and example wafer 200A-3 shows a wafer dedicated to an entire wafer of die 2, an example die of which is shown at 212. It should be understood that although the various examples shown herein generally refer to first and second functional dies (e.g., die 1 and die 2), the scope of the present disclosure extends to any number of functional dies of the same or different types (e.g., three dies, four dies, etc.). For example, the scope of the present disclosure extends to passive electronic components (e.g., resistors, capacitors, inductors, etc.) in addition to or in place of functional semiconductor dies.

The functional dies 211 and 212 may include die interconnect structures. For example, as shown in fig. 2A, the first functional die 211 includes a first set of one or more die interconnect structures 213, and a second set of one or more die interconnect structures 214. Similarly, the second functional die 212 may include such structures. Die

interconnect structures

213 and 214 may include any of a variety of die interconnect structure characteristics, non-limiting examples of which are provided herein.

The first die interconnect structure 213 may, for example, include metal (e.g., copper, aluminum, etc.) posts or pads. The first die interconnect structure 213 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, posts, and the like.

The first die interconnect structure 213 may be formed in any of a variety of ways. For example, the first die interconnect structure 213 may be plated on a die pad of the functional die 211. Also, for example, the first die interconnect structure 213 may be printed and reflowed, wire bonded, and the like. It should be noted that in some example embodiments, the first die interconnect structure 213 may be a die pad of the first functional die 211.

The first die interconnect structure 213 may, for example, be capped. For example, the first die interconnect structure 213 may be solder capped. As another example, the first die interconnect structure 213 may be capped with a metal layer (e.g., a metal layer other than solder that forms a substitutional solid solution or an intermetallic with copper). For example, the first die interconnect structure 213 may be formed and/or connected as explained in U.S. patent application No. 14/963,037 entitled "Metal bonded Transient Interface Gradient Bonding for Metal Bonds," filed on 8.12.2015, the entire contents of which are hereby incorporated by reference herein. Additionally, for example, the first die interconnect structure 213 may be formed and/or connected as explained in U.S. patent application No. 14/989,455 entitled Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing the same, filed on 6.1.2016, which is hereby incorporated by reference herein in its entirety.

The first die interconnect structure 213 may, for example, include any of a variety of dimensional characteristics. For example, in an example implementation, the first die interconnect structure 213 may include a pitch (e.g., center-to-center spacing) of 30 microns and a diameter (or width, minor or major axis width, etc.) of 17.5 microns. For another example, in an example embodiment, the first die interconnect structure 213 may include a pitch in a range of 20 to 40 (or 30 to 40) microns and a diameter (or width, minor or major axis width, etc.) in a range of 10 to 25 microns. The first die interconnect structure 213 may be, for example, 15 to 20 microns high.

The second die interconnect structure 214 may, for example, share any or all of the characteristics with the first die interconnect structure 213. Some or all of the second die interconnect structures 214 may be substantially different from the first die interconnect structures 213, for example.

The second die interconnect structure 214 may, for example, include metal (e.g., copper, aluminum, etc.) posts or pads. The second die interconnect structure 214 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, and the like. The second die interconnect structure 214 may, for example, but need not be, the same general type of interconnect structure as the first die interconnect structure 213. For example, the first die interconnect structure 213 and the second die interconnect structure 214 may both include copper pillars. As another example, the first die interconnect structure 213 may include a metal pad and the second die interconnect structure 214 may include a copper pillar.

The second die interconnect structure 214 can be formed in any of a variety of ways. For example, the second die interconnect structure 214 may be electroplated on the die pad of the functional die 211. Also, for example, the second die interconnect structure 214 may be printed and reflowed, wire bonded, and the like. The second die interconnect structure 214 may be formed in the same process step as the first die interconnect structure 213, but such

die interconnect structures

213 and 214 may also be formed in separate respective steps and/or in overlapping steps.

For example, in a first example scenario, a first portion (e.g., a first half, a first third, etc.) of each of the second die interconnect structures 214 may be formed in the same first electroplating operation as the first die interconnect structure 213. Continuing with the first example scenario, a second portion (e.g., a second half, the remaining thirds, etc.) of each of the second die interconnect structures 214 may then be formed in a second electroplating operation. For example, during the second plating operation, the first die interconnect structure 213 may be inhibited from additional plating (e.g., by a dielectric or protective mask layer formed thereon, by removing a plating signal, etc.). In another example scenario, the second die interconnect structure 214 may be formed in a second electroplating process that is completely independent of the first electroplating process used to form the first die interconnect structure 213, which may be covered by, for example, a protective mask layer during the second electroplating process.

The second die interconnect structure 214 may, for example, be uncapped. For example, the second die interconnect structure 214 may not be solder capped. In an example scenario, the first die interconnect structure 213 may be capped (e.g., by a solder cap, by a metal layer cap, etc.) while the second die interconnect structure 214 is not capped. In another example scenario, neither the first die interconnect structure 213 nor the second die interconnect structure 214 is capped.

The second die interconnect structure 214 may, for example, include any of a variety of dimensional characteristics. For example, in an example embodiment, the second die interconnect structures 214 may include a pitch (e.g., center-to-center spacing) of 80 microns and a diameter (or width) of 25 microns or more. For another example, in an example embodiment, the second die interconnect structure 214 may include a pitch in a range of 50 to 80 microns and a diameter (or width, minor or major axis width, etc.) in a range of 20 to 30 microns. Additionally, for example, in an example embodiment, the second die interconnect structure 214 may include a pitch in a range of 80 to 150 (or 100 to 150) microns and a diameter (or width, minor or major axis width, etc.) in a range of 25 to 40 microns. The second die interconnect structure 214 may be, for example, 40 to 80 microns high.

It should be noted that a functional die (e.g., in wafer form, etc.) may be received that already has one or more die interconnect structures 213/214 (or any portion thereof) formed thereon.

It should also be noted that the functional die (e.g., in wafer form) may be thinned at this point from its original die thickness (e.g., by grinding, mechanical and/or chemical thinning, etc.), but need not be. For example, the functional die wafer (e.g., the wafer shown in examples 200A-1, 200A-2, 200A-3, and/or 200A-4) may be a full thickness wafer. As another example, a wafer of functional dies (e.g., the wafer shown by examples 200A-1, 200A-2, 200A-3, 200A-4, etc.) can be at least partially thinned to reduce the thickness of the resulting package while still enabling safe handling of the wafer.

In general, block 110 may include receiving, fabricating, and/or preparing a plurality of functional dies. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of such receiving and/or manufacturing, nor by any particular characteristics of such functional die.

Example method 100 may include receiving, fabricating, and/or preparing a connection die at block 115. Block 115 may include receiving and/or fabricating a plurality of connected dies in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 115 are presented in examples 200B-1 through 200B-7 shown in FIGS. 2B-1 and 2B-2.

Block 115 may, for example, include receiving a plurality of connected dies from an upstream manufacturing process at the same facility or geographic location. Block 115 may also include, for example, receiving a connection die from a vendor (e.g., from a foundry, etc.).

The received, fabricated, and/or prepared connection die may include any of a variety of characteristics. For example, the received, manufactured, and/or prepared die may include a plurality of connected dies on a wafer (e.g., a silicon or other semiconductor wafer, a glass wafer or panel, a metal wafer or panel, etc.). For example, as shown in FIG. 2B-1, the example 200B-1 includes an entire wafer of connected dies, an example connected die of which is shown at 216 a. It should be understood that although the various examples shown herein generally involve the utilization of a single connection die in a package, multiple connection dies (e.g., multiple connection dies of the same or different designs) may be utilized in a single electronic device package. Non-limiting examples of such configurations are provided herein.

In the examples shown herein (e.g., 200B-1 to 200B-4), the connecting die may, for example, include only circuit routing circuitry (e.g., no active semiconductor components and/or passive components). It should be noted, however, that the scope of the present disclosure is not so limited. For example, the connecting die shown herein may include passive electronic components (e.g., resistors, capacitors, inductors, Integrated Passive Devices (IPDs), etc.) and/or active electronic components (e.g., transistors, logic circuits, semiconductor processing components, semiconductor memory components, etc.) and/or optical components, etc.

The connection die may include a connection die interconnect structure. For example, the example connection die 216a shown in figure 200B-1 includes a connection die interconnect structure 217. The connection-die interconnect structure 217 may include any of a variety of interconnect structure characteristics, non-limiting examples of which are provided herein. Although this discussion typically presents all of the connection die interconnect structures 217 as being identical to one another, they may also be different from one another. For example, referring to fig. 2B-1, the left portion of the connecting-die interconnect structure 217 may be the same as or different from the right portion of the connecting-die interconnect structure 217.

The connecting die interconnect structure 217 and/or formation thereof may share any or all of the characteristics with the first die interconnect structure 213 and/or the second die interconnect structure 214 and/or formation thereof discussed herein. In an example embodiment, connecting the first portions of the die interconnect structures 217 may include providing spacing, layout, shape, size, and/or material characteristics of the respective first die interconnect structures 213 that mate such first portions to the first functional die 211, and connecting the second portions of the die interconnect structures 217 may include providing spacing, layout, shape, size, and/or material characteristics of the respective first die interconnect structures 213 that mate such second portions to the second functional die 212.

The connection-die interconnect structure 217 may, for example, include metal (e.g., copper, aluminum, etc.) posts or pads. The connection die interconnect structure 217 may also include, for example, conductive bumps (e.g., C4 bumps, etc.) or balls, leads, posts, and the like.

The connection-die interconnect structure 217 may be formed in any of a variety of ways. For example, the connecting die interconnect structure 217 may be plated on the die pad of the connecting die 216 a. Also, for example, the connection die interconnect structure 217 may be printed and reflowed, wire bonded, and the like. It should be noted that in some example embodiments, connection die interconnect structure 217 may be a die pad connecting die 216 a.

The connection die interconnect structure 217 may be capped, for example. For example, the connection die interconnect structure 217 may be covered with solder. As another example, the connection die interconnect structure 217 may be covered with a metal layer (e.g., a metal layer forming a substituted solid solution or an intermetallic with copper). For example, the connecting die interconnect structure 217 may be formed and/or connected as explained in U.S. patent application No. 14/963,037 entitled "Metal bonded Transient Interface Gradient Bonding for Metal Bonds," filed on 8.12.2015, the entire contents of which are hereby incorporated by reference herein. Additionally, for example, the connecting die interconnect structure 217 may be formed and/or connected as explained in U.S. patent application No. 14/989,455 entitled Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing the same, filed on 6.1.2016, which is hereby incorporated by reference in its entirety.

The connecting-die interconnect structure 217 may, for example, include any of a variety of dimensional characteristics. For example, in an example implementation, the connecting die interconnect structures 217 may include a pitch (e.g., center-to-center spacing) of 30 microns and a diameter (or width, minor or major axis width, etc.) of 17.5 microns. Also for example, in an example embodiment, the connection die interconnect structure 217 may include a pitch in the range of 20 to 40 (or 30 to 40) microns and a diameter (or width, minor or major axis width, etc.) in the range of 10 to 25 microns. The connection die interconnect structure 217 may be, for example, 15 to 20 microns high.

In an example scenario, the connecting die interconnect structures 217 may include copper pillars that mate with respective first die interconnect structures 213 (e.g., metal pads, conductive bumps, copper pillars, etc.) of the first and second functional dies 211, 212.

Connecting die 216a (or wafer 200B-1 thereof) may be formed in any of a variety of ways, non-limiting examples of which are discussed herein. For example, referring to fig. 2B-1, a connecting die 216a (e.g., shown in example 200B-3) or wafer thereof (e.g., shown in example 200B-1) may, for example, include a support layer 290a (e.g., a silicon or other semiconductor layer, a glass layer, a metal layer, a plastic layer, etc.). A Redistribution (RD) structure 298 may be formed on support layer 290 a. RD structure 298 may, for example, include a base dielectric layer 291, a first dielectric layer 293, first conductive traces 292, a second dielectric layer 296, second conductive traces 295, and a connecting die interconnect structure 217.

Base dielectric layer 291 may be, for example, on support layer 290 a. The base dielectric layer 291 may include, for example, an oxide layer, a nitride layer, any of a variety of inorganic dielectric materials, and the like. The base dielectric layer 291 may be formed, for example, according to specifications and/or may be native. The base dielectric layer 291 may be referred to as a passivation layer. The base dielectric layer 291 may be or include, for example, a silicon dioxide layer formed using a Low Pressure Chemical Vapor Deposition (LPCVD) process. In other example embodiments, the base dielectric layer 291 may be formed of any of a variety of organic dielectric materials, many examples of which are provided herein.

The connecting die 216a (e.g., shown in example 200B-3) or wafer thereof (e.g., shown in example 200B-1) can also include, for example, first conductive traces 292 and a first dielectric layer 293. The first conductive trace 292 can, for example, comprise a deposited conductive metal (e.g., copper, aluminum, tungsten, etc.). The first conductive trace 292 may be formed, for example, by sputtering, electroplating, electroless plating, and the like. The first conductive traces 292 may be formed, for example, at sub-micron or sub-two micron pitches (or center-to-center spacing). The first dielectric layer 293 may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). It should be noted that in various implementations, the first dielectric layer 293 may be formed before the first conductive trace 292, e.g., formed with an aperture that is then filled with the first conductive trace 292 or a portion thereof. In example embodiments including, for example, copper conductive traces, the traces may be deposited using a dual damascene process.

In an alternative assembly, the first dielectric layer 293 may comprise an organic dielectric material. For example, the first dielectric layer 293 may include Bismaleimide Triazine (BT), phenol resin, Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), epoxy resin, and equivalents thereof and compounds thereof, but aspects of the present disclosure are not limited thereto. The organic dielectric material may be formed in any of a variety of ways, such as Chemical Vapor Deposition (CVD). In such alternative assemblies, the first conductive traces 292 can be, for example, at a pitch (or center-to-center spacing) of 2 to 5 microns.

The connecting die 216a (e.g., shown in example 200B-3) or wafer 200B-1 thereof (e.g., shown in example 200B-1) can also include, for example, second conductive traces 295 and a second dielectric layer 296. The second conductive trace 295 may, for example, comprise a deposited conductive metal (e.g., copper, etc.). The second conductive traces 295 may be connected to respective first conductive traces 292, for example, by respective conductive vias 294 or holes (e.g., in the first dielectric layer 293). The second dielectric layer 296 may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer 296 may comprise an organic dielectric material. For example, the second dielectric layer 296 may include Bismaleimide Triazine (BT), phenol resin, Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), epoxy resin, and equivalents thereof and compounds thereof, but aspects of the present disclosure are not limited thereto. Second dielectric layer 296 may be formed, for example, using a CVD process, although the scope of the present disclosure is not limited in this respect. It should be noted that the various dielectric layers (e.g., first dielectric layer 293, second dielectric layer 296, etc.) may be formed from the same dielectric material and/or using the same process, but this is not required. For example, the first dielectric layer 293 may be formed of any of the inorganic dielectric materials discussed herein and the second dielectric layer 296 may be formed of any of the organic dielectric materials discussed herein, or vice versa.

Although two sets of dielectric layers and conductive traces are illustrated in fig. 2B-1, it should be understood that RD structure 298 connecting die 216a (e.g., shown in example 200B-3) or a wafer thereof (e.g., shown in example 200B-1) may include any number of such layers and traces. For example, RD structure 298 may include only one dielectric layer and/or one set of conductive traces, three sets of dielectric layers and/or conductive traces, and so on.

A connection die interconnect structure 217 (e.g., conductive bumps, conductive balls, conductive pillars or rods, conductive pads or pads, etc.) may be formed on a surface of the RD structure 298. Examples of such connecting die interconnect structures 217 are shown in fig. 2B-1 and 2B-2, where the connecting die interconnect structures 217 are shown formed on the front side (or top side) of the RD structure 298 and electrically connected to respective second conductive traces 295 through conductive vias in the second dielectric layer 296. Such a connecting die interconnect structure 217 may be used, for example, to couple RD structure 298 to various electronic components (e.g., active semiconductor components or dies, passive components, etc.), including, for example, first functional die 211 and second functional die 212 discussed herein.

The connecting-die interconnect structure 217 may, for example, comprise any of a variety of conductive materials (e.g., any one or combination of copper, nickel, gold, etc.). The connection die interconnect structure 217 may also include solder, for example. Also for example, the connecting die interconnect structure 217 may include solder balls or bumps, multi-ball solder columns, elongated solder balls, metal (e.g., copper) core balls with a solder layer on the metal core, plated column structures (e.g., copper columns, etc.), lead structures (e.g., wire bond leads), and so forth.

Referring to fig. 2B-1, an example 200B-1 showing a wafer of connection dies 216a may be thinned, e.g., to produce a thin connection die wafer of thin connection dies 216B as shown at example 200B-2. For example, a thin-connected die wafer (e.g., as shown in example 200B-2) may be thinned (e.g., by grinding, chemical and/or mechanical thinning, etc.) to a degree that still allows safe handling of the thin-connected die wafer and/or its individual thin-connected dies 216B, but provides a low profile. For example, referring to fig. 2B-1, in an example implementation in which support layer 290B comprises silicon, thin-connect die 216B may still comprise at least a portion of silicon support layer 290B. For example, the bottom side (or back side) of thin-connect die 216b may include sufficient non-conductive support layer 290b, base dielectric layer 291, etc. to prevent conductive access at the bottom side of the remaining support layer 290b to conductive layers at the top side. In other examples, thin connection die 216b may be thinned to substantially or completely remove support layer 290 b. In such examples, conductive access at the bottom side of the connecting die 216b may still be blocked by the base dielectric 291.

For example, in an example implementation, the thin-connect die wafer (e.g., as shown in example 200B-2) or the thin-connect die 216B thereof may have a thickness of 50 microns or less. In another example implementation, the thin-connect die wafer (or the thin-connect die 216b thereof) may have a thickness in the range of 20 to 40 microns. As will be discussed herein, the thickness of thin connection die 216b may be less than the length of second die interconnect structure 214 of first die 211 and second die 212, e.g., such that thin connection die 216b may fit between the carrier and functional dies 211 and 212.

Two example connected die implementations labeled "connected die example 1" and "connected die example 2" are shown at 200B-5 of FIG. 2B-2. Connecting die example 1 may utilize inorganic dielectric layers (and/or a combination of inorganic and organic dielectric layers), for example, in RD structure 298 and semiconductor support layer 290. The connecting die example 1 may be produced, for example, using the silicon-free integrated module (SLIMTM) Technology of the security company (Amkor Technology). The semiconductor support layer may be, for example, 30 μm to 100 μm (e.g., 70 μm) thick, and each level (or sub-layer or layer) of the RD structure (e.g., comprising at least a dielectric layer and a conductive layer) may be, for example, 1 μm to 3 μm (e.g., 3 μm, 5 μm, etc.) thick. Examples the total thickness of the resulting structure can be, for example, in the range of 33 μm to 109 μm (e.g., <80 μm, etc.). It should be noted that the scope of the present disclosure is not limited to any particular size.

Example 2 of connecting dies may utilize an organic dielectric layer (and/or a combination of inorganic and organic dielectric layers), for example, in RD structure 298 and semiconductor support layer 290. Connecting die example 2 may be implemented, for example, with a company-attached Silicon Wafer Integrated Fanout (SWIFT)^TM) And (4) technical generation. The semiconductor support layer may be, for example, 30 μm to 100 μm (e.g., 70 μm) thick, and each level (or sub-layer or layer) of the RD structure (e.g., including at least a dielectric layer and a conductive layer) may be, for example, 4 to 7 μm thick, 10 μm thick, and so on. Examples the total thickness of the resulting structure may be in the range of 41 μm to 121 μm for example (e.g.,<80 μm, 100 μm, 110 μm, etc.). It should be noted that the scope of the present disclosure is not limited to any particular size. It should also be noted that in various example implementations, support layer 290 of example 2 of connected die may be thinned (e.g., relative to example 1 of connected die) to achieve the same or similar overall thickness.

Example implementations presented herein generally relate to single-sided connection dies that may have interconnect structures on only one side, for example. It should be noted, however, that the scope of the present disclosure is not limited to such single-sided structures. For example, as demonstrated by examples 200B-6 and 200B-7, connection die 216c may include interconnect structures on both sides. An example implementation of such a connection die 216c (e.g., as shown at example 200B-7) and its wafer (e.g., as shown at example 200B-6) is shown at fig. 2B-2, which may also be referred to as a double-sided connection die. The example wafer of (e.g., example 200B-6) may share any or all of the characteristics, for example, with the example wafer shown in FIG. 2B and discussed herein (e.g., examples 200B-1 and/or 200B-2). Also for example, example connector die 216c may share any or all of the characteristics with example connector dies 216a and/or 216B shown in fig. 2B-1 and discussed herein. For example, the connecting-die interconnect structure 217B may share any or all of the characteristics with the connecting-die interconnect structure 217 shown in fig. 2B-1 and discussed herein. Also for example, any or all of Redistribution (RD) structure 298B, base dielectric layer 291B, first conductive trace 292B, first dielectric layer 293B, conductive via 294B, second conductive trace 295B, and second dielectric layer 296B may share any or all of the characteristics of Redistribution (RD) structure 298, base dielectric layer 291, first conductive trace 292, first dielectric layer 293, conductive via 294, second conductive trace 295, and second dielectric layer 296, respectively, shown in fig. 2B-1 and discussed herein. The example connecting die 216c also includes a second set of connecting die interconnect structures 299 received and/or fabricated on a side of the connecting die 216c opposite the connecting die interconnect structure 217 b. Such a second connection-die interconnect structure 299 may share any or all characteristics with the connection-die interconnect structure 217. In an example implementation, when RD structure 298b is built on a support structure (e.g., such as support structure 290), second connecting die interconnect structure 299 may be formed first, which is then removed or thinned or planarized (e.g., by grinding, peeling, stripping, etching, etc.).

Similarly, any or all of the example methods and structures shown in U.S. patent application No. 15/594,313, which is hereby incorporated by reference in its entirety, may be performed by any such connecting

die

216a, 216b, and/or 216 c.

It should be noted that one or more or all of the second connecting die interconnect structures 299 may be isolated from other circuitry of the connecting die 216c, which connecting die 216c may also be referred to herein as dummy structures (e.g., dummy pillars, etc.), anchor structures (e.g., anchor pillars, etc.), and so forth. For example, any or all of the second connection die interconnect structures 299 may be formed only for anchoring the connection die 216c to a carrier or RD structure or metal pattern at a later step. It should also be noted that one or more or all of the second connecting die interconnect structures 299 may be electrically connected to electrical traces, which may be connected, for example, to electronic device circuitry attached to the die of the connecting die 216 c. Such structures may be referred to, for example, as active structures (e.g., active pillars, etc.), and the like.

In general, block 115 may include receiving, fabricating, and/or preparing to connect dies. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of such receiving, manufacturing, and/or preparing, or any particular characteristics of such connecting dies.

The example method 100 may include receiving, manufacturing, and/or preparing a first carrier at block 120. Block 120 may include receiving, manufacturing, and/or preparing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 120 may share any or all of the characteristics, e.g., with other carrier receiving, manufacturing, and/or preparation steps discussed herein. Various example aspects of block 120 are presented at example 200C of fig. 2C.

Block 120 may, for example, comprise receiving the carrier from an upstream manufacturing process at the same facility or geographic location. Block 120 may also, for example, include receiving a carrier from a vendor (e.g., from a foundry, etc.).

The received, manufactured and/or prepared carrier 221 can include any of a variety of characteristics. For example, the carrier 221 may include a semiconductor wafer or panel (e.g., a typical semiconductor wafer, a low-level semiconductor wafer utilizing lower-level silicon than that used for the functional die discussed herein, etc.). For another example, the carrier 221 may comprise metal, glass, plastic, and the like. The carrier 221 can, for example, be reusable or destructible (e.g., single use, multiple use, etc.).

The carrier 221 may comprise any of a variety of shapes. For example, the carrier may be wafer-shaped (e.g., circular, etc.), may be plate-shaped (e.g., square, rectangular, etc.), and the like. The carrier 221 can have any of a variety of lateral dimensions and/or thicknesses. For example, the carrier 221 may have the same or similar lateral dimensions and/or thicknesses of the functional die and/or die-connected wafer discussed herein. As another example, the carrier 221 may have the same or similar thickness as the functional die and/or the die-connected wafer discussed herein. The scope of the present disclosure is not limited by any particular carrier characteristics (e.g., material, shape, size, etc.).

The example 200C shown at fig. 2C includes a layer of adhesive material 223. The adhesive material 223 may comprise any of various types of adhesives. For example, the adhesive may be a liquid, paste, tape, or the like.

Adhesive 223 may include any of a variety of sizes. For example, the adhesive 223 may cover the entire top side of the first carrier 221. For another example, the adhesive may cover a central portion of the top side of the first carrier 221 while leaving a peripheral edge of the top side of the first carrier 221 uncovered-for another example, the adhesive may cover a respective portion of the top side of the first carrier 221 corresponding in position to a future position of a functional die of a single electronic package.

The thickness of the adhesive 223 may be greater than the height of the second die interconnect structure 214, and thus also greater than the height of the first die interconnect structure 213 (e.g., 5% greater, 10% greater, 20% greater, etc.).

The example vector 221 may share any or all of the characteristics with any of the vectors discussed herein. For example, and without limitation, the carrier may be free of signal distribution layers, but may also include one or more signal distribution layers. Examples of such structures and their formation are illustrated in example 600A of fig. 6A and discussed herein.

In general, block 120 may include receiving, manufacturing, and/or preparing a carrier. Thus, the scope of the present disclosure should not be limited by any particular conditions under which a vector is received, any particular manner of making a vector, and/or the nature of any particular manner of preparing such a vector for use.

Example method 100 may include coupling (or mounting) the functional die to a carrier (e.g., a top side coupled to a non-conductive carrier, a metal pattern coupled on the top side of the carrier, an RD structure coupled on the top side of the carrier, etc.) at block 125. Block 125 may include performing such coupling in any of a variety of ways, non-limiting examples of which are provided herein. For example, the block 125 may share any or all characteristics, such as with other die mounting steps discussed herein. Various example aspects of block 125 are presented in example 200D shown at fig. 2D.

For example, functional dies 201-204 (e.g., any of functional dies 211 and 212) may be received as separate dies. As another example, one or more of the functional dies 201-204 may be received on a single wafer, one or more of the functional dies 201-204 may be received on multiple respective wafers (e.g., as shown at examples 200A-1 and 200A-3, etc.), and so forth. In the context of receiving one or both of the functional dies in wafer form, the functional dies may be singulated from the wafer. It should be noted that if any of the functional dies 201-204 are received on a single MPW, such functional dies may be singulated out of the wafer as an attached device (e.g., connected with bulk silicon).

Block 125 may include placing functional dies 201-204 in adhesive layer 223. For example, the second die interconnect structure 214 and the first die interconnect structure 213 may be fully (or partially) inserted into the adhesive layer 223. As discussed herein, the adhesive layer 223 may be thicker than the height of the second die interconnect structure 214 such that when the bottom surfaces of the dies 201-204 contact the top surface of the adhesive layer 223, the bottom end of the second die interconnect structure 214 does not contact the carrier 221. However, in alternative embodiments, the adhesive layer 223 may be thinner than the height of the second die interconnect structure 214, but still thick enough to cover at least a portion of the first die interconnect structure 213 when the dies 201-204 are placed on the adhesive layer 223.

The block 125 may include placing the functional dies 201-204 using, for example, a die pick and place machine.

It should be noted that although the illustrations herein generally set the size and shape of the functional dies 201-204 (and their interconnect structures) to be similar, such symmetry is not required. For example, the functional dies 201-204 may have different respective shapes and sizes, may have different types and/or numbers of interconnect structures, and so on. It should also be noted that the functional dies 201-204 (or any so-called functional die discussed herein) may be semiconductor dies, but may also be any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies, packaged dies, etc.). Accordingly, the scope of the present disclosure should not be limited by characteristics of the functional dies 201-204 (or any so-called functional die discussed herein).

In general, block 125 may include coupling (or mounting) the functional die to a carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such coupling or any particular characteristics of such functional die, interconnect structure, carrier, attachment means, etc.

The example method 100 may include encapsulating at block 130. Block 130 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 130 are presented in example 200E shown in fig. 2E. The block 130 may share any or all of the characteristics, for example, with other envelopes discussed herein.

Block 130 may, for example, comprise performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to singulation to cut individual modules. Referring to example implementation 200E shown in fig. 2E, encapsulation material 226' may cover a top side of adhesive 223, a top side of functional dies 201-204, at least a portion (or all) of lateral side surfaces of functional dies 201-204, and so on. The encapsulation material 226' may also, for example, cover any portion of the second die interconnect structure 214, the first die interconnect structure 213, and the bottom surface of the functional die 201-204 exposed from the adhesive 223 (if any of such components are exposed).

The encapsulant material 226' may include any of various types of encapsulant materials, such as a molding material, any dielectric material presented herein, and the like.

Although encapsulation material 226' (as shown in fig. 2E) is shown covering the top sides of functional dies 201-204, any or all of such top sides (or any corresponding portions of such top sides) may be exposed from encapsulation material 226 (as shown in fig. 2F). Block 130 may, for example, include initially forming encapsulation material 226 with the top side of the die exposed (e.g., using film-assisted molding techniques, die-seal molding techniques, etc.); forming an encapsulation material 226', followed by a thinning process (e.g., performed at block 135) to thin the encapsulation material 226' enough to expose the top side of any or all of the functional dies 201-204; an encapsulation material 226 'is formed, followed by a thinning process (e.g., performed at block 135) to thin the encapsulation material but still leave a portion of encapsulation material 226' covering the top sides of any or all of functional dies 201-204 (or any corresponding portions thereof), and so on.

Generally, the block 130 may include an envelope. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such encapsulation or characteristics of any particular type of encapsulating material or configuration thereof.

The example method 100 may include grinding the encapsulation material at block 135. Block 135 may include performing such grinding (or any thinning or planarization) in any of a variety of ways, non-limiting examples of which are provided herein. The block 135 may share any or all of the characteristics, for example, with other grinding (or thinning) blocks (or steps) discussed herein. Various example aspects of block 135 are presented in example 200F shown in fig. 2F.

As discussed herein, in various example embodiments, the encapsulant material 226' may be initially formed to a thickness greater than the final desired thickness. In such example implementations, block 135 may be performed to grind (or otherwise thin or planarize) the encapsulation material 226'. In the example 200F shown in fig. 2F, the encapsulant material 226' has been milled to form the encapsulant material 226. The top surface of the milled (or thinned or planarized) encapsulant material 226 is coplanar with the top surfaces of the functional dies 201-204, which are thus exposed from the encapsulant material 226. It should be noted that in various example implementations, one or more of the functional dies 201-204 may be exposed while one or more of the functional dies 201-204 may remain covered by the encapsulation material 226. It should be noted that such grinding operations, if performed, do not require exposing the top sides of functional dies 201-204.

In an example embodiment, block 135 may include grinding (or thinning or planarizing) encapsulant material 226' and the back side of any or all of functional dies 201-204 to achieve coplanarity of the top surface of encapsulant material 226 with one or more of functional dies 201-204.

Generally, block 135 may include grinding the encapsulation material. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such grinding (or thinning or planarizing).

The example method 100 may include attaching a second carrier at block 140. The block 140 may include attaching the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 140 may share any or all of the characteristics with any of the carrier attachments discussed herein. Fig. 2G shows various example aspects of block 140.

As shown in example 200G of fig. 2G, a second carrier 231 may be attached to the top side of encapsulation material 226 and/or the top sides of functional dies 201-204. It should be noted that the assembly may still be in wafer (or panel) form at this point. The second carrier 231 may include any of a variety of characteristics. For example, the second carrier 231 may include a glass carrier, a silicon (or semiconductor) carrier, a metal carrier, a plastic carrier, and the like. The block 140 may include attaching (or coupling or mounting) the second carrier 231 in any of a variety of ways. For example, block 140 may include attaching second carrier 231 using an adhesive, using a mechanical attachment mechanism, using a vacuum attachment, and the like.

In general, block 140 may include attaching a second carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of attaching the carrier or characteristics of any particular type of carrier.

The example method 100 may include removing the first carrier at block 145. Block 145 may include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 145 may share any or all of the characteristics with any of the carrier removal processes discussed herein. Various example aspects of block 145 are presented in example 200H shown in fig. 2H.

For example, example 200H of fig. 2H shows the removal of the first carrier 221 (e.g., as compared to example 200G of fig. 2G). Block 145 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal release, laser release, etc.).

As another example, block 145 may include removing the adhesive layer 223 utilized at block 125 to couple the functional dies 201-204 to the first carrier 221. For example, such an adhesive layer 223 may be removed together with the first carrier 221 in a single-step or multi-step process. For example, in an example embodiment, the block 145 may include pulling the first carrier 221 from the functional dies 201-204 and the encapsulation material 226, wherein the adhesive (or a portion thereof) is removed with the first carrier 221. As another example, the block 145 may include removing the adhesive layer 223 (e.g., the entire adhesive layer 223 and/or any portion of the adhesive layer 223 remaining after removing the first carrier 221, etc.) from the functional dies 201-204 (e.g., from the bottom surfaces of the functional dies 201-204, from the first die 213 and/or the second die 214 interconnect structures, etc.) and the encapsulation material 226 using a solvent, thermal energy, optical energy, or other cleaning technique.

In general, block 145 may include removing the first carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of removing the carrier or characteristics of any particular type of carrier.

The example method 100 may include attaching (or coupling or mounting) a connection die to the functional die at block 150. Block 150 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. The block 150 may share any or all of the characteristics, for example, with any of the die attach processes discussed herein. Various example aspects of block 150 are presented at fig. 2I.

For example, the die interconnect structures 217 of the first connection die 216b (e.g., any or all of such connection dies) may be mechanically and electrically connected to the respective first die interconnect structures 213 of the first and second functional dies 201, 202.

Such interconnect structures may be connected in any of a variety of ways. The connection may be performed by welding, for example. In example embodiments, the first die interconnect structure 213 and/or the connection die interconnect structure 217 may include a solder cap (or other solder structure) that may be reflowed to perform the connection. Such solder caps may be reflowed, for example, by mass reflow, Thermal Compression Bonding (TCB), and the like. In another example implementation, the connection may be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding instead of utilizing solder. Examples of such connections are provided in U.S. patent application No. 14/963,037, filed on 8.12.2015 and entitled "Transient Interface Gradient Bonding for Metal Bonds" and U.S. patent application No. 14/989,455, filed on 6.2016.1.4 and entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing the same", each of which is hereby incorporated by reference in its entirety. The first die interconnect structure 213 may be attached to the connecting die interconnect structure 217 using any of a variety of techniques (e.g., mass reflow, Thermal Compression Bonding (TCB), direct metal-to-metal intermetallic bonding, conductive adhesive, etc.).

As example 200I shows, first die interconnect structures 213 of first connection die 201 are connected to respective connection die interconnect structures 217 of connection die 216b, and first die interconnect structures 213 of second connection die 202 are connected to respective connection die interconnect structures 217 of connection die 216 b. When connected, connection die 216B provides electrical connections between the various die interconnect structures of first functional die 201 and second functional die 202 via RD structure 298 (e.g., as shown by example 200B-3 of FIG. 2B-1, etc.).

In the example 200I illustrated in fig. 2I, the height of the second die interconnect structure 214 may be, for example, greater than (or equal to) the combined height of the first die interconnect structure 213, the connecting die interconnect structure 217, the RD structure 298, and any supporting layer 290b of the connecting die 216 b. Such height differences may, for example, provide space for a buffer material (e.g., underfill, etc.) between the connection die 216b and another substrate (e.g., as shown by example 200N of fig. 2N and discussed herein).

It should be noted that although example bonded die (216B) is shown as a single-sided bonded die (e.g., similar to example bonded die 216B of fig. 2B-1), the scope of the present disclosure is not so limited. For example, any or all such example-connected dies 216B may be double-sided (e.g., similar to example-connected die 216c of fig. 2B-2).

In general, block 150 may include attaching (or coupling or mounting) a connection die to a functional die. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such attachment or characteristics of any particular type of attachment structure.

Example method 100 may include underfilling the connected die at block 155. Block 155 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are provided herein. Block 155 may share any or all of the characteristics, for example, with any of the underfill processes discussed herein. Various example aspects of block 155 are presented in the example 200J shown in fig. 2J.

It should be noted that an underfill may be applied between connection die 216b and functional dies 201-204. In the context of utilizing a pre-applied underfill (PUF), such PUF may be applied to the functional dies 201-204 and/or to the connection die 216b prior to coupling the connection die interconnect structure 217 to the first die interconnect structure 213 of the functional dies 201-204 (e.g., at block 150).

After the attachment performed at block 150, block 155 may include forming an underfill (e.g., a capillary underfill, etc.). As shown in the example implementation 200J of fig. 2J, the underfill material 223 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the underside of the connection die 216b (e.g., the orientation as shown in fig. 2J), and/or at least a portion, if not all, of the lateral sides of the connection die 216 b. The underfill material 223 may also surround the connection die interconnect structure 217, and surround the first die interconnect structure 213 of the functional dies 201 to 204, for example. The underfill material 223 may additionally cover the top sides (as oriented as shown in fig. 2J) of the functional dies 201-204 in the region corresponding to the first die interconnect structure 213, for example.

It should be noted that in various example implementations of example method 100, the underfill performed at block 155 may be skipped. For example, underfilling the connection die may be performed at another block (e.g., at block 175, etc.). Also for example, such underfill may be omitted entirely.

In general, block 155 may include underfilling the connected die. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such underfilling or characteristics of any particular type of underfilling.

Example method 100 may include removing the second carrier at block 160. Block 160 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 160 may share any or all of the characteristics with any of the carrier removal processes discussed herein (e.g., with respect to block 145, etc.). The example 200K shown in fig. 2K presents various example aspects of the block 160.

For example, the example implementation 200K shown in fig. 2K does not include the second carrier 231 of the example implementation 200J shown in fig. 2J. It should be noted that such removal may, for example, include cleaning the surface, removing the adhesive (if used), and the like.

Generally, block 160 may include removing the second carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such carrier removal or characteristics of any particular type of carrier or carrier material being removed.

The example method 100 may include singulation at block 165. Block 165 may include performing such singulation cuts in any of a variety of ways, non-limiting examples of which are discussed herein. The block 165 may share any or all of the characteristics, for example, with any of the singulation cuts discussed herein. The example 200L shown in fig. 2L presents various example aspects of the block 165.

As discussed herein, the example assemblies shown herein may be formed on a wafer or panel that includes a plurality of such assemblies (or modules). For example, the example 200K shown in fig. 2K has two assemblies (left and right) joined together by an encapsulant material 226. In such example implementations, the wafer or panel may be singulated and cut (or diced) to form individual assemblies (or modules). In the example 200L of fig. 2L, the encapsulant material 226 is sawn (or cut, snapped, stretch-broken, diced, or otherwise cut, etc.) into two

encapsulant material portions

226a and 226b, each corresponding to a respective electronic device.

In the example implementation 200L shown in fig. 2L, only the encapsulation material 226 needs to be cut. However, the block 165 may include cutting any of a variety of materials, if present along a singulation cut line (or cut line). For example, the block 165 may include trimming underfill material, carrier material, functional and/or connection die material, substrate material, and the like.

In general, block 165 may include singulation cuts. Accordingly, the scope of the present disclosure should not be limited by any particular manner of singulation.

The example method 100 may include mounting to a substrate at block 170. Block 170 may, for example, include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, the block 170 may share any or all of the characteristics with any of the mounting (or attachment) steps discussed herein (e.g., attaching interconnect structures, attaching die backside, etc.). Various example aspects of block 170 are presented in example 400M shown in fig. 4M.

The substrate 288 can include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, the substrate 288 may include a package substrate, an interposer, a motherboard, a printed wiring board, a functional semiconductor die, a stacked redistribution structure of another device, and so forth. For example, the substrate 288 may comprise a coreless substrate, an organic substrate, a ceramic substrate, or the like. The substrate 288 can, for example, include one or more dielectric layers (e.g., organic and/or inorganic dielectric layers) and/or conductive layers formed on a semiconductor (e.g., silicon, etc.) substrate, a glass or metal substrate, a ceramic substrate, etc. The substrate 288 may share any or all of the characteristics with, for example, the RD structure 298 of FIG. 2B-1, the RD structure 298B of FIG. 2B-2, any of the RD structures discussed herein, and the like. The substrate 288 may, for example, comprise an individual package substrate or may comprise a plurality of substrates coupled together (e.g., in a panel or wafer) that may later be singulated for cutting.

In the example 200M shown in fig. 2M, the block 170 may include soldering (e.g., with mass reflow, thermocompression bonding, laser welding, etc.) the second die interconnect structures 214 of the functional dies 201-202 to respective pads (e.g., bond pads, traces, pads, etc.) or other interconnect structures (e.g., posts, rods, balls, bumps, etc.) of the substrate 288.

It should be noted that in example implementations in which connection die 216b is a double-sided connection die similar to connection die 216c, block 170 may also include respective pads or other interconnect structures that connect second set of connection die interconnect structures 299 to substrate 288. However, in the example 200M of fig. 2M, the connection die 216b is a single-sided connection die. It should be noted that, as discussed herein, because second die interconnect structure 214 of functional dies 201-202 is taller than the combined height of first die interconnect structure 213, connection die interconnect structure 217, and support layer 290b of connection die 216b, there is a gap between the back side of connection die 216b (the underside of connection die 216b in fig. 2M) and the top side of substrate 288. As shown in fig. 2N, this gap may be filled with an underfill.

In general, block 170 includes mounting (or attaching or coupling) the singulated and cut assembly (or module) at block 165 to a substrate. Thus, the scope of the present disclosure should not be limited by characteristics of any particular type of mounting (or attachment) or characteristics of any particular mounting (or attachment) structure.

The example method 100 may include, at block 175, underfilling between the substrate and the assembly (or module) mounted thereto at block 170. Block 175 may include performing underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 175 may, for example, share any or all characteristics with any underfill (or encapsulation) process discussed herein (e.g., with respect to block 155, etc.). Various aspects of block 175 are presented in the example 200N shown in fig. 2N.

Block 175 may, for example, include performing a capillary underfill or injected underfill process after the mounting is performed at block 170. For another example, in the context of utilizing a pre-applied underfill (PUF), such PUF may be applied to a substrate, a metal pattern of the substrate, and/or interconnect structures thereof prior to such mounting. Block 175 may also include performing such underfill using a molded underfill process.

As shown in the example implementation 200N of fig. 2N, an underfill material 291 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the top side of the substrate 288. The underfill material 291 may also, for example, surround the second die interconnect structures 214 (and/or corresponding substrate pads) of the functional dies 201-202. Underfill material 291 may, for example, cover the bottom sides of functional dies 201-202, the bottom side of connection die 216b, and the bottom side of encapsulation material 226 a. Underfill material 291 may also, for example, cover lateral side surfaces of connection die 216b and/or exposed lateral surfaces of underfill 223 between connection die 216b and functional dies 201-202. Underfill material 291 may, for example, cover encapsulation material 226a and/or lateral side surfaces (e.g., all or a portion) of functional dies 201-202.

In example embodiments in which underfill 223 is not formed, underfill material 291 may be formed in place of underfill 223. For example, referring to example 200N, underfill material 223 may be replaced with more underfill material 291 in example 200N.

In example embodiments in which underfill 223 is formed, underfill material 291 may be a different type of underfill material than underfill material 223. In another example embodiment, both underfill

materials

223 and 291 may be the same type of material.

As with block 155, block 175 may also be skipped, e.g., leaving a space at another block to be filled with another underfill (e.g., a molded underfill, etc.).

Typically, block 175 includes performing an underfill. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular type of underfill or characteristics of any particular underfill material.

Example method 100 may include performing continued processing at block 190. Such continued processing may include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, block 190 may comprise returning the execution flow of example method 100 to any of its blocks. Also for example, block 190 may include directing the execution flow of example method 100 to any other method block (or step) discussed herein (e.g., with respect to example method 300 of fig. 3, example method 500 of fig. 5, etc.).

For example, the block 190 may include forming an interconnect structure 299 (e.g., conductive balls, bumps, pillars, etc.) on a bottom side of the substrate 288.

For another example, as illustrated by example 200O of fig. 2O, block 190 may include forming an encapsulation material 225. Such encapsulation material 225 may, for example, cover a top side of the substrate 288, lateral sides of the underfill 224, lateral sides of the encapsulation material 226a, and/or lateral sides of the functional dies 201-202. In the example 200O illustrated in fig. 2O, the top side of encapsulant material 225, the top side of encapsulant material 226a, and/or the top sides of functional dies 201-202 may be coplanar.

As discussed herein, the underfill 224 may not be formed (e.g., the underfill as formed at block 175). In this case, the encapsulant material 225 may replace the underfill. An example 200P of such a structure and method is provided at fig. 2P. With respect to the example implementation 200O shown in fig. 2O, in the example implementation 200P, the underfill 224 of the example implementation 200O is replaced with an encapsulation material 225 as the underfill.

As discussed herein, the underfill 223 (e.g., the underfill as formed at block 155) and the underfill 224 may not be formed. In this case, the encapsulating material 225 may replace them. An example implementation 200Q of such structures and methods is provided at fig. 2Q. With respect to the example implementation 200P shown in fig. 2P, in the example implementation 200Q, the underfill 223 of the example implementation 200P is replaced with an encapsulation material 225.

It should be noted that in any of the

example implementations

200O, 200P, and 200Q shown in fig. 2O, 2P, and 2Q, the lateral sides of the encapsulation material 225 and the substrate 288 may be coplanar.

In the example method 100 shown in fig. 1 and 2A-2Q, various die interconnect structures (e.g., the first die interconnect structure 213, the second die interconnect structure 214, the connecting die interconnect structure 217 (and/or 299), etc.) are typically formed during the receiving, manufacturing, and/or preparation processes of the die. For example, such various die interconnect structures may typically be formed prior to their respective dies being integrated into an assembly. However, the scope of the present disclosure should not be limited by the timing of such example implementations. For example, any or all of the various die interconnect structures may be formed after their respective dies are integrated into an assembly. An example method 300 showing the formation of a die interconnect structure at different stages will now be discussed.

Fig. 3 shows a flow diagram of an example method 300 of manufacturing an electronic device (e.g., a semiconductor package, etc.). The example method 300 may, for example, share any or all characteristics with any other example methods discussed herein (e.g., the example method 100 of fig. 1, the example method 500 of fig. 5, the example method 700 of fig. 7, etc.). Fig. 4A-4N show cross-sectional views illustrating an example electronic device (e.g., semiconductor package, etc.) and an example method of manufacturing the example electronic device, according to various aspects of the present disclosure. Fig. 4A-4N may illustrate example electronic devices, e.g., in various blocks (or steps) of method 300 of fig. 3. Fig. 3 and 4A-4N will now be discussed together. It should be noted that the order of the example blocks of the method 300 may be varied without departing from the scope of the present disclosure.

The example method 300 may begin execution at block 305. The method 300 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, the method 300 may begin executing automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, and so forth. As another example, the method 300 may begin execution in response to an operator command starting. Additionally, for example, the method 300 may begin execution in response to receiving an execution stream from any other method block (or step) discussed herein.

The example method 300 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 310. Block 310 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 310 may share any or all of the characteristics with block 110 of the example method 100 shown in fig. 1 and discussed herein. Various aspects of block 310 are presented in examples 400A-1 through 400A-4 shown in FIG. 4A.

Block 310 may, for example, comprise receiving multiple functional dies from an upstream manufacturing process at the same facility or geographic location. Block 310 may also include, for example, receiving a functional die from a vendor (e.g., from a foundry). Block 310 may also include, for example, forming any or all of the features of a plurality of functional dies.

In an example embodiment, the block 310 may share any or all of the characteristics with the block 110 of the example method 100 of fig. 1, but without the first die interconnect structure 213 and the second die interconnect structure 214. It will be appreciated that such die interconnect structures may be formed later in example method 300 (e.g., at block 347, etc.). Although not shown in fig. 4A, each of the functional dies 411-412 may include, for example, a die pad and/or an under bump metallization structure, upon which such a die interconnect structure may be formed.

The functional dies 411-412 shown in fig. 4A may, for example, share any or all characteristics with the functional dies 211-212 shown in fig. 2A (e.g., without the first die interconnect structure 213 and the second die interconnect structure 214). For example, but not limiting of, the functional dies 411-412 can include characteristics of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

In general, block 310 may include receiving, fabricating, and/or preparing a plurality of functional dies. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such receiving, manufacturing, and/or preparing, nor by any particular characteristics of such functional die.

Example method 300 may include receiving, fabricating, and/or preparing a connection die at block 315. Block 315 may include receiving, fabricating, and/or preparing one or more connected dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 315 may share any or all of the characteristics with block 115 of the example method 100 shown in fig. 1 and discussed herein. Various example aspects of block 315 are presented in examples 400B-1 and 400B-2 shown in FIG. 4B.

The connection dies 416a and/or 416b (or wafers thereof) may, for example, include a connection die interconnect structure 417. The connection-die interconnect structure 417 may include any of a variety of characteristics. For example, the formation of the connection-die interconnect structure 417 and/or any aspect thereof may share any or all of the characteristics with the connection-die interconnect structure 217 and/or formation thereof shown in fig. 2B-1 through 2B-2 and discussed herein.

The connector dies 416a and/or 416B (or wafers thereof) may be formed in any of a variety of ways, non-limiting examples of which are provided herein, e.g., with respect to the connector dies 216a, 216B, and/or 216c of fig. 2B-1 through 2B-2.

In general, block 315 may include receiving, fabricating, and/or preparing to connect dies. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such receiving, manufacturing, and/or preparing, nor by any particular characteristics of such connected dies.

The example method 300 may include receiving, manufacturing, and/or preparing a first carrier at block 320. Block 320 may include receiving, manufacturing, and/or preparing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. Block 320 may share any or all of the characteristics, for example, with other carrier receiving, manufacturing, and/or preparation steps discussed herein (e.g., with block 120 of the example method 100 of fig. 1, etc.).

Various example aspects of block 320 are presented in example 400C shown in fig. 4C. For example, the carrier 421 may share any or all of the characteristics with the carrier 221 of fig. 2C. For another example, adhesive 423 may share any or all of the characteristics with adhesive 223 of fig. 2C. It should be noted, however, that adhesive 423 need not be as thick as adhesive 223, as adhesive 423 does not receive the die interconnect structure of the functional die (e.g., at block 325).

In general, block 320 may include receiving, manufacturing, and/or preparing a first carrier. Thus, the scope of the present disclosure should not be limited by any particular conditions under which a vector is received, any particular manner of making a vector, and/or the nature of any particular manner of preparing such a vector for use.

Example method 300 may include coupling (or mounting) the functional die to a carrier (e.g., to a top side of a non-conductive carrier, to a metal pattern on the top side of the carrier, to an RD structure on the top side of the carrier, etc.) at block 325. Block 325 may include performing such coupling in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 325 may share any or all of the characteristics, e.g., with other die mounting steps discussed herein (e.g., at block 125 of the example method 100 of fig. 1, etc.).

Various example aspects of block 325 are presented in example 400D shown in fig. 4D. The instantiation 400D may share any or all of the characteristics with the instantiation 200D of FIG. 2D. For example, functional dies 401-404 (e.g., instances of dies 411 and/or 412) may share any or all of the characteristics (e.g., die

interconnect structures

213 and 214 do not extend into adhesive 223) with functional dies 201-204 of fig. 2D (e.g., instances of dies 211 and/or 212).

In example 400D, functional dies 401-404 are shown with respective active sides coupled to adhesive 423, although the scope of the present disclosure is not limited to such orientations. In alternative implementations, the respective inactive sides of the functional dies 401-404 may be mounted to the adhesive 423 (e.g., where the functional dies 401-404 may have through-silicon vias or other structures to later connect to a connection die, etc.).

In general, block 325 may include coupling the functional die to a carrier. Thus, the scope of this disclosure should not be limited by characteristics of any particular manner of performing such coupling.

The example method 300 may include encapsulating at block 330. Block 330 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 330 may share any or all of the characteristics with other envelopes discussed herein (e.g., with block 130 of the example method 100 of fig. 1, etc.).

Various example aspects of block 330 are presented in example 400E shown in fig. 4E. For example, the encapsulation material 426 '(and/or formation thereof) may share any or all of the characteristics with the encapsulation material 226' (and/or formation thereof) of fig. 2E.

Generally, the block 330 may include an envelope. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such encapsulation, characteristics of any particular type of encapsulating material, or the like.

The example method 300 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 335. Block 335 may include performing such grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 335 may share any or all of the characteristics with other grinding (or thinning or planarizing) discussed herein (e.g., with block 135 of the example method 100 of fig. 1, etc.).

Various example aspects of block 335 are presented in example 400F shown in fig. 4F. Example the milled (or thinned or planarized, etc.) encapsulant material 426 (and/or formation thereof) may share any or all of the characteristics with the encapsulant material 226 (and/or formation thereof) of fig. 2F.

Generally, the block 335 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such grinding (or thinning or planarizing).

The example method 300 may include attaching a second carrier at block 340. Block 340 may include attaching the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 340 may share any or all of the characteristics with any carrier attachment discussed herein (e.g., with block 140 of the example method 100 of fig. 1, etc.).

Various example aspects of block 340 are shown in the example 400G shown in fig. 4G. Second carrier 431 (and/or its attachment) may share any or all of the characteristics with second carrier 231 of fig. 2G, for example.

In general, block 340 may include attaching a second carrier. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such attachment and/or characteristics of any particular type of second carrier.

The example method 300 may include removing the first carrier at block 345. Block 345 may include removing the first carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 345 may share any or all features with any carrier removal discussed herein (e.g., with block 145 of the example method 100 shown in fig. 1, etc.).

Various example aspects of block 345 are shown in the example 400H shown in FIG. 4H-1. For example, with respect to example 400G, the first carrier 421 has been removed.

Generally, block 345 may include removing the first carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such removal.

Example method 300 may include, at block 347, forming an interconnect structure. Block 347 may include forming the interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 347 may share any or all of the characteristics with other interconnect structure formation processes (or steps or blocks) discussed herein (e.g., block 110 of the example method 100 shown with respect to fig. 1 and discussed herein, etc.).

Various example aspects of block 347 are shown at example 400H-2 of FIG. 4H-2. The first die interconnect structure 413 of fig. 4H-2 (and/or formation thereof) may share any or all of the characteristics with the first die interconnect structure 213 of fig. 2A (and/or formation thereof). Similarly, the second die interconnect structure 414 of fig. 4H-2 (and/or formation thereof) may share any or all of the characteristics with the second die interconnect structure 214 of fig. 2A (and/or formation thereof).

Example embodiment 400H-2 includes a passivation layer 417 (or repassivation layer). Although not shown in the example implementation of fig. 2A and/or other example implementations presented herein, such example implementations may also include such passivation layers 417 (e.g., between the functional die and the die interconnect structure and/or around the base of the die interconnect structure, between the connecting die and the connecting die interconnect structure and/or around the base of the connecting die interconnect structure, etc.). For example, in the context of block 347 having not yet formed such passivation layer 417, block 347 may include forming such passivation layer 417. Note that the passivation layer 417 may also be omitted.

In example embodiments, such as where the functional die is received or formed through an outer inorganic dielectric layer, the passivation layer 417 may include an organic dielectric layer (e.g., including any of the organic dielectric layers discussed herein).

Passivation layer 417 (and/or formation thereof) may include characteristics of any passivation (or proton) layer (and/or formation thereof) discussed herein. The first die interconnect structure 413 and the second die interconnect structure 414 may be electrically connected to the functional dies 401 to 404, e.g., through respective holes in the passivation layer 417.

Although passivation layer 417 is shown over molding layer 426 and functional dies 401 through 404, passivation layer 417 may also be formed over only functional dies 401 through 404 (e.g., at block 310). In such example embodiments, an outer surface of the passivation layer 417 (e.g., an upward facing surface of the passivation layer 417 in fig. 4H-2) may be coplanar with a corresponding surface of the encapsulation material 426 (e.g., an upward facing surface of the encapsulation material 426 in fig. 4H-2).

In general, block 347 may include forming an interconnect structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of such formation or any particular characteristics of the interconnect structure.

The example method 300 may include attaching (or coupling or mounting) a connection die to the functional die at block 350. Block 350 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. For example, the block 350 may share any or all of the characteristics, such as with any of the die-attach discussed herein (e.g., with the block 150 of the example method 100 of fig. 1, etc.).

Various example aspects of block 350 are presented in example 400I shown in FIG. 4I. Connection die 416b, functional dies 401-404, and/or the connection of such dies to each other may share any or all characteristics with connection die 216b, functional dies 201-204, and/or the connection of such dies to each other, for example, of example 200I shown in fig. 2I.

In general, block 350 may include attaching a connecting die to the functional die. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such attachment and/or characteristics of any particular structure for performing such attachment.

The example method 300 may include underfilling the connection die at block 355. Block 355 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are provided herein. Block 355 may, for example, share any or all of the characteristics with any of the underfills discussed herein (e.g., with block 155 and/or block 175 of the example method 100 of fig. 1, etc.).

Various example aspects of block 355 are presented in example 400J shown in fig. 4J. For example, the underfill 423 of fig. 4J (and/or formation thereof) may share any or all of the characteristics with the underfill 223 of fig. 2J (and/or formation thereof). It should be noted that various example implementations may omit performing such underfill, as with any underfill discussed herein.

In general, block 355 may include underfilling the connected die. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such underfill or characteristics of any particular type of underfill material.

The example method 300 may include removing the second carrier at block 360. Block 360 may include removing the second carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 360 may share any or all characteristics with any carrier removal discussed herein (e.g., with block 145 and/or block 160, with block 345, etc. of the example method 100 of fig. 1).

Various example aspects of block 360 are presented in example 400K shown in fig. 4K. For example, comparing fig. 4K with fig. 4J, the second carrier 431 has been removed.

Generally, block 360 may include removing the second carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such removal.

The example method 300 may include singulation cutting at block 365. Block 365 may include performing such singulation cuts in any of a variety of ways, non-limiting examples of which are discussed herein. The block 365 may, for example, share any or all characteristics with any of the singulation cuts discussed herein (e.g., as discussed with respect to block 165 of the example method 100 of fig. 1, etc.).

Various example aspects of block 365 are presented in example 400L shown in FIG. 4L. The singulated cut structures (e.g., corresponding to the two

encapsulant portions

426a and 426b) may share any or all of the characteristics, for example, with the singulated cut structures of fig. 2L (e.g., corresponding to the two

encapsulant portions

226a and 226 b).

In general, block 365 may include singulation cuts. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of singulation.

The example method 300 may include mounting to a substrate at block 370. Block 370 may, for example, comprise performing such mounting (or coupling or attaching) in any of a variety of ways, non-limiting examples of which are provided herein. For example, the block 370 may share any or all of the characteristics with any of the installations (or couplings or attachments) discussed herein (e.g., block 170 of the example method 100 shown with respect to fig. 1, etc.).

Various example aspects of block 370 are presented in example 400M shown in fig. 4M. For example, the substrate 488 (and/or attachment to such substrate 288) may share any or all of the characteristics with the substrate 288 of the example 200M of fig. 2M (and/or attachment to such substrate 288).

In general, block 370 may include mounting to a substrate. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of mounting to a substrate or characteristics of any particular type of substrate.

The example method 300 may include, at block 375, underfilling between the substrate and the assembly (or module) mounted thereto at block 370. Block 375 may include performing underfill in any of a variety of ways, non-limiting examples of which are provided herein. Block 375 may share any or all characteristics, for example, with any of the underfill (or encapsulation) processes discussed herein (e.g., with respect to block 355, with respect to

blocks

155 and 175 of the example method 100 of fig. 1, etc.).

Various aspects of block 375 are presented in the example 400N shown in fig. 4N. The underfill 424 (and/or formation thereof) may share any or all of the characteristics, for example, with the example underfill 224 (and/or formation thereof) shown in the example 200N of fig. 2N. It should be noted that as with any of the underfilling discussed herein, the underfilling of block 375 may be skipped or may be performed at a different point in the method.

In general, block 375 may include underfilling between the substrate and the assembly mounted to the substrate. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of mounting to a substrate or characteristics of any particular type of substrate.

Example method 300 may include performing continued processing at block 390. Such continued processing may include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, block 390 may share any or all of the characteristics with block 190 of the example method 100 of fig. 1 discussed herein.

For example, block 390 may include returning the execution flow of example method 300 to any of its blocks. Also for example, block 390 may include directing the flow of execution of example method 300 to any other method block (or step) discussed herein (e.g., with respect to example method 100 of fig. 1, example method 500 of fig. 5, example method 700 of fig. 7, etc.).

For example, the block 390 may include forming interconnect structures 499 (e.g., conductive balls, bumps, posts, etc.) on the bottom side of the substrate 488.

Also for example, as illustrated by the example 200O of fig. 2O, the example 200P of fig. 2P, and the example 200Q of fig. 2Q, the block 390 may include forming an encapsulation material and/or an underfill (or skipping forming an encapsulation material and/or an underfill).

In various example implementations discussed herein, the functional die is mounted to the carrier prior to attaching the connection die to the functional die. The scope of the present disclosure is not limited to such an installation order. A non-limiting example will now be presented in which the connector dies are mounted to a carrier prior to attachment of the connector dies to the functional dies.

Fig. 5 shows a flow diagram of an example method 500 of manufacturing an electronic device, in accordance with various aspects of the present disclosure. The example method 500 may share any or all characteristics, for example, with any other example methods discussed herein (e.g., the example method 100 of fig. 1, the example method 300 of fig. 3, the example method 700 of fig. 7, etc.). Fig. 6A-6M show cross-sectional views illustrating example electronic devices (e.g., semiconductor packages, etc.) and example methods of manufacturing example electronic devices, according to various aspects of the present disclosure. Fig. 6A-6M may, for example, illustrate example electronic devices at various blocks (or steps) of method 500 of fig. 5. Fig. 5 and 6A-6M will now be discussed together. It should be noted that the order of the example blocks of method 500 may be varied without departing from the scope of the present disclosure.

The example method 500 may begin execution at block 505. Method 500 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, method 500 may begin executing automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, and so forth. As another example, method 500 may begin execution in response to an operator command starting. Additionally, for example, the method 500 may begin execution in response to receiving an execution stream from any other method block (or step) discussed herein.

Example method 500 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 510. Block 510 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 510 may share any or all of the characteristics with block 310 of the example method 300 shown in fig. 3 and discussed herein. Various aspects of block 510 are presented in examples 400A-1 through 400A-4 shown in FIG. 4A. It should be noted that block 510 may also share any or all of the characteristics, for example, with block 110 of the example method 100 shown in fig. 1 and discussed herein.

Functional dies 611a and 612A (and/or formation thereof) as shown in many of figures 6A-6M may share any or all of the characteristics with, for example, functional dies 411 and 412 (and/or formation thereof) of figure 4A, with functional dies 211-212 (and/or formation thereof) of figure 2A, and so on. For example, and without limitation, functional dies 611a and 612a may include characteristics of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

In general, block 510 may include receiving, fabricating, and/or preparing a plurality of functional dies. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such receiving and/or fabrication, nor by any particular characteristics of such functional die.

Example method 500 may include receiving, fabricating, and/or preparing a connection die at block 515. Block 515 may include receiving and/or fabricating a plurality of connected dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 515 may share any or all of the characteristics with block 115 of the example method 100 shown in fig. 1 and discussed herein. Various example aspects of block 515 are presented in examples 200B-1 and 200B-7 shown in FIGS. 2B-1 through 2B-2. It should be noted that block 515 may also share any or all of the characteristics, such as with block 315 of the example method 300 shown in fig. 3 and discussed herein.

The connecting die 616B and the connecting die interconnect structure 617 (and/or formation thereof) as shown in many of fig. 6A-6M may, for example, share any or all of the characteristics with the connecting die 216B and the connecting die interconnect structure 217 (and/or formation thereof) of fig. 2B-1-2.

It should be noted that the connecting die interconnect structure 617 (and/or formation thereof) may, for example, share any or all of the characteristics with the first die interconnect structure 213 (and/or formation thereof). For example, in an example embodiment, instead of forming a first die interconnect structure, such as first die interconnect structure 213 of fig. 2A, on functional die 211/212, the same or similar connection die interconnect structure 617 may be formed on connection die 616 b.

In general, block 515 may include receiving, fabricating, and/or preparing to connect dies. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of such receiving, manufacturing, and/or preparing, or any particular characteristics of such connecting dies.

Example method 500 may include, at block 520, receiving, fabricating, and/or preparing a carrier having a signal Redistribution (RD) structure (or distribution structure) thereon. Block 520 may include performing such receiving, manufacturing, and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 520 may, for example, share any or all characteristics with any or all of the carrier receiving, manufacturing, and/or preparing discussed herein (e.g., block 120 with respect to example method 100 of fig. 1, block 320 with respect to example method 300 of fig. 3, etc.). Various example aspects of block 520 are provided in example 600A of fig. 6A.

As discussed herein, any or all of the carriers discussed herein may, for example, comprise only bulk material (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal Redistribution (RD) structures on (or in place of) the bulk material. Block 520 provides an example of the receipt, manufacture and/or preparation of such a carrier.

The block 520 may include forming the RD structure 646a on the bulk carrier 621a in any of a variety of ways, non-limiting examples of which are presented herein. In example embodiments, the one or more dielectric layers and the one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to a second die interconnect structure 614 (later formed) that will ultimately be connected to the functional dies 611a and 612a (later connected).

Fig. 6A shows an example where RD structure 646A includes three dielectric layers 647 and three conductive layers 648. Such number of layers is merely an example, and the scope of the present disclosure is not so limited. In another example implementation, RD structure 646a may include only a single dielectric layer 647 and a single conductive layer 648, two of each layer, etc. Example Redistribution (RD) structures 646a are formed on the bulk carrier 621a material.

The dielectric layer 647 may be formed of any of various materials (e.g., Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy, or other insulating material). Dielectric layer 647 may be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). Dielectric layer 647 may, for example, be patterned to expose various surfaces (e.g., to expose lower traces or pads of conductive layer 648, etc.).

The conductive layer 648 may be formed of any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). The conductive layer 648 may be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The redistribution structure 646a may, for example, comprise a conductor exposed at an outer surface thereof (e.g., exposed at the top surface of example 600A). Such exposed conductors may be used, for example, for attachment (or formation) of a die interconnect structure (e.g., at block 525, etc.). In such embodiments, the exposed conductors may include pads and may, for example, include Under Bump Metallization (UBM) formed thereon to enhance attachment (or formation) of the die interconnect structure. Such an under bump metallization may, for example, comprise one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive material.

Example redistribution structures and/or their formation are provided in U.S. patent application No. 14/823,689 entitled SEMICONDUCTOR package and METHOD of MANUFACTURING the same (SEMICONDUCTOR device PACKAGE AND MANUFACTURING METHOD) filed on 11/8/2015 and U.S. patent No. 8,362,612 entitled SEMICONDUCTOR device and METHOD of MANUFACTURING the same (SEMICONDUCTOR device DEVICE AND MANUFACTURING METHOD), the contents of each of which are hereby incorporated by reference in their entirety.

The redistribution structure 646a may, for example, perform fan-out redistribution of at least some electrical connections, such as moving electrical connections to at least a portion of the die interconnect structure 614 (to be formed) laterally to a location outside of the footprint of the functional dies 611a and 612a to be attached via such die interconnect structure 614. As another example, the rearrangement structure 646a may perform a fan-in rearrangement of at least some electrical connections, such as moving electrical connections to at least a portion of the die interconnect structure 614 (to be formed) laterally to a location within the footprint of the connection die 616b (to be connected) and/or within the footprints of the functional dies 611a and 612a (to be connected). Redistribution structure 646a may also, for example, provide connectivity for various signals between functional dies 611a and 612a (e.g., in addition to the connections provided by connection die 616 b).

In various example implementations, the block 520 may include forming only a first portion 646a of the entire RD structure 646, where a second portion 646b of the entire RD structure 646 may be formed at a later time (e.g., at block 570).

In general, block 520 may include receiving, fabricating, and/or preparing a carrier having a signal Redistribution (RD) structure thereon. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of making such carriers and/or signal redistribution structures or by any particular characteristics of such carriers and/or signal redistribution structures.

Example method 500 may include, at block 525, forming a high die interconnect structure on the RD structure (e.g., as provided at block 520). Block 525 may include forming a high die interconnect structure on the RD structure in any of various ways, non-limiting examples of which are provided herein.

Block 525 may share any or all characteristics (e.g., second die interconnect structure formation characteristics, etc.) with, for example, any or all of the functional die receiving, manufacturing, and/or preparation discussed herein (e.g., with respect to formation of block 110 and second die interconnect structure 214 and/or formation of first die interconnect structure 213 of example method 100 of fig. 1, formation of block 347 and second die interconnect structure 414 of example method 300 of fig. 3, etc.).

Various example aspects of block 525 are provided in example 600B of fig. 6B. The high interconnect structure 614 (and/or formation thereof) may share any or all of the characteristics with the second die interconnect structure 214 (and/or formation thereof) of fig. 2A and/or with the second die interconnect structure 414 (and/or formation thereof) of fig. 4H-2.

In general, block 525 may include forming a high die interconnect structure on the RD structure (e.g., as provided at block 520). Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of forming such high-die interconnect structures and/or characteristics of any particular type of high-die interconnect structure.

Example method 500 may include mounting a connection die to the RD structure at block 530 (e.g., as provided at block 520). Block 530 may include performing such mounting (or attaching or coupling) in any of a variety of ways, non-limiting examples of which are provided herein. The block 530 may share any or all characteristics, such as with any of the die attach methods discussed herein (e.g., the block 325 of the example method 300 shown with respect to fig. 3 and discussed herein, the block 125 of the example method 100 shown with respect to fig. 1 and discussed herein, etc.). Various example aspects of block 530 are presented in example 600C shown in fig. 6C.

Block 530 may, for example, include attaching the backside of the connecting die 616b to the RD structure 646a with a die-attach adhesive (e.g., tape, liquid, paste, etc.). Although connection die 616b is shown in fig. 6C as being coupled to a dielectric layer of RD structure 646a, in other example implementations, the back side of connection die 616b may be coupled to a conductive layer (e.g., to enhance heat dissipation, provide additional structural support, etc.).

Additionally, as discussed herein, any of the connection dies discussed herein may be double-sided. In such example implementations, the backside interconnect structures may be electrically connected to corresponding interconnect structures (e.g., pads, bumps, etc.) of RD structure 646 a.

In general, block 530 may include mounting a connection die to the RD structure (e.g., as provided at block 520). Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of mounting the connection die.

The example method 500 may include encapsulating at block 535. Block 535 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. Block 535 may share any or all of the characteristics, for example, with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of the example method 100 of fig. 1, with block 330 of the example method 300 of fig. 3, etc.). Various example aspects of block 535 are presented at FIG. 6D.

Block 535 may, for example, comprise performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to singulation to cut individual modules. Referring to example implementation 600D shown in fig. 6D, encapsulant 651' may cover the top side of RD structure 646a, tall pillars 614, connection die interconnect structure 617, the top side (or active or front side) of connection die 616b, and at least part (or all) of the lateral side surfaces of connection die 616 b.

Although encapsulation material 651 '(as shown in fig. 6D) is shown covering the top of high interconnect structure 614 and the top of connection die interconnect structure 617, any or all of such ends may be exposed from encapsulation material 651' (as shown in fig. 6E). Block 535 may, for example, comprise initially forming an encapsulation material 651' with tips of various interconnects exposed or protruding (e.g., using film assisted molding techniques, die seal molding techniques, etc.). Alternatively, block 535 may include forming an encapsulant material 651', followed by a thinning (or planarization or grinding) process (e.g., performed at block 540) to thin encapsulant material 651' enough to expose a top side of any or all of high interconnect structures 614 and connection die interconnect structures 617, etc.

Generally, the block 535 may comprise an envelope. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such encapsulation or characteristics of any particular type of encapsulating material or configuration thereof.

The example method 500 may include grinding the encapsulation material and/or various interconnect structures at block 540. Block 540 may include performing such grinding (or any thinning or planarization) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 540 are presented in example 600E shown in fig. 6E. The block 540 may share any or all of the characteristics, for example, with other abrasive (or thinning or planarizing) blocks (or steps) discussed herein.

As discussed herein, in various example implementations, the encapsulation material 651' may be initially formed to a thickness greater than the final desired thickness, and/or the high interconnect structure 614 and the connecting die interconnect structure 617 may be initially formed to a thickness greater than the final desired thickness. In such example implementations, block 540 may be performed to grind (or otherwise thin or planarize) the encapsulation material 651', the high interconnect structures 614, and/or the connection die interconnect structures 617. In example 600E shown in fig. 6E, encapsulant material 651, high interconnect structure 614, and/or connecting die interconnect structure 617 have been ground to produce encapsulant material 651 and interconnect structures 613 and 617 (as shown in fig. 6E). The top surface of the ground encapsulant 651, the top surface of the tall interconnect structures 614, and/or the top surface of the connection die interconnect structures 617 may be coplanar, for example.

It should be noted that in various example implementations, the top surface of the tall interconnect structures 614 and/or the top surface of the connection die interconnect structures 617 may protrude from the top surface of the encapsulant material 651, for example, using a chemical or mechanical process that thins the encapsulant material 651 more than the interconnect structures 614 and/or 617, using a film assist and/or seal molding process at block 535, or the like.

In general, block 540 may include grinding (or thinning or planarizing) the encapsulation material and/or various interconnect structures. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 500 may include attaching (or coupling or mounting) a functional die to the high interconnect structure and connecting the die interconnect structure at block 545. Block 545 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. The block 545 may share any or all of the characteristics, for example, with any of the die attach processes discussed herein. Various example aspects of block 545 are presented in the example 600F shown in fig. 6F.

For example, the die interconnect structures (e.g., pads, bumps, etc.) of the first functional die 611a may be mechanically and electrically connected to the respective high interconnect structures 614 and to the respective connecting die interconnect structures 617. Similarly, the die interconnect structures (e.g., pads, bumps, etc.) of the second functional die 612a can be mechanically and electrically connected to the respective high interconnect structures 614 and to the respective connecting die interconnect structures 617.

Such interconnect structures may be connected in any of a variety of ways. The connection may be performed by welding, for example. In an example embodiment, the high-die interconnect structure 614, the connecting-die interconnect structure 617, and/or the respective interconnect structures of the first functional die 611a and the second functional die 612a may include solder caps (or other solder structures) that may be reflowed to perform the connections. Such solder caps may be reflowed, for example, by mass reflow, Thermal Compression Bonding (TCB), and the like. In another example implementation, the connection may be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding instead of utilizing solder. Examples of such connections are provided in U.S. patent application No. 14/963,037, filed on 8.12.2015 and entitled "Transient Interface Gradient Bonding for Metal Bonds" and U.S. patent application No. 14/989,455, filed on 6.2016.1.4 and entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing the same", each of which is hereby incorporated by reference in its entirety. Any of a variety of techniques may be utilized to attach the functional die interconnect structure to the high interconnect structure 614 and the connecting die interconnect structure 617 (e.g., mass reflow, Thermal Compression Bonding (TCB), direct metal-to-metal intermetallic bonding, conductive adhesive, etc.).

As example implementation 600F shows, the first connecting die interconnect structures 617 of the connecting die 616b are connected to respective interconnect structures of the first functional die 611a, and the second connecting die interconnect structures 617 of the connecting die 616b are connected to respective interconnect structures of the second functional die 612 a. When connected, the connecting die 616B provides electrical connections between the various die interconnect structures of the first functional die 611a and the second functional die 612a via the RD structure 298 of the connecting die 616B (e.g., as shown by example 200B-4 of FIG. 2B-1, etc.).

In the example 600F shown in fig. 6F, the height of the high interconnect structure 614 may be, for example, equal to (or greater than) the combined height of the support layer 290b connecting the die interconnect structure 217 and the connection die 616b, and the adhesive or other means used to attach the connection die 616b to the RD structure 646 a.

In general, block 545 may include attaching (or coupling or mounting) a functional die to a high interconnect structure and connecting the die interconnect structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such attachment or characteristics of any particular type of attachment structure.

The example method 500 may include underfilling the functional die at block 550. Block 550 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are provided herein. Block 550 may, for example, share any or all characteristics with any of the underfills discussed herein (e.g., with block 155 and/or block 175 of the example method 100 of fig. 1, with block 355 and/or block 375 of the example method 300 of fig. 3, etc.). Various example aspects of block 550 are presented in example 600G shown in fig. 6G.

It should be noted that an underfill may be applied between the functional dies 611a and 612a and the encapsulating material 651. In the context of utilizing a pre-applied underfill (PUF), such PUF may be applied to the functional dies 611a and 612a, and/or to the top exposed ends of the encapsulant material 651 and/or

interconnect structures

614 and 617 prior to coupling the functional dies.

Following the attachment performed at block 545, block 550 may include forming an underfill (e.g., a capillary underfill, an injected underfill, etc.). As shown in the example implementation 600G of fig. 6G, an underfill material 661 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the underside of the functional dies 611a and 612a (e.g., in the orientation shown in fig. 6G), and/or at least a portion, if not all, of the lateral sides of the functional dies 611a and 612 a. The underfill material 661 can also, for example, cover most (or all) of the top side of the encapsulation material 651. The underfill material 661 can also, for example, surround the respective interconnect structures of the functional dies 611a and 612a to which the high interconnect structure 614 and the connection die interconnect structure 617 are attached. In example implementations in which the ends of the tall interconnect structures 614 and/or the connection die interconnect structures 617 protrude from the encapsulation material 651, the underfill material 661 can also surround such protruding portions.

It should be noted that in various example implementations of example method 500, the underfill performed at block 550 may be skipped. For example, underfilling the functional die may be performed at another block (e.g., at block 555, etc.). Also for example, such underfill may be omitted entirely.

In general, block 550 may include underfilling the functional die. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such underfill or characteristics of any particular type of underfill material.

The example method 500 may include wrapping at block 555. Block 555 may include performing such wrapping in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 555 may share any or all of the characteristics, e.g., with other encapsulation blocks (or steps) discussed herein (e.g., with block 535, with block 130 of the example method 100 of fig. 1, with block 330 of the example method 300 of fig. 3, etc.).

Various example aspects of block 555 are presented in example 600H shown in fig. 6H. For example, encapsulation material 652 '(and/or formation thereof) may share any or all of the characteristics with encapsulation material 226' (and/or formation thereof) of fig. 2E, with encapsulation material 426 (and/or formation thereof) of fig. 4K, with encapsulation material 651 (and/or formation thereof) of fig. 6D, and so forth.

Encapsulation material 652' covers the top side of encapsulation material 651, covers the lateral side surfaces of underfill 661, covers at least some (if not all) of the lateral side surfaces of functional dies 611a and 612a, covers the top sides of functional dies 611a and 612a, and so on.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226 'of fig. 2E, etc.), encapsulation material 652' need not be initially formed to cover the top sides of functional dies 611a and 612 a. For example, block 555 may include forming the encapsulation material 652' using film assisted molding, seal molding, or the like.

Generally, block 555 may include an envelope. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such encapsulation, characteristics of any particular type of encapsulating material, or the like.

The example method 500 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 560. Block 560 may include performing such grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 560 may share any or all of the characteristics, e.g., with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of the example method 100 of fig. 1, with block 335 of the example method 300 of fig. 3, with block 540, etc.).

Various example aspects of block 560 are presented in example 600I shown in fig. 6I. Example polished (or thinned or planarized, etc.) encapsulant 652 (and/or formed thereof) can share any or all of the characteristics with encapsulant 226 (and/or formed thereof) of fig. 2F, with encapsulant 426 (and/or formed thereof) of fig. 4F, with encapsulant 651 (and/or formed thereof) of fig. 6E, and/or the like.

Block 560 may, for example, include grinding encapsulant 652 and/or functional dies 611a and 612a such that a top surface of encapsulant 652 is coplanar with a top surface of functional die 611a and/or with a top surface of functional die 612 a.

Generally, block 560 may include grinding (or otherwise thinning or planarizing) the encapsulant material. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such grinding (or thinning or planarizing).

The example method 500 may include removing the carrier at block 565. Block 565 may include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 565 may share any or all of the characteristics with any of the carrier removal processes discussed herein (e.g., with block 145 and/or block 160 of the example method 100 of fig. 1, with block 345 and/or block 360 of the example method 300 of fig. 3, etc.). Various example aspects of block 565 are shown in example 600J of fig. 6J.

For example, example 600J of fig. 6J shows the removal of the first carrier 621a (e.g., as compared to example 600I of fig. 6I). Block 565 may include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, lift-off, shearing, thermal release, or laser release, etc.). As another example, if an adhesive layer is utilized during formation of the RD structure 646a, such as at block 520, then block 565 may include removing the adhesive layer.

It should be noted that in various example implementations, as shown and discussed herein with respect to the

example methods

100 and 300 of fig. 1 and 3, a second carrier (e.g., coupled to the encapsulation material 652 and/or coupled to the functional dies 611a and 612a) may be utilized. In other example embodiments, various tool configurations may be utilized in place of the carrier.

In general, block 565 may include removing the carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of removing the carrier or characteristics of any particular type of carrier.

Example method 500 may include completing a signal Redistribution (RD) structure at block 570. Block 570 may include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 570 may, for example, share any or all of the characteristics with block 520 (e.g., with respect to the RD structure forming aspects of block 520). Various aspects of block 570 are presented in example 600K shown in FIG. 6K.

As discussed herein, for example, with respect to block 520, the carrier may have been (or fabricated or prepared) with only a portion of the desired RD structure formed. In such an example scenario, block 570 may include completing formation of the RD structure.

Referring to fig. 6K, block 570 may include forming a second portion 646b of the RD structure over the first portion 646a of the RD structure (e.g., the first portion 646a of the RD structure has been received or manufactured or prepared at block 520). Block 570 may, for example, include forming a second portion 646b of the RD structure in the same manner as forming the first portion 646a of the RD structure.

It should be noted that in various embodiments, first portion 646a of the RD structure and second portion 646b of the RD structure may be formed using different materials and/or different processes. For example, the first portion 646a of the RD structure may be formed using an inorganic dielectric layer, and the second portion 646b of the RD structure may be formed using an organic dielectric layer. For another example, the first portion 646a of the RD structure may be formed to have a finer pitch (or finer traces, etc.), while the second portion 646b of the RD structure may be formed to have a coarser pitch (or coarser traces, etc.). For another example, the first portion 646a of the RD structure may be formed using a back end of line (BEOL) semiconductor wafer fabrication (fab) process, while the second portion 646b of the RD structure may be formed using a fab post-electronics packaging process. Additionally, the first portion 646a of the RD structure and the second portion 646b of the RD structure may be formed at different geographic locations.

As with the first portion 646a of the RD structure, the second portion 646b of the RD structure may have any number of dielectric and/or conductive layers.

An interconnect structure may be formed over RD structure 646b as discussed herein. In such example implementations, block 565 may include forming an Under Bump Metallization (UBM) on the exposed pads to enhance the formation (or attachment) of such interconnect structures.

In general, block 570 may include a done signal Redistribution (RD) structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of forming the signal redistribution structures or characteristics of any particular type of signal redistribution structure.

Example method 500 may include, at block 575, forming an interconnect structure on the redistribution structure. Block 575 may include forming the interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 575 may be formed to share any or all of the characteristics with any of the interconnect structures discussed herein.

Various example aspects of block 575 are presented in example 600L shown in fig. 6L. Example interconnect structures 652 (e.g., package interconnect structures, etc.) may include characteristics of any of a variety of interconnect structures. For example, the package interconnect structure 652 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive pillars, leads, and the like.

Block 575 can include forming the interconnect structure 652 in any of a variety of ways. For example, interconnect structure 652 may be pasted and/or printed over RD structure 646b (e.g., pasted and/or printed to its respective pad 651 and/or UBM), and then reflowed. As another example, interconnect structures 652 (e.g., conductive balls, conductive bumps, posts, wires, etc.) can be pre-formed prior to attachment and then attached to RD structure 646b (e.g., to its respective pad 651), e.g., via reflow, plating, gluing with epoxy, wire bonding, etc.

It should be noted that, as discussed above, the pads 651 of RD structure 646b may be formed with an Under Bump Metal (UBM) or any metallization to aid in forming (e.g., building, attaching, coupling, depositing, etc.) the interconnect structure 652. Such UBM formation may be performed, for example, at block 570 and/or at block 575.

In general, block 575 may include forming an interconnect structure on the redistribution structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of forming such interconnect structures or by any particular characteristics of the interconnect structures.

The example method 500 may include singulating cuts at block 580. Block 580 may include performing such singulation cuts in any of a variety of ways, non-limiting examples of which are discussed herein. Block 580 may share any or all characteristics, for example, with any singulation cut discussed herein (e.g., as discussed with respect to block 165 of the example method 100 of fig. 1, as discussed with respect to block 365 of the example method 300 of fig. 3, etc.).

Various example aspects of block 580 are presented in example 600M shown in fig. 6M. The singulated cut structure (e.g., corresponding to the encapsulating material portion 652a) may, for example, share any or all of the characteristics with the singulated cut structure of fig. 2L (e.g., corresponding to the two encapsulating

material portions

226a and 226b), with the singulated cut structure of fig. 4L (e.g., corresponding to the two encapsulating

material portions

426a and 426b), and so on.

In general, block 580 may include singulation cuts. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of singulation.

Example method 500 may include performing continued processing at block 590. Such continued processing may include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, block 590 may share any or all of the characteristics with block 190 of the example method 100 of fig. 1, with block 390 of the example method 300 of fig. 3, and so on.

For example, block 590 may comprise returning the execution flow of example method 500 to any of its blocks. Also for example, block 590 may include directing the flow of execution of example method 500 to any other method block (or step) discussed herein (e.g., with respect to example method 100 of fig. 1, example method 300 of fig. 3, example method 700 of fig. 7, etc.).

For example, as illustrated by the example 200O of fig. 2O, the example 200P of fig. 2P, and the example 200Q of fig. 2Q, the block 590 may include forming an encapsulation material and/or an underfill (or skipping forming an encapsulation material and/or an underfill).

As discussed herein, the functional die and the connecting die may be mounted to the substrate, for example, in a multi-chip module configuration. Non-limiting examples of such configurations are shown in fig. 9 and 10.

Fig. 7 shows a flow diagram of an example method 700 of manufacturing an electronic device, in accordance with various aspects of the present disclosure. The example method 700 may, for example, share any or all characteristics with any other example methods discussed herein (e.g., the example method 100 of fig. 1, the example method 300 of fig. 3, the example method 500 of fig. 5, etc.). Fig. 8A-8N show cross-sectional views illustrating an example electronic device (e.g., semiconductor package, etc.) and an example method of manufacturing the example electronic device, in accordance with various aspects of the present disclosure. Fig. 8A-8N may, for example, illustrate example electronic devices at various blocks (or steps) of method 700 of fig. 7. Fig. 7 and 8A-8N will now be discussed together. It should be noted that the order of the example blocks of method 700 may be varied without departing from the scope of the present disclosure. In an example embodiment, the method 700 of fig. 7 may be considered similar to the method of fig. 5, but with the addition of block 742 for forming the second redistribution structure.

The example method 700 may begin execution at block 705. Method 700 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, method 700 may begin executing automatically in response to one or more signals received from one or more upstream and/or downstream manufacturing stations, in response to a signal from a central manufacturing line controller, and so forth. As another example, method 700 may begin execution in response to an operator command starting. Additionally, for example, the method 700 may begin execution in response to receiving an execution stream from any other method block (or step) discussed herein.

Example method 700 may include receiving, fabricating, and/or preparing a plurality of functional dies at block 710. Block 710 may include receiving, fabricating, and/or preparing a plurality of functional dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 710 may share any or all of the characteristics with block 510 of the example method 500 shown in fig. 5 and discussed herein, with block 310 of the example method 300 shown in fig. 3 and discussed herein, and so on. Various aspects of block 710 are presented in the examples 400A-1 through 400A-4 shown in FIG. 4A. It should be noted that block 710 may also share any or all of the characteristics, such as with block 110 of the example method 100 shown in fig. 1 and discussed herein.

Functional dies 811a and 812a (and/or formation thereof) as shown in many of figures 8A-8N may, for example, share any or all characteristics with functional dies 611a and 612a (and/or formation thereof), functional dies 411 and 412 (and/or formation thereof), functional dies 211 and 212 (and/or formation thereof), and so on. For example, and without limitation, functional dies 811a and 812a can include characteristics of any of a variety of electronic components (e.g., passive electronic components, active electronic components, bare dies or components, packaged dies or components, etc.).

In general, block 710 may include receiving, fabricating, and/or preparing a plurality of functional dies. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such receiving and/or fabrication, nor by any particular characteristics of such functional die.

Example method 700 may include, at block 715, receiving, fabricating, and/or preparing a connection die. Block 715 may include receiving and/or fabricating a plurality of connected dies in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 715 may share any or all of the characteristics with block 115 of the example method 100 shown in fig. 1 and discussed herein. Various example aspects of block 715 are presented in examples 200B-1 and 200B-7 shown in FIGS. 2B-1 through 2B-2. It should be noted that block 715 may also share any or all of the characteristics, such as with block 315 of the example method 100 shown in fig. 3 and discussed herein, with block 515 of the example method 500 shown in fig. 5, and so forth.

Connection die 816B and connection die interconnect structure 817 (and/or formation thereof) as shown in many of figures 8A-8N may share any or all of the characteristics with connection die 216B and connection die interconnect structure 217 (and/or formation thereof) of figures 2B-1-2, for example.

It should be noted that the connection die interconnect structure 817 (and/or formation thereof) may share any or all of the characteristics with the first die interconnect structure 213 (and/or formation thereof), for example. For example, in an example embodiment, instead of forming a first die interconnect structure, such as first die interconnect structure 213 of fig. 2A, on functional die 211/212, the same or similar connection die interconnect structure 817 may be formed on connection die 816 b.

In general, block 715 may include receiving, fabricating, and/or preparing to connect dies. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of such receiving, manufacturing, and/or preparing, or any particular characteristics of such connecting dies.

Example method 700 may include, at block 720, receiving, fabricating, and/or preparing a carrier having a signal Redistribution (RD) structure (or distribution structure) thereon. Block 720 may include performing such receiving, manufacturing, and/or preparing in any of a variety of ways, non-limiting examples of which are provided herein.

Block 720 may share any or all characteristics, for example, with any or all of the carrier receiving, manufacturing, and/or preparing discussed herein (e.g., block 120 with respect to example method 100 of fig. 1, block 320 with respect to example method 300 of fig. 3, block 520 with respect to example method 500 of fig. 5, etc.). Various example aspects of block 720 are provided in example 800A of fig. 8A.

As discussed herein, any or all of the carriers discussed herein may, for example, comprise only bulk material (e.g., bulk silicon, bulk glass, bulk metal, etc.). Any or all such carriers may also include signal Redistribution (RD) structures on (or in place of) the bulk material. Block 720 provides an example of the receipt, manufacture and/or preparation of such a carrier.

Block 720 may include forming RD structures 846a on bulk carrier 821a in any of a variety of ways, non-limiting examples of which are presented herein. In example embodiments, the one or more dielectric layers and the one or more conductive layers may be formed to distribute electrical connections laterally and/or vertically to vertical interconnect structures 814 (to be formed later) that will ultimately be electrically connected to second redistribution structure 896 and/or functional dies 811a and 812a (to be connected later). Thus, RD structure 846a may be coreless. It should be noted, however, that in various alternative embodiments, RD structure 846a may be a cored structure.

Fig. 8A shows an example where RD structure 846a includes three dielectric layers 847 and three conductive layers 848. Such number of layers is merely an example, and the scope of the present disclosure is not so limited. In another example implementation, the RD structure 846a may include only a single dielectric layer 847 and a single conductive layer 848, two of each layer, or the like. Example Redistribution (RD) structures 846a are formed on bulk carrier 821a material.

The dielectric layer 847 may be formed of any of various materials (e.g., Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy, or other insulating material). The dielectric layer 847 may be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). The dielectric layer 847 may, for example, be patterned to expose various surfaces (e.g., to expose lower traces or pads of the conductive layer 848, etc.).

The conductive layer 848 may be formed of any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). Conductive layer 848 may be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

Redistribution structure 846a may, for example, comprise a conductor exposed at an outer surface thereof (e.g., exposed at a top surface of example 800A). Such exposed conductors may be used, for example, for attachment (or formation) of a die interconnect structure (e.g., at block 725, etc.). In such embodiments, the exposed conductors may include pads and may, for example, include Under Bump Metallization (UBM) formed thereon to enhance attachment (or formation) of the die interconnect structure. Such an under bump metallization may, for example, comprise one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive material.

Redistribution structure 846a may, for example, perform fan-out redistribution of at least some electrical connections, such as moving electrical connections to at least a portion of vertical interconnect structure 814 (to be formed) laterally to a location outside of a footprint of functional die 811 and 812 to be attached via such vertical interconnect structure 814. As another example, redistribution structure 846a may perform a fan-in redistribution of at least some electrical connections, such as moving electrical connections to at least a portion of vertical interconnect structure 814 (to be formed) laterally to a location inside the footprint of connection die 816b (to be connected) and/or inside the footprints of function dies 811 and 812 (to be connected). Redistribution structures 846a may also, for example, provide connectivity for various signals between functional dies 811 and 812 (e.g., in addition to the connections provided by connection die 816 b).

In various example implementations, block 720 may include a first portion 846a that forms only the entire RD structure 846, where a second portion 846b of the entire RD structure 846 may be formed later (e.g., at block 770).

In general, block 720 may include receiving, fabricating, and/or preparing a carrier having a signal Redistribution (RD) structure thereon. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of making such carriers and/or signal redistribution structures or by any particular characteristics of such carriers and/or signal redistribution structures.

Example method 700 may include, at block 725, forming a vertical interconnect structure over the RD structure (e.g., as provided at block 720). Block 725 may include forming a vertical interconnect structure over the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. It should be noted that vertical interconnect structures may also be referred to herein as high bumps, high pillars, high bars, die interconnect structures, functional die interconnect structures, and the like.

The block 725 may share any or all characteristics (e.g., second die interconnect structure formation characteristics, etc.) with, for example, any or all of the functional die receiving, manufacturing, and/or preparation discussed herein (e.g., with respect to the formation of the block 110 and second die interconnect structure 214 and/or the formation of the first die interconnect structure 213 of the example method 100 of fig. 1, with respect to the formation of the block 347 and second die interconnect structure 414 of the example method 300 of fig. 3, with respect to the block 525 of the example method 500 of fig. 5, etc.).

Various example aspects of block 725 are provided in example 800B of fig. 8B. The vertical interconnect structure 814 (and/or formation thereof) may share any or all of the characteristics with the second die interconnect structure 214 (and/or formation thereof) of fig. 2A and/or with the second die interconnect structure 414 (and/or formation thereof) of fig. 4H-2. Additionally, vertical interconnect structure 814 (and/or formation thereof) may share any or all of the characteristics with interconnect structure 614 (and/or formation thereof) of fig. 6B.

In general, block 725 may include forming a vertical interconnect structure over the RD structure (e.g., as provided at block 720). Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of forming such vertical interconnect structures and/or characteristics of any particular type of vertical interconnect structure.

Example method 700 may include mounting a connection die to the RD structure at block 730 (e.g., as provided at block 720). Block 730 may include performing such mounting (or attaching or coupling) in any of a variety of ways, non-limiting examples of which are provided herein. The block 730 may share any or all characteristics, for example, with any die attach discussed herein (e.g., the block 530 of the example method 500 shown with respect to fig. 5 and discussed herein, the block 325 of the example method 300 shown with respect to fig. 3 and discussed herein, the block 125 of the example method 100 shown with respect to fig. 1 and discussed herein, etc.). Various example aspects of block 730 are presented in example 800C shown in fig. 8C.

Block 730 may, for example, include attaching the backside of the connection die 816b to the RD structure 846a with a die-attach adhesive (e.g., tape, liquid, paste, etc.). Although connector die 816b is shown in fig. 8C coupled to a dielectric layer of RD structure 846a, in other example implementations, the backside of connector die 816b may be coupled to a conductive layer (e.g., to enhance heat dissipation, provide additional structural support, etc.).

Additionally, as discussed herein, any of the connection dies discussed herein may be double-sided. In such example implementations, the backside interconnect structures may be electrically connected to corresponding interconnect structures (e.g., pads, bumps, etc.) of RD structure 846 a.

In general, block 730 may include mounting a connection die to the RD structure (e.g., as provided at block 720). Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of mounting the connection die.

The example method 700 may include encapsulating at block 735. Block 735 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 735 may share any or all of the characteristics, e.g., with other encapsulation blocks (or steps) discussed herein (e.g., with block 130 of the example method 100 of fig. 1, with block 330 of the example method 300 of fig. 3, with block 530 of the example method 500 of fig. 5, etc.). Various example aspects of block 735 are presented at FIG. 8D.

Block 735 may include, for example, performing a wafer (or panel) level molding process. As discussed herein, any or all of the process steps discussed herein may be performed at the panel or wafer level prior to singulation to cut individual modules. Referring to example implementation 800D illustrated in fig. 8D, encapsulation material 851' may cover a top side of RD structures 846a, vertical interconnect structures 814, connector die interconnect structures 817, a top side (or active side or front side) of connector die 816b, and at least a portion (or all) of a lateral side surface of connector die 816 b.

Although encapsulation material 851 '(as shown in fig. 8D) is shown covering the top of vertical interconnect structures 814 and the top of connection die interconnect structures 817, any or all of such ends may be exposed from encapsulation material 851' (as shown in fig. 8E). Block 735 may, for example, include initially forming encapsulation material 851' with tips of the various interconnects exposed or protruding (e.g., using film assisted molding techniques, die seal molding techniques, etc.). Alternatively, block 735 may include forming encapsulation material 851 'followed by a thinning (or planarization or grinding) process (e.g., performed at block 740) to thin encapsulation material 851' sufficiently to expose a top side of any or all of vertical interconnect structures 814 and connection die interconnect structures 817, etc.

Generally, block 735 may include an envelope. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such encapsulation or characteristics of any particular type of encapsulating material or configuration thereof.

The example method 700 may include grinding the encapsulation material and/or various interconnect structures at block 740. Block 740 may include performing such grinding (or any thinning or planarization) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 740 are presented in example 800E shown in fig. 8E. The block 740 may share any or all of the characteristics, for example, with other abrasive (or thinning or planarizing) blocks (or steps) discussed herein.

As discussed herein, in various example embodiments, encapsulation material 851' may be initially formed to a thickness greater than the final desired thickness, and/or vertical interconnect structures 814 and connection die interconnect structures 817 may be initially formed to a thickness greater than the final desired thickness. In such example implementations, block 740 may be performed to grind (or otherwise thin or planarize) encapsulation material 851', vertical interconnect structures 814, and/or connection die interconnect structures 817. In the example 800E shown in fig. 8E, encapsulant 851, vertical interconnect structures 814, and/or connection die interconnect structures 817 have been milled to produce encapsulant 851 and vertical interconnect structures 814 and connection die interconnect structures 817 (as shown in fig. 8E). The top surface of the ground encapsulation material 851, the top surface of the vertical interconnect structures 814, and/or the top surface of the connection die interconnect structures 817 may, for example, be coplanar.

It should be noted that in various example implementations, the top surface of the vertical interconnect structures 814 and/or the top surface of the connection die interconnect structures 817 may protrude from the top surface of the encapsulation material 851, for example, utilizing a chemical or mechanical process that thins the encapsulation material 851 more than the vertical interconnect structures 814 and/or the connection die interconnect structures 817, utilizing a film assist and/or seal molding process at block 735, and/or the like.

In general, block 740 may include grinding (or thinning or planarizing) the encapsulation material and/or various interconnect structures. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such grinding (or thinning or planarizing).

Example method 700 may include forming a second signal Redistribution (RD) structure (or distribution structure) at block 742. Block 742 may include performing such formation in any of a variety of ways, non-limiting examples of which are provided herein.

Block 742 may, for example, share any or all of the characteristics with any or all of the signal distribution structure formations discussed herein (e.g., block 120 with respect to example method 100 of fig. 1, block 320 with respect to example method 300 of fig. 3, block 520 with respect to example method 500 of fig. 5, block 720, etc.). Various example aspects of block 742 are provided in example 800F of fig. 8F.

As discussed herein, example structure 800E resulting from block 740 may include a top surface comprising a top surface of encapsulation material 851, exposed top end surfaces of vertical interconnect structures 814 and/or connection die interconnect structures 817, exposed top lateral surfaces of vertical interconnect structures 814 and/or connection die interconnect structures 817, and the like. Block 742 may, for example, comprise forming a second signal redistribution structure on any or all such surfaces.

Block 742 may include forming a second RD structure in any of a variety of ways, such as on top of structure 800E, non-limiting examples of which are presented herein. In example embodiments, the one or more dielectric layers and the one or more conductive layers may be formed to laterally and/or vertically distribute electrical connections between vertical interconnect structures 814 and/or connected die interconnect structures 817 to electrical components mounted therein (e.g., to semiconductor die such as die 811 and 812, passive electrical components, shielding components, etc.). Fig. 8F shows an example where second RD structure 896 includes three dielectric layers 897 and three conductive layers 898. Such number of layers is merely an example, and the scope of the present disclosure is not so limited. In another example embodiment, second RD structure 896 may include only a single dielectric layer 897 and a single conductive layer 898, two of each layer, etc. Thus, second RD structure 896 may be coreless. It should be noted, however, that in various alternative embodiments, second RD structure 896 may be a cored structure. In another example embodiment, the second redistribution (or distribution) structure 896 may include only a single vertical metal structure (e.g., one or more layers), such as an under bump metallization structure.

The dielectric layer 897 may be formed of any of a variety of materials (e.g., Si3N4, SiO2, SiON, PI, BCB, PBO, WPR, epoxy, or other insulating material). Dielectric layer 897 may be formed using any of a variety of processes (e.g., PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, etc.). The dielectric layer 897 may, for example, be patterned to expose various surfaces (e.g., to expose lower traces or pads of the conductive layer 898, etc.).

Conductive layer 898 may be formed from any of a variety of materials (e.g., copper, silver, gold, aluminum, nickel, combinations thereof, alloys thereof, etc.). Conductive layer 898 may be formed using any of a variety of processes (e.g., electrolytic plating, electroless plating, CVD, PVD, etc.).

The second RD structure 896 may, for example, include a conductor exposed at its outer surface (e.g., exposed at the top surface of instance 800F). Such exposed conductors may be used, for example, for attachment (or formation) of electrical components and/or attachment structures thereof (e.g., at block 745, etc.). Such exposed conductors may, for example, include pad structures, under bump metallization structures, and the like. In such embodiments, the exposed conductor may include a pad and may, for example, include an Under Bump Metal (UBM) formed thereon to enhance attachment (or formation) of the component and/or its interconnect structure. Such an under bump metallization may, for example, comprise one or more layers of Ti, Cr, Al, TiW, TiN, or other conductive material.

Second RD structure 896 may, for example, perform a fan-out redistribution of at least some electrical connections or signals, moving electrical connections or signals laterally from at least a portion of connection die interconnect structure 817 and/or vertical interconnect structure 814 (attached to the underside of second RD structure 896) to a location outside the footprint of connection die interconnect structure 817 (or connection die 816b) and/or vertical interconnect structure 814. As another example, second RD structure 896 may perform a fan-in redistribution of at least some electrical connections or signals, moving electrical connections or signals laterally from at least a portion of connection die interconnect structure 817 and/or vertical interconnect structure 814 to a position inside the footprint of connection die interconnect structure 817 (or connection die 816b) and/or vertical interconnect structure 814. Second RD structure 896 may also, for example, provide connectivity for various signals between functional dice 811 and 812 (e.g., in addition to the connections provided by connection die 816b, in addition to the connections provided by RD structure 846a, etc.).

Although example block 742 has been described as forming the second RD structure layer-by-layer, it should be noted that the second RD structure may be received in a pre-formed format and then attached (e.g., welded, glued with epoxy, etc.) at block 742.

In general, block 742 may include forming a second Redistribution (RD) structure. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of making such carriers and/or signal redistribution structures or by any particular characteristics of such carriers and/or signal redistribution structures.

The example method 700 may include, at block 745, attaching (or coupling or mounting) the functional die to a second Redistribution (RD) structure (e.g., as formed at block 742). Block 745 may include performing such attachment in any of a variety of ways, non-limiting examples of which are provided herein. Block 745 may share any or all of the characteristics, for example, with any of the die attach processes discussed herein. Various example aspects of block 745 are presented in the example 800G shown in fig. 8G.

For example, the die interconnect structures (e.g., pads, bumps, etc.) of the first functional die 811a may be mechanically and electrically connected to corresponding conductors (e.g., pads, under-bump metallization, exposed traces, etc.) of the second RD structure 896. For example, the die interconnect structures of the first functional die 811a may be electrically connected to the respective vertical interconnect structures 814 and/or electrically connected to the respective connecting die interconnect structures 817 through conductors of the second RD structure 896. Similarly, the die interconnect structures (e.g., pads, bumps, etc.) of the second functional die 812a may be mechanically and electrically connected to corresponding conductors (e.g., pads, under-bump metallization, exposed traces, etc.) of the second RD structure 896. For example, the die interconnect structures of second functional die 812a may be electrically connected to respective vertical interconnect structures 814 and/or electrically connected to respective connected die interconnect structures 817 through conductors of second RD structure 896.

Such interconnect structures of the functional die may be connected in any of a variety of ways. The connection may be performed by welding, for example. In an example embodiment, the interconnect structure of functional dies 811a and 812a may include solder caps (or other solder structures) that may be reflowed by mass reflow, Thermal Compression Bonding (TCB), or the like. Similarly, the pad or underbump metallization of the second RD structure 896 may have been formed (e.g., at block 742) with a solder cap (or other solder structure) that may be reflowed by mass reflow, Thermal Compression Bonding (TCB), or the like. In another example embodiment, the connection may be performed by direct metal-to-metal (e.g., copper-to-copper, etc.) bonding without the use of solder and/or by the use of one or more intermediate non-solder metal layers. Examples of such connections are provided in U.S. patent application No. 14/963,037, filed on 8.12.2015 and entitled "Transient Interface Gradient Bonding for Metal Bonds" and U.S. patent application No. 14/989,455, filed on 6.2016.1.4 and entitled "Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing the same", each of which is hereby incorporated by reference in its entirety. Any of a variety of techniques may be utilized to attach the functional die interconnect structure to the second RD structure 896 (e.g., mass reflow, Thermal Compression Bonding (TCB), direct metal-to-metal intermetallic bonding, conductive adhesive, etc.).

As example implementation 800G shows, first connecting die interconnect structure 817 of connecting die 816b is connected to a corresponding interconnect structure of first functional die 811a by second RD structure 896, and second connecting die interconnect structure 817 of connecting die 816b is connected to a corresponding interconnect structure of second functional die 812a by second RD structure 896. When connected, connecting die 816B (e.g., in conjunction with second RD structure 896) provides electrical connections between the various die interconnect structures of first functional die 811a and second functional die 812a via RD structure 298 of connecting die 816B (e.g., as shown by example 200B-4 of FIG. 2B-1, etc.).

In the example 800G illustrated in fig. 8F, the height of the vertical interconnect structure 814 may be, for example, equal to (or greater than) the combined height of the support layer 290b connecting the die interconnect structure 217 and the connector die 816b, and the adhesive or other means used to attach the connector die 816b to the RD structure 846 a. Thus, second RD structure 896 may, for example, include a substantially planar lower side, a substantially uniform thickness, and a substantially planar upper side.

In general, block 745 may include attaching (or coupling or mounting) the functional die to the second RD structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such attachment or characteristics of any particular type of attachment structure.

Example method 700 may include underfilling the functional die at block 750. Block 750 may include performing such underfilling in any of a variety of ways, non-limiting examples of which are provided herein. Block 750 may share any or all characteristics, for example, with any of the underfills discussed herein (e.g., with block 155 and/or block 175 of the example method 100 of fig. 1, with block 355 and/or block 375 of the example method 300 of fig. 3, with block 550 of the example method 500 of fig. 5, etc.). Various example aspects of block 750 are presented in example 800H shown in fig. 8H.

It should be noted that an underfill may be applied between functional dies 811a and 812a and second RD structure 896. In the context of utilizing a pre-applied underfill (PUF), such PUF may be applied to functional dies 811a and 812a, and/or to top-exposed conductors (e.g., pads, underbump metallization, exposed traces, etc.) of second RD structure 896 and/or second RD structure 896, before coupling functional dies 811a and 812 a.

Following the attachment performed at block 745, block 750 may include forming an underfill (e.g., a capillary underfill, an injected underfill, etc.). As shown in the example implementation 800H of fig. 8H, an underfill material 861 (e.g., any underfill material discussed herein, etc.) may completely or partially cover the bottom side of the functional dies 811a and 812a (e.g., the orientation as shown in fig. 8H), and/or at least a portion, if not all, of the lateral sides of the functional dies 811a and 812 a. The underfill material 861 may also cover a majority (or all) of the top side of the second RD structure 896, for example. The underfill material 861 may also, for example, surround respective interconnect structures (e.g., pads, bumps, etc.) of the functional dies 811a and 812a to which respective interconnect structures (e.g., pads, traces, underbump metallization, etc.) of the second RD structure 896 are attached. In example implementations in which the ends of the interconnect structures of the second RD structure 896 protrude from the top surface (e.g., top dielectric layer surface) of the second RD structure 896, the underfill material 861 may also surround such protruding portions.

It should be noted that in various example implementations of example method 700, the underfill performed at block 750 may be skipped. For example, underfilling the functional die may be performed at another block (e.g., at block 755, etc.). Also for example, such underfill may be omitted entirely.

In general, block 750 may include underfilling the functional die. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such underfill or characteristics of any particular type of underfill material.

The example method 700 may include encapsulating at block 755. Block 755 may include performing such encapsulation in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 755 may share any or all characteristics with other encapsulation blocks (or steps) discussed herein (e.g., with block 735, with block 130 of the example method 100 of fig. 1, with block 330 of the example method 300 of fig. 3, with

blocks

535 and 555 of the example method 500 of fig. 5, etc.), for example.

Various example aspects of block 755 are presented in example 800I shown in fig. 8I. For example, the encapsulation material 852' (and/or formation thereof) may share any or all of the characteristics with the encapsulation material 226' (and/or formation thereof) of fig. 2E, with the encapsulation material 426 (and/or formation thereof) of fig. 4K, with the encapsulation materials 651 and 652' (and/or formation thereof) of fig. 6D and 6H, with the encapsulation material 851 of fig. 8E, and so on.

The encapsulation material 852' covers the top side of the second RD structure 896, covers the lateral side surfaces of the underfill 861, covers the top surface of the underfill 861 (e.g., between dies 811a and 812a), covers at least some (if not all) of the lateral side surfaces of functional dies 811a and 812a, covers the top sides of functional dies 811a and 812a, and so on. In other examples, the encapsulation material 852' may replace the underfill 861, thus providing an underfill between the functional die 811a and/or 812a and the second RD structure 896.

As discussed herein with respect to other encapsulation materials (e.g., encapsulation material 226 'of fig. 2E, etc.), encapsulation material 852' need not be initially formed to cover the top sides of functional dies 811a and 812 a. For example, block 755 may include forming the encapsulation material 852' using film assisted molding, seal molding, or the like.

Generally, block 755 may include an envelope. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such encapsulation, characteristics of any particular type of encapsulating material, or the like.

The example method 700 may include grinding (or otherwise thinning or planarizing) the encapsulation material at block 760. Block 760 may include performing such grinding (or any thinning or planarization process) in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 760 may share any or all of the characteristics, e.g., with other grinding (or thinning) blocks (or steps) discussed herein (e.g., with block 135 of the example method 100 of fig. 1, with block 335 of the example method 300 of fig. 3, with

blocks

540 and 555 of the example method 500 of fig. 5, with block 735, etc.).

Various example aspects of block 760 are presented in example 800J shown in fig. 8J. Example milled (or thinned or planarized, etc.) encapsulant 852 (and/or formed thereof) may share any or all of the characteristics with encapsulant 226 (and/or formed thereof) of fig. 2F, with encapsulant 426 (and/or formed thereof) of fig. 4F, with encapsulant 651 and 652 (and/or formed thereof) of fig. 6E and 6I, with encapsulant 851, and so forth.

Block 760 may, for example, include grinding encapsulation material 852 and/or functional dies 811a and 812a such that a top surface of encapsulation material 852 is coplanar with a top surface of functional die 811a and/or with a top surface of functional die 812 a.

Generally, block 760 may include grinding (or otherwise thinning or planarizing) the encapsulation material. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular manner of performing such grinding (or thinning or planarizing).

The example method 700 may include removing the carrier at block 765. Block 765 can include removing the carrier in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 765 may share any or all of the characteristics with any of the carrier removal processes discussed herein (e.g., with block 145 and/or block 160 of the example method 100 of fig. 1, with block 345 and/or block 360 of the example method 300 of fig. 3, with block 565 of the example method 500 of fig. 5, etc.). Various example aspects of block 765 are shown in example 800K of fig. 8K.

For example, example 800K of fig. 8K shows removal of first carrier 821a (e.g., as compared to example 800J of fig. 8J). Block 765 can include performing such carrier removal in any of a variety of ways (e.g., grinding, etching, chemical mechanical planarization, peeling, shearing, thermal or laser release, etc.). As another example, block 765 may include removing the adhesive layer if the adhesive layer is utilized during formation of RD structure 846a, e.g., at block 720.

example methods

100 and 300 of fig. 1 and 3, a second carrier (e.g., coupled to the encapsulation material 852 and/or coupled to the functional dies 811a and 812a) may be utilized. In other example embodiments, various tool configurations may be utilized in place of the carrier.

Generally, block 765 may include removing the carrier. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of removing the carrier or characteristics of any particular type of carrier.

Example method 700 may include completing a signal Redistribution (RD) structure at block 770 (e.g., if RD structure 846a is not fully formed at block 820). Block 770 may include completing the RD structure in any of a variety of ways, non-limiting examples of which are provided herein. Block 770 may, for example, share any or all of the characteristics with block 720 (e.g., regarding RD structure formation aspects of block 720). Various aspects of block 770 are presented in example 800L shown in fig. 8L.

As discussed herein, for example, with respect to block 720, the carrier may have been (or fabricated or prepared) with only a portion of the desired RD structure formed. In such an example scenario, block 770 may include completing the formation of the RD structure.

Referring to fig. 8L, block 770 may include forming a second portion 846b of the RD structure over the first portion 846a of the RD structure (e.g., the first portion 846a of the RD structure has been received or fabricated or prepared at block 720). Block 770 may, for example, include forming a second portion 846b of the RD structure in the same manner as forming the first portion 846a of the RD structure.

It should be noted that in various embodiments, first portion 846a of the RD structure and second portion 846b of the RD structure may be formed using different materials and/or different processes. For example, the first portion 846a of the RD structure may be formed using an inorganic dielectric layer, while the second portion 846b of the RD structure may be formed using an organic dielectric layer. For another example, the first portion 846a of the RD structure may be formed with a finer pitch (or finer traces, etc.), while the second portion 846b of the RD structure may be formed with a coarser pitch (or coarser traces, etc.). As another example, the first portion 846a of the RD structure may be formed using a back-end-of-line (BEOL) semiconductor wafer fabrication (fab) process, while the second portion 846b of the RD structure may be formed using a fab-back-electronics packaging process. Additionally, the first portion 846a of the RD structure and the second portion 846b of the RD structure may be formed at different geographic locations.

As with the first portion 846a of the RD structure, the second portion 846b of the RD structure may have any number of dielectric and/or conductive layers.

As discussed herein, an interconnect structure may be formed over RD structure 846 b. In such example embodiments, block 765 may include forming an Under Bump Metallization (UBM) on the exposed liner to enhance the formation (or attachment) of such interconnect structures.

In general, block 770 may include a done signal Redistribution (RD) structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of forming the signal redistribution structures or characteristics of any particular type of signal distribution structure.

Example method 700 may include, at block 775, forming an interconnect structure over the redistribution structure. Block 775 can include forming the interconnect structure in any of a variety of ways, non-limiting examples of which are provided herein. For example, block 775 may be formed to share any or all of the characteristics with any of the interconnect structures discussed herein.

Various example aspects of block 775 are presented in example 800M shown in fig. 8M. Example interconnect structures 852 (e.g., package interconnect structures, etc.) may include characteristics of any of a variety of interconnect structures. For example, the package interconnect structure 852 may include conductive balls (e.g., solder balls, etc.), conductive bumps, conductive pillars, leads, and the like.

Block 775 may comprise forming interconnect structure 852 in any of a variety of ways. For example, interconnect structure 852 may be pasted and/or printed on RD structure 846b (e.g., pasted and/or printed to its respective pads 851 and/or UBM), and then reflowed. As another example, interconnect structures 852 (e.g., conductive balls, conductive bumps, posts, wires, etc.) may be pre-formed prior to attachment and then attached to RD structures 846b (e.g., to their respective pads 851), e.g., by reflow, plating, gluing with epoxy, wire bonding, etc.

It should be noted that, as discussed above, the pads 851 of the RD structure 846b may be formed with an Under Bump Metal (UBM) or any metallization to aid in forming (e.g., building, attaching, coupling, depositing, etc.) the interconnect structure 852. Such UBM formation may be performed, for example, at block 770 and/or at block 775.

In general, block 775 may comprise forming an interconnect structure over the redistribution structure. Thus, the scope of the present disclosure should not be limited by characteristics of any particular manner of forming such interconnect structures or by any particular characteristics of the interconnect structures.

The example method 700 may include singulation cutting at block 780. Block 780 may include performing such singulation cuts in any of a variety of ways, non-limiting examples of which are discussed herein. Block 780 may, for example, share any or all of the characteristics with any singulation cut discussed herein (e.g., as discussed with respect to block 165 of the example method 100 of fig. 1, as discussed with respect to block 365 of the example method 300 of fig. 3, as discussed with respect to block 580 of the example method 500 of fig. 5, etc.).

Various example aspects of block 780 are presented in example 800N shown in fig. 8N. The singulated cut structure (e.g., corresponding to the encapsulating material portion 852a) may, for example, share any or all of the characteristics with the singulated cut structure of fig. 2L (e.g., corresponding to the two encapsulating

material portions

426a and 426b), with the singulated cut structure 600M of fig. 6M, and so on.

In general, block 780 may include singulation cuts. Accordingly, the scope of the present disclosure should not be limited by the characteristics of any particular manner of singulation.

Example method 700 may include performing continuation processing at block 790. Such continued processing may include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, block 790 may share any or all of the characteristics with block 190 of the example method 100 of fig. 1, with block 390 of the example method 300 of fig. 3, with block 590 of the example method 500 of fig. 5, and so on.

For example, block 790 may include returning the execution flow of example method 700 to any of its blocks. Also for example, block 790 may include directing the flow of execution of example method 700 to any other method block (or step) discussed herein (e.g., with respect to example method 100 of fig. 1, example method 300 of fig. 3, example method 500 of fig. 5, etc.).

For example, as illustrated by example 200O of fig. 2O, example 200P of fig. 2P, and example 200Q of fig. 2Q, block 790 may include forming an encapsulation material and/or an underfill (or skipping forming an encapsulation material and/or an underfill).

Fig. 9 shows a top view of an example electronic device 900, in accordance with various aspects of the present disclosure. The example electronic device 900 may, for example, share any or all of the characteristics with any or all of the electronic devices discussed herein. For example, functional dies 911 and 912 may share any or all characteristics with any or all of the functional dies discussed herein (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, etc.). Also for example, connecting die 916 may share any or all characteristics with any or all of the connecting dies discussed herein (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, etc.). Additionally, for example, substrate 930 may share any or all of the characteristics with any or all of the substrates and/or RD structures (288, 488, 646, 846, 896, etc.) discussed herein.

Fig. 10 shows a top view of an example electronic device, according to various aspects of the present disclosure. The example electronic device 1000 may, for example, share any or all of the characteristics with any or all of the electronic devices discussed herein. For example, the functional dies (functional die 1-functional die 10) may share any or all of the characteristics with any or all of the functional dies discussed herein (211, 212, 201-204, 411, 412, 401-404, 611a, 612a, 811a, 812a, 911, 912, etc.). Also for example, a connecting die (connecting die 1 to connecting die 10) may share any or all of the characteristics with any or all of the connecting dies (216a, 216b, 216c, 290a, 290b, 416a, 416b, 616b, 816b, 916, etc.) discussed herein. Additionally, for example, substrate 1030 may share any or all of the characteristics with any or all of the substrates and/or RD structures (288, 488, 646, 846, 896, 930, etc.) discussed herein.

Although the illustrations discussed herein generally include a connection die between two functional dies, the scope of the present disclosure is not so limited. For example, as shown in fig. 10, the connection die 9 is connected to three functional dies (e.g., functional die 2, functional die 9, and functional die 10), e.g., electrically connecting each such functional die to each other. Thus, a single connecting die may couple multiple functional dies (e.g., two functional dies, three functional dies, four functional dies, etc.).

Additionally, although the illustrations discussed herein generally include functional dies connected to only one connection die, the scope of the present disclosure is not so limited. For example, a single functional die may be connected to two or more connecting dies. For example, as shown in fig. 10, functional die 1 is connected to many other functional dies via many respective connection dies.

Fig. 11 shows a cross-sectional view illustrating an example electronic device 1100, connecting dies 11-16, and electronic assembly 1100A, according to various aspects of the present disclosure. In the example shown in fig. 11, the electronic device 1100 may include external substrates 11-46, device interconnects 11-14, connection dies 11-16, adhesives 11-23, internal components 11-16z, adhesives 11-23z, internal enclosures 11-51, internal substrates 11-96, electronic components 11-11, 11-12, external enclosures 11-52, underfills 11-61 (optional), and external interconnects 11-92. The example electronic device 1100 and the electronic assembly 1100A, or similarly-named portions thereof, may share any or all of the characteristics with any other device or assembly, or similarly-named portions thereof, disclosed herein.

The external substrates 11-46 may include dielectric structures 11-47 and conductive structures 11-48. The internal substrates 11-96 may include dielectric structures 11-97 and conductive structures 11-98. The electronic components 11-11 may include component interconnects 11-11a having a relatively thin width or fine pitch and component interconnects 11-11b having a relatively thick width or coarse pitch. The electronic components 11-12 may include component interconnects 11-12a having a relatively thin width or fine pitch and component interconnects 11-12b having a relatively thick width or coarse pitch.

In the example shown in fig. 11, the connected dies 11-16 can include connected die interconnects 11-17, connected die substrates 11-18, and connected die encapsulants 11-19. Connecting the die substrates 11-18 may include: a dielectric structure comprising one or more dielectric layers; and a conductive structure comprising conductive features defined by one or more conductive layers. The internal components 11-16z may include component bodies 11-15z, component interconnects 11-17z, component substrates 11-18z, or component enclosures 11-19 z.

In the example shown in FIG. 11, an electronic assembly 1100A may include an electronic device 1100, assembly substrates 11-56, peripheral structures 11-57, and components 11-58.

The external substrate 11-46, the internal enclosure 11-51, the internal substrate 11-96, and the external enclosure 11-52 may be referred to as a semiconductor package, and the package may provide protection for the electronic components 11-11 and 11-12, the connecting dies 11-16, or the internal components 11-16z from external elements or environmental exposure. The semiconductor package may provide electrical coupling between external electrical components and external interconnects.

Fig. 12A-12E show cross-sectional views illustrating an example method of fabricating example connection dies 11-16, in accordance with various aspects of the present disclosure.

Figure 12A shows a cross-sectional view of the connecting dies 11-16 at an early stage of fabrication. In the example shown in FIG. 12A, a support carrier 11-16A may be provided, and the connection die substrates 11-18 may be formed on the support carrier 11-16A. In some examples, the connecting die substrates 11-18 may be similar in structure or formation to the RD structure 298 described herein in FIG. 2B-1 or 2B-2. In some examples, the support carriers 11-16A may comprise or be referred to as silicon, glass, ceramic, metal, or plastic wafers or panels. In some examples, the support carriers 11-16A may include or be referred to as low-level printed circuit boards or low-level lead frames. In some examples, the support carriers 11-16A may be wafer-shaped (e.g., circular, etc.) or plate-shaped (e.g., square, rectangular, etc.). The support carrier 11-16A may support the connection die substrates 11-18, the connection die interconnects 11-17 and the connection die encapsulants 11-19 during the following later stages.

In some examples, the connecting die substrates 11-18 may be built on a support carrier 11-16A. Although the illustrations herein present one single connection die substrate 11-18 built on a support carrier 11-16A, the multiple connection die substrates 11-18 may be built on the support carrier 11-16A in an N x M matrix, where at least one of N or M is greater than 1.

In some examples, the connecting die substrates 11-18 may be referred to as redistribution ("RD") layers, substrates, or structures. The RD substrate may include one or more conductive redistribution layers and one or more dielectric layers, which may be formed layer-by-layer over a support carrier that may be completely removed or at least partially removed after the RD substrate is provided. RD substrates can be fabricated layer by layer as wafer level substrates in a wafer level process on a circular wafer, or as panel level substrates in a panel level process on a rectangular or square panel carrier. The RD substrate may be formed in an additive build-up process, which may include one or more dielectric layers alternately stacked with one or more conductive layers defining respective conductive redistribution patterns or traces. The conductive pattern may be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern may comprise a conductive material such as copper or other plateable metal. The location of the conductive pattern may be defined using a photo-patterning process, such as a photolithography process and a photoresist material used to form a photolithography mask. The dielectric layer of the RD substrate may be patterned using a photo-patterning process and may include a photolithographic mask through which light is exposed to the desired features of the photo-pattern, such as vias in the dielectric layer. Accordingly, the dielectric layer may be made of a photo-definable organic dielectric material such as Polyimide (PI), benzocyclobutene (BCB), or Polybenzoxazole (PBO). Such dielectric materials may be spun on or otherwise coated in liquid form, rather than being attached in the form of a pre-formed film. Such photodefinable dielectric materials may omit structural reinforcing agents, or may be free of fillers, and free of strands, woven or other particles that may interfere with light from the photo-patterning process, in order to permit proper formation of the desired photo-defined features. In some examples, such unfilled characteristics of the unfilled dielectric material may permit a reduction in the thickness of the resulting dielectric layer. Although the photo-definable dielectric material described above may be an organic material, in other examples, the dielectric material of the RD substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or SiON. The one or more inorganic dielectric layers may be formed not by using photo-defined organic dielectric materials but by growing the inorganic dielectric layers using an oxidation or nitridation process. Such inorganic dielectric layers may be free of fillers without strands, woven fabrics, or other distinct inorganic particles. In some examples, RD substrates may omit a permanent core structure or carrier, such as a dielectric material including Bismaleimide Triazine (BT) or FR4, and these types of RD substrates may be referred to as coreless substrates.

In some examples, the dielectric or conductive structures connecting the die substrates 11-18 may have a line/space/width in a range of about 0.1 microns to about 30 microns. In some examples, the total thickness of the connecting die substrates 11-18 may be in a range of about 3 microns to about 50 microns.

Figure 12B shows a cross-sectional view of the connecting dies 11-16 at a later stage of fabrication. In the example shown in fig. 12B, the connecting die interconnects 11-17 may be disposed on connecting die substrates 11-18. In some examples, the connection die interconnects 11-17 may be formed on conductive structures of the connection die substrates 11-18. The connected die interconnects 11-17 may include or be referred to as posts, rods, balls, leads, or bumps. In some examples, the connected die interconnects 11-17 may comprise a metal, such as copper, aluminum, gold, silver, nickel, palladium, or solder. The connected die interconnects 11-17 may be formed in any of a variety of ways. In some examples, the die interconnect 11-17 may be disposed on conductive structures of the die substrate 11-18 by plating. In some examples, the connecting die interconnects 11-17 may be disposed on the connecting die substrates 11-18 by printing, reflow, or wire bonding. In some examples, the connection die interconnects 11-17 may extend from conductive structures of the connection die substrates 11-18. In some examples, the connected die interconnects 11-17 may have a line/space spacing or pitch in a range of about 20 microns to about 300 microns. In some examples, the height of the connected die interconnects 11-17 may be in a range of about 10 microns to about 300 microns.

In some examples, the connecting die interconnects 11-17 may be electrically connected as a bridge between the component interconnects 11-11a of the electronic components 11-11 and the component interconnects 11-12a of the electronic components 11-12, and thus the two electronic components 11-11 and 11-12 may be electrically connected to each other in a horizontal direction by the connecting die substrates 11-18.

In some examples, the connecting die substrates 11-18 may be electrically connected to the component interconnects 11-11a of the electronic components 11-11 and the component interconnects 11-12a of the electronic components 11-12, thus electrically connecting the two electronic components 11-11 and 11-12 to each other in a horizontal direction by the connecting die substrates 11-18, and the connecting die interconnects 11-17 may be electrically connected to the external substrates 11-46, thus electrically connecting the two electronic components 11-11 and 11-12 to the external substrates 11-46 by the connecting die interconnects 11-17. In an example implementation, power from the external substrates 11-46 may be supplied to the electronic components 11-11 and 11-12 by connecting the die interconnects 11-17.

Figure 12C shows a cross-sectional view of the connecting dies 11-16 at a later stage of fabrication. In the example shown in fig. 12C, the connection die encapsulants 11-19 can be disposed on the connection die substrates 11-18 and the connection die interconnects 11-17. The connection die encapsulants 11-19 may cover a top side of the connection die substrates 11-18 or may cover lateral sides of the connection die interconnects 11-17. In some examples, the connection die encapsulants 11-19 may include an epoxy or phenolic resin, or a silica filler. In some examples, the connection die encapsulants 11-19 may include or be referred to as a molding compound, resin, encapsulant, filler reinforced polymer, or organic body. In some examples, the connection die encapsulants 11-19 can cover not only the lateral sides but also the top ends of the connection die interconnects 11-17. In some examples, the top sides of the connection die encapsulants 11-19 and the top sides of the connection die interconnects 11-17 can be coplanar. In some examples, the connecting die encapsulates 11-19 may be formed by a compression molding process, a transfer molding process, a liquid phase encapsulant molding process, a vacuum lamination process, a paste printing process, or a film assisted molding process. In some examples, a compression molding process may be performed such that the flowable resin is pre-supplied to a mold, the connected die substrates 11-18 with the connected die interconnects 11-17 are placed into the mold, and the corresponding flowable resin is then cured. A transfer molding process may be performed such that flowable resin is supplied from a gate (supply orifice) of the mold to the peripheral edges of the connected die substrates 11-18 including the connected die interconnects 11-17. In some examples, the thickness (height) of the connection die encapsulants 11-19 can be similar to the connection die interconnects 11-17. The connection die encapsulants 11-19 may provide structural integrity or protection for the connection dies 11-16 (e.g., the connection die interconnects 11-17) from external elements or environmental exposure when the connection dies 11-16 are manufactured.

Figure 12D shows a cross-sectional view of the connecting dies 11-16 at a later stage of fabrication. In the example shown in fig. 12D, a thinning process may be carried out. A grinding wheel or grinding pad may be used to reduce the top side of the connection die interconnects 11-17 and the top side of the connection die encapsulants 11-19. After or before the thinning process, the top side of the connection die interconnects 11-17 and the top side of the connection die encapsulants 11-19 may be etched. After the thinning process, the top sides of the connection die interconnects 11-17 and the top sides of the connection die encapsulates 11-19 may be coplanar, or the top sides of the connection die interconnects 11-17 may be exposed through the top sides of the connection die encapsulates 11-19.

Figure 12E shows a cross-sectional view of the connecting dies 11-16 at a later stage of fabrication. In the example shown in fig. 12E, the support carrier 11-16A may be removed from the connection die substrate 11-18. In some examples, the wafer support system may be first attached to the connection die interconnects 11-17 and the connection die encapsulants 11-19. In some examples, heat or light (e.g., a laser beam) may be supplied to the temporary adhesive when the temporary adhesive is positioned between the connection die substrates 11-18 and the support carriers 11-16A, and thus may weaken or remove the adhesiveness of the temporary adhesive, thereby removing the support carriers 11-16A from the connection die substrates 11-18. In some examples, mechanical forces may be used to forcibly separate the support carriers 11-16A from the connecting die substrates 11-18. In some examples, the support carriers 11-16A may be removed by mechanical grinding and chemical etching. When the connecting die substrates 11-18 are manufactured in a matrix type as discussed above, a singulation or sawing process may additionally be performed to separate into individual connecting dies 11-16. The lateral sides of the connection die encapsulation 11-19 and the lateral sides of the connection die substrate 11-18 may be coplanar by a singulation process.

When completed, the connection dies 11-16 may include connection die substrates 11-18 having a fine or narrow pitch and connection die interconnects 11-17 having a fine or narrow pitch. In some examples, the connected die interconnects 11-17 can be connected to the internal substrates 11-96, wherein the connected die interconnects 11-17 facing toward the internal substrates 11-96 (upward facing) and such upward facing arrangement can couple the electronic components 11-11 and 11-12 in a horizontal direction through the connected dies 11-16. In some examples, the connecting die substrates 11-18 can be connected to the internal substrates 11-96, and the connecting die interconnects 11-17 can be connected to the external substrates 11-46, with the connecting die interconnects 11-17 facing toward the external substrates 11-46 (facing downward). The connector dies 11-16 having a similar structure may be used as face-up type connector dies in some examples and face-down type connector dies in some other examples, and will be described in further detail below.

Fig. 13A-13K show cross-sectional views of an example method of manufacturing an example electronic device 1100 and an example electronic assembly 1100A, in accordance with various aspects of the present disclosure.

Figure 13A shows a cross-sectional view of an electronic assembly 1100A at an early stage of fabrication. In the example shown in fig. 13A, the external substrates 11-46 may be disposed or formed on a support carrier 11-46A. In some examples, the external substrates 11-46 may include or be referred to as Redistribution (RD) layers, substrates, or structures. The external substrates 11-46 may include dielectric structures 11-47 and conductive structures 11-48. The dielectric structures 11-47 may include or be referred to as one or more dielectric layers. Conductive structures 11-48 may include or be referred to as one or more conductive layers, traces, vias, pads, or UBMs. In some examples, the dielectric structures 11-47 may include PI, BCB, PBO, Si3N4, SiO2, or SiON, and may be provided by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. In some examples, the conductive structures 11-48 may include copper, silver, gold, aluminum, nickel, or palladium, or may be provided by electroplating, electroless plating, CVD, or PVD. In some examples, a portion of conductive structures 11-48 may be exposed through dielectric structures 11-47. The exposed portions of conductive structures 11-48 may include pads, and the pads may include UBMs. The UBM may include Ti, Cr, Al, TiW, TiN, Cu, NiV, or other conductive materials. In some examples, the features, materials, structures, or processes of fig. 13A may be similar to the features, materials, structures, or processes of example 600A shown in fig. 6A, example 800A shown in fig. 8A, or example shown in fig. 12A.

Figure 13B shows a cross-sectional view of the electronic assembly 1100A at a later stage of fabrication. In the example shown in FIG. 13B, the device interconnects 11-14 may be formed or disposed on the external substrates 11-46. Device interconnects 11-14 may be disposed on conductive structures 11-48. The device interconnects 11-14 may include or be referred to as posts, rods, balls, leads, or bumps. In some examples, the features, materials, structures, or processes of fig. 13B may be similar to the features, materials, structures, or processes of example 600B shown in fig. 6B, example 800B shown in fig. 8B, or example shown in fig. 12B.

Figure 13C shows a cross-sectional view of the electronic assembly 1100A at a later stage of fabrication. In the example shown in fig. 13C, the connecting dice 11-16 may be disposed on external substrates 11-46. In some examples, the adhesive 11-23 may be supplied between the dielectric structures 11-47 connecting the die substrates 11-18 and the external substrates 11-46. In some examples, the adhesives 11-23 may include an electrical insulator layer. In some examples, the connecting die substrates 11-18 and the external substrates 11-46 may be electrically decoupled from each other by the adhesive 11-23. In some examples, the adhesives 11-23 may include or be referred to as adhesive tapes, adhesive films, or adhesive pastes. In some examples, the adhesives 11-23 may further include thermally conductive fillers based on nitrides, oxides, or carbides of, for example, AlN, BN, Al2O3, SiC. In some examples, the connection dies 11-16 are attached in a face up configuration with the connection die interconnects 11-17 facing up or away from the external substrates 11-46. In some examples, the features, materials, structures, or processes of fig. 13C may be similar to the features, materials, structures, or processes of example 600C shown in fig. 6C or example 800C shown in fig. 8C.

In some examples, the internal components 11-16z (FIG. 11) may additionally be disposed on the external substrates 11-46. In some examples, the internal component bodies 11-15z may be attached to the dielectric structures 11-47 or the conductive structures 11-48 of the external substrates 11-46 using adhesives 11-23 z. In some examples, internal components 11-16z may include active devices such as processors, microcontrollers, memory, or transistor devices, passive devices such as resistors, capacitors, inductors, or Integrated Passive Devices (IPDs), or another connecting die similar to connecting dies 11-16.

Figure 13D shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in FIG. 13D, the inner enclosures 11-51 may be disposed on the outer substrates 11-46. The inner encapsulation 11-51 may cover the outer substrate 11-46 and may also cover the device interconnects 11-14 and the connection dies 11-16. In some examples, the thickness of the inner enclosure 11-51 may be greater than the thickness of the device interconnects 11-14 or the thickness of the connection dies 11-16. In this case, a thinning process for removing the top portion of the inner enclosures 11-51 may be additionally performed. In some examples, the top sides of the device interconnects 11-14 and the connection dies 11-16 may be exposed through the inner encapsulants 11-51 by a thinning process. In some examples, an etching process for removing the top side of the inner enclosures 11-51 may be performed after or before the thinning process. In some examples, the top side of the connection die interconnects 11-17 and the top side of the connection die encapsulants 11-19 may be exposed through the top side of the inner encapsulants 11-51. In some examples, the top sides of the device interconnects 11-14 and the top sides of the connection dies 11-16 may be coplanar with the top sides of the internal enclosures 11-51. In some examples, the top side of the connection die interconnects 11-17 and the top side of the connection die encapsulates 11-19 may be coplanar with the top side of the internal encapsulates 11-51. In some examples, the features, materials, structures, or processes of fig. 13D may be similar to the features, materials, structures, or processes of examples 600D and 600E shown in fig. 6D and 6E, examples 800D and 800E shown in fig. 8D and 8E, or examples shown in fig. 12D.

Figure 13E shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in fig. 13E, the internal substrates 11-96 may be formed or disposed on the device interconnects 11-14, the internal encapsulants 11-51, and the connection dies 11-16. In some examples, the interior substrates 11-96 may include or be referred to as Redistribution (RD) layers, RD substrates, or RD structures. The internal substrates 11-96 may include dielectric structures 11-97 and conductive structures 11-98. The dielectric structures 11-97 may include or be referred to as one or more dielectric layers. The conductive structures 11-98 may include or be referred to as one or more conductive layers, traces, vias, pads, or UBMs. In some examples, the dielectric structures 11-97 of the internal substrates 11-96 may be formed on the internal encapsulants 11-51 or the connection die encapsulants 11-19. In some examples, the conductive structures 11-98 of the internal substrates 11-96 can be formed to contact the device interconnects 11-14 or connect die interconnects 11-17. In some examples, not only the device interconnects 11-14 but also the connection dies 11-16 may be electrically connected to the internal substrates 11-96. In some examples, a portion of the conductive structures 11-98 may be exposed through the dielectric structures 11-97, the exposed portion of the conductive structures 11-98 may include a pad, and the pad may include a UBM. In some examples, the features, materials, structures, or processes of fig. 13E may be similar to those of example 800F shown in fig. 8F. In some examples, the dielectric structures 11-97 of the interior substrates 11-96 may be in contact with the component encapsulants 11-19z (see FIG. 11). In some examples, the conductive structures 11-98 of the internal substrates 11-96 can electrically contact the component interconnects 11-17z (see fig. 11).

Figure 13F shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in FIG. 13F, the electronic components 11-11 and 11-12 may be disposed on the inner substrates 11-96. In some examples, electronic components 11-11 or 11-12 may be similar to

components

811a or 812a described herein. The electronic components 11-11 can include a set of component interconnects 11-11a having a relatively thin width or fine pitch (e.g., in the range of about 20 microns to about 300 microns) and a set of component interconnects 11-11b having a relatively thick width or coarse pitch (e.g., in the range of about 30 microns to about 500 microns), and these sets of component interconnects 11-11a and 11-11b can be electrically connected to the conductive structures 11-98 of the internal substrates 11-96. The electronic components 11-12 can include a set of component interconnects 11-12a having a relatively thin width or fine pitch (e.g., in the range of about 20 microns to about 300 microns) and a set of component interconnects 11-12b having a relatively thick width or coarse pitch (e.g., in the range of about 30 microns to about 500 microns), and these sets of component interconnects 11-12a and sets of component interconnects 11-12b can be electrically connected to the conductive structures 11-98 of the internal substrates 11-96.

In some examples, the component interconnects 11-11a, 11-11b, 11-12a, and 11-12b may include or be referred to as bumps, posts, solder caps, pads, or leads. In some examples, electronic components 11-11 and 11-12 may include or be referred to as dies, chips, or packages. In some examples, electronic components 11-11 may include processors and electronic components 11-12 may include memory chips. In some examples, both electronic components 11-11 and 11-12 may include processors or memory chips. In some examples, the component interconnects 11-11a, 11-11b, 11-12a, or 11-12b may be directly connected to the conductive structures 11-98 of the internal substrates 11-96, or may be connected using a conductive adhesive, such as solder. In some examples, the underfill 11-61 may additionally be disposed between the electronic components 11-11, 11-12 and the internal substrate 11-96. The underfill 11-61 may be disposed between the bottom side of the electronic components 11-11 and 11-12 and the top side of the internal substrate 11-96, and may cover lateral sides of the electronic components 11-11 or 11-12. The underfill 11-61 may surround a lateral side of the module interconnect 11-11a, 11-11b, 11-12a, or 11-12 b. In some examples, the features, materials, structures, or processes of fig. 13F may be similar to the features, materials, structures, or processes of examples 600F and 600G shown in fig. 6F and 6G, and examples 800G and 800H shown in fig. 8G and 8H.

Figure 13G shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in FIG. 13G, the outer enclosures 11-52 may be disposed on the inner substrates 11-96 and the electronic components 11-11 and 11-12. In some examples, the outer enclosures 11-52 may cover the top sides of the inner substrates 11-96, the top sides and (or lateral) sides of the electronic components 11-11 and 11-12, and the sides of the underfills 11-61. In some examples, the top side of the outer enclosures 11-52 or the top sides of the electronic components 11-11 and 11-12 may be ground (or otherwise planarized). In some examples, the top side of the outer enclosures 11-52 may be coplanar with the top sides of the electronic components 11-11 and 11-12. In some examples, the top sides of the electronic components 11-11 and 11-12 may be exposed through the top side of the outer enclosures 11-52. In some examples, the features, materials, structures, or processes of fig. 13G may be similar to the features, materials, structures, or processes of examples 600H and 600I shown in fig. 6H and 6I or examples 800I and 800J shown in fig. 8I and 8J.

Figure 13H shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in fig. 13H, the support carrier 11-52A may be disposed on the electronic components 11-11 and 11-12 and the outer enclosure 11-52 using a temporary adhesive, and the support carrier 11-16A may be removed from the outer substrate 11-46. In some examples, the support carrier 11-16A may be removed from the external substrate 11-46 by grinding or etching. After removal of the support carrier 11-16A, the bottom sides of the dielectric structures 11-47 and the conductive structures 11-48 of the external substrate 11-46 may be exposed. In some examples, the process of removing the support carriers 11-16A may be similar to example 800K shown in fig. 8K. In some examples, the features, materials, structures, or processes of fig. 13H may be similar to those of example 800K shown in fig. 8K.

Figure 13I shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in FIG. 13I, the external interconnects 11-92 may be disposed on the external substrates 11-46. In some examples, the external interconnects 11-92 may be provided as conductive structures 11-48 coupled to the external substrates 11-46. In some examples, the external interconnects 11-92 may include or be referred to as conductive balls, conductive bumps, conductive pillars, or solder caps. In some examples, the features, materials, structures, or processes of fig. 13I may be similar to the features, materials, structures, or processes of example 600L shown in fig. 6L or example 800M shown in fig. 8M.

The electronic device 1100 may be completed after the support carriers 11-52A are removed. The electronic device 1100 may include the connecting dice 11-16 in a face-up configuration, where the connecting dice 11-16 electrically couple the electronic components 11-11 and 11-12 in a horizontal direction. In some examples, when a plurality of electronic devices 1100 are manufactured in a matrix type, a singulation cut or sawing process may additionally be performed to separate the plurality of electronic devices into individual electronic devices 1100. Due to the singulation process, lateral sides of the outer substrate 11-46, the inner enclosure 11-51, the inner substrate 11-96, and the outer enclosure 11-52 may be coplanar.

Figure 13J shows a cross-sectional view of a later stage in the manufacture of the electronic assembly 1100A. In the example shown in FIG. 13J, the electronic device 1100 may be disposed on the assembly substrates 11-56. In some examples, the external interconnects 11-92 of the electronic device 1100 may be coupled to the assembly substrates 11-56. In some examples, the underfill 11-61A may be disposed between the electronic device 1100 and the assembly substrate 11-56. In some examples, electronic components 11-58 may additionally be disposed on assembly substrates 11-56 (see FIG. 11). The assembly substrates 11-56 may include: a dielectric structure having one or more dielectric layers; and a conductive structure having one or more features, such as pads, or traces, defined by one or more conductive layers.

In some examples, the assembly substrates 11-56 may be preformed substrates. The preformed substrate may be fabricated prior to attachment to the electronic device and may include dielectric layers between respective conductive layers. The conductive layer may include copper, and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer that may be attached in a preformed film rather than in liquid form and may contain a resin with a filler such as strands, woven fabric or other inorganic particles for rigid or structural support. Because the dielectric layer is not photodefinable, features such as vias or openings can be formed by using a drill or laser. In some examples, the dielectric layer may include a prepreg or an ajinomoto film (ABF). The preformed substrate may comprise a permanent core structure or carrier, such as a dielectric material including Bismaleimide Triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate and omit the permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after formation of the dielectric and conductive layers and before attachment to the electronic device. The preformed substrate may be referred to as a Printed Circuit Board (PCB) or a laminate substrate. Such a pre-formed substrate may be formed by a semi-additive process or a modified semi-additive process.

Figure 13K shows a cross-sectional view of the electronic assembly 1100A at a later stage in fabrication. In the example shown in FIG. 13K, peripheral structures 11-57 may be disposed on the assembly substrates 11-56. In some examples, the peripheral structures 11-57 may include or be referred to as covers, shrouds, fins, stiffeners, covers, or covers. In some examples, the peripheral structures 11-57 may include a conductive material (e.g., copper, steel, or aluminum), a dielectric material (e.g., a molding compound, resin, or ceramic), or a dielectric material coated with a conductive material. In some examples, the perimeter structures 11-57 may be applied as pre-formed parts, or may be formed in place by coating or sputtering as a layer on the top or lateral sides of the outer envelope 11-52 or inner envelope 11-51.

In some examples, the peripheral structures 11-57 may include sidewalls coupled to the assembly substrates 11-56, and a top portion over the sidewalls and covering a top side of the electronic device 1100. In some examples, adhesive 11-23A may couple a top portion of the peripheral structures 11-57 to a top side of the electronic device 1100. The adhesive 11-23A may include a Thermal Interface Material (TIM) or an adhesive similar to the adhesive 11-23. In some examples, the perimeter structures 11-57 may lack a top portion and may include only perimeter sidewalls. In some examples, the sidewalls of the peripheral structures 11-57 may be coupled to the assembly substrates 11-56 by adhesives 11-23B. In some examples, the adhesive 11-23B may comprise a conductive adhesive, such as solder, that electrically couples the peripheral structures 11-57 to portions of the conductive structures of the assembly substrates 11-56, such as ground nodes. In some examples, the assembly interconnects 11-98 may be disposed on a bottom side of the assembly substrates 11-56. The assembly interconnects 11-98 may include or be referred to as conductive balls, conductive bumps, conductive pillars, or conductive pillars with solder caps.

When complete, the electronic assembly 1100A may include an electronic device 1100 having the connected dies 11-16 in an upward configuration. When the electronic assembly 1100A is manufactured in a matrix type, a singulation or sawing process may additionally be performed to separate the individual assemblies.

Fig. 14 shows a cross-sectional view illustrating an example electronic device 1400, connecting dies 11-16, and electronic assembly 1400A, in accordance with various aspects of the present disclosure. The features, materials, structures, or processes of the electronic device 1400, the connecting dice 11-16, and the electronic assembly 1400A may be similar to those of the example electronic device 1100, the connecting dice 11-16, and the electronic assembly 1100A shown in fig. 11-12. The example electronic device 1400 and the electronic assembly 1400A, or similarly-named portions thereof, may share any or all of the characteristics with any other device or assembly, or similarly-named portions thereof, disclosed herein.

In the example shown in fig. 14, the connection dies 11-16 are positioned in a face-down configuration in which the connection die interconnects 11-17 face the external substrates 11-46 and the connection die substrates 11-18 face the internal substrates 11-96.

Fig. 15A-15J show cross-sectional views of an example method of manufacturing an example electronic device 1400 and an example electronic assembly 1400A, in accordance with various aspects of the present disclosure. The example method shown in fig. 15A-15J may be similar to the example method shown in fig. 13A-13K, except that a face-down configuration of the connection dies 11-16 is used.

Fig. 15A shows a cross-sectional view of an electronic assembly 1400A at an early stage of fabrication. In the example shown in FIG. 15A, the device interconnects 11-14 may be formed or disposed on a support carrier 11-46A. The device interconnects 11-14 may include or be referred to as posts, rods, balls, leads, or bumps. In some examples, the features, materials, structures, or processes of fig. 15A may be similar to those of example 600B shown in fig. 6B, example 800B shown in fig. 8B, or example shown in fig. 13B, except that the device interconnects 11-14 are disposed on the support carriers 11-46A with no substrate therebetween.

Fig. 15B shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in fig. 15B, the connection dies 11-16 may be disposed on a support carrier 11-46A. In some examples, the adhesive 11-23 may be disposed between or on the connection die substrate 11-18 and the support carrier 11-46A. In some examples, the adhesives 11-23 may include or be referred to as adhesive tapes, adhesive films, or adhesive pastes. In some examples, the features, materials, structures, or processes of fig. 15B may be similar to those of example 600C shown in fig. 6C, example 800C shown in fig. 8C, or example shown in fig. 13C, except that the connection dies 11-16 are disposed on the support carriers 11-46A with no substrate therebetween.

In some examples, the internal components 11-16z (FIG. 14) may be disposed on the support carriers 11-46A. In some examples, the component interconnects 11-17z and the component enclosures 11-19z may be attached to the support carriers 11-46A. At a later time, the component interconnects 11-17z and the component encapsulants 11-19z can be coupled with the inner substrates 11-96, and the component bodies 11-15z can be coupled with the outer substrates 11-46.

Fig. 15C shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in FIG. 15C, the inner enclosures 11-51 may be disposed on support carriers 11-46A. The inner encapsulation 11-51 may cover not only the support carrier 11-46A but also the device interconnects 11-14 and the connection dies 11-16. In some examples, the thickness of the inner enclosure 11-51 may be greater than the thickness of the device interconnects 11-14 or the thickness of the connection dies 11-16. In this case, a thinning process, such as grinding or etching for reducing the height of the inner enclosures 11-51, may additionally be performed. In some examples, the top sides of the device interconnects 11-14 and the connection dies 11-16 may be exposed through the inner encapsulants 11-51 due to the thinning process. In some examples, the top side of the connection die interconnects 11-17 and the top side of the connection die encapsulants 11-19 may be exposed through the top side of the inner encapsulants 11-51. In some examples, the top sides of the device interconnects 11-14 and the top sides of the connection dies 11-16 may be coplanar with the top sides of the internal enclosures 11-51. In some examples, the top side of the connection die interconnects 11-17 and the top side of the connection die encapsulates 11-19 may be coplanar with the top side of the internal encapsulates 11-51. In some examples, the features, materials, structures, or processes of fig. 15C may be similar to the features, materials, structures, or processes of examples 600D and 600E shown in fig. 6D and 6E, examples 800D and 800E shown in fig. 8D and 8E, or examples shown in fig. 13D.

Fig. 15D shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in fig. 15D, the external substrates 11-46 may be formed or disposed on the device interconnects 11-14, the internal encapsulants 11-51, and the connection dies 11-16. The external substrates 11-46 may include dielectric structures 11-47 and conductive structures 11-48. In some examples, the dielectric structures 11-47 of the external substrates 11-46 may contact or may be formed on the internal encapsulant 11-51 and the connection die encapsulant 11-19. In some examples, the conductive structures 11-48 of the external substrates 11-46 can be coupled with device interconnects 11-14 or connection die interconnects 11-17. Thus, the connection dies 11-16 can be electrically connected to the external substrates 11-46 via the connection die interconnects 11-17. In some examples, the features, materials, structures, or processes of fig. 15D may be similar to the features, materials, structures, or processes of example 600A shown in fig. 6A, example 800A or 800F shown in fig. 8A or 8F, or example shown in fig. 13A or 13E.

Fig. 15E shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in fig. 15E, the external interconnects 11-92 may be formed or disposed on the external substrates 11-46. In some examples, the external interconnects 11-92 may be disposed on the conductive structures 11-48 of the external substrates 11-46. In some examples, the external interconnects 11-92 may include or be referred to as conductive balls, conductive bumps, conductive pillars, or solder caps. In some examples, the features, materials, structures, or processes of fig. 15E may be similar to the features, materials, structures, or processes of example 600L shown in fig. 6L, example 800M shown in fig. 8M, or example shown in fig. 13I.

Fig. 15F shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in fig. 15F, the support carriers 11-52A may be coupled over the external interconnects 11-92 or the external substrates 11-46 using an adhesive 223 that laterally defines the external interconnects 11-92, and the support carriers 11-46A may be removed. In some examples, as a result of removing the support carrier 11-46A, a top side of the connection dies 11-16, the internal encapsulation 11-51, and the device interconnects 11-14 may be exposed. In some examples, the adhesive 11-23 on the connection dies 11-16 may be exposed through the inner encapsulant 11-51.

Fig. 15G shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in fig. 15G, the adhesive 11-23 on the connection dies 11-16 may be removed as needed. In some examples, the adhesives 11-23 may be removed by a thinning process, such as grinding or etching. In some examples, the top sides of the device interconnects 11-14, the internal enclosures 11-51, or the connection die substrates 11-18 may be coplanar due to the thinning process. In some examples, the top side of the connection die substrates 11-18 may be exposed through the top side of the internal encapsulation 11-51. In some examples, the internal components 11-16z (FIG. 14) may also be exposed through the internal enclosure 11-51. In some examples, the top sides of the component interconnects 11-17z and the component enclosures 11-19z of the internal components 11-16z may be exposed through the top sides of the internal enclosures 11-51. In some examples, the features, materials, structures, or processes of fig. 15G may be similar to the features, materials, structures, or processes of examples 600D and 600E shown in fig. 6D and 6E, examples 800D and 800E shown in fig. 8D and 8E, or examples shown in fig. 13D.

Fig. 15H shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in fig. 15H, the internal substrates 11-96 can be formed or disposed on the device interconnects 11-14, the internal encapsulants 11-51, and the connection dies 11-16. The internal substrates 11-96 may include dielectric structures 11-97 and conductive structures 11-98. In some examples, the dielectric structures 11-97 of the internal substrates 11-96 may contact or may be formed on the internal encapsulant 11-51 and the connecting die substrates 11-18. In some examples, the conductive structures 11-98 of the internal substrates 11-96 may be coupled with the device interconnects 11-14 or the connection die substrates 11-18. Thus, the internal substrates 11-96 can be electrically connected to the device interconnects 11-14 and the connection dies 11-16. In some examples, the features, materials, structures, or processes of fig. 15H may be similar to the features, materials, structures, or processes of the example 800F shown in fig. 8F or the example shown in fig. 13E.

Fig. 15I shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in FIG. 15I, electronic components 11-11 and 11-12 may be coupled to the internal substrates 11-96. In some examples, electronic components 11-11 or 11-12 may be similar to

components

811a or 812a described herein. The electronic components 11-11 can include a set of component interconnects 11-11a having a relatively thin width or fine pitch and a set of component interconnects 11-11b having a relatively thick width or coarse pitch, and these sets of component interconnects 11-11a and 11-11b can be electrically connected to the conductive structures 11-98 of the internal substrates 11-96. The electronic components 11-12 can include a set of component interconnects 11-12a having a relatively thin width or fine pitch and a set of component interconnects 11-12b having a relatively thick width or coarse pitch, and these sets of component interconnects 11-12a and 11-12b can be electrically connected to the conductive structures 11-98 of the inner substrates 11-96.

In some examples, the underfill 11-61 may additionally be disposed between the electronic components 11-11, 11-12 and the internal substrate 11-96. The underfill 11-61 may be disposed between the electronic components 11-11 and 11-12 and the top side of the internal substrate 11-96, and may cover lateral sides of the electronic components 11-11 or 11-12. The underfill 11-61 may surround a lateral side of the module interconnect 11-11a, 11-11b, 11-12a, or 11-12 b. The underfill 11-61 may be disposed between the electronic components 11-11 and 11-12 and the top side of the internal substrate 11-96, and may cover lateral sides of the electronic components 11-11 or 11-12. The underfill 11-61 may surround a lateral side of the module interconnect 11-11a, 11-11b, 11-12a, or 11-12 b. In some examples, the features, materials, structures, or processes of fig. 15I regarding the coupling of electronic components 11-11 and 11-12 may be similar to the features, materials, structures, or processes of examples 600F and 600G shown in fig. 6F-6G, examples 800G and 800H shown in fig. 8G-8H, or examples shown in fig. 13F.

In some examples, the outer enclosures 11-52 may be disposed on the inner substrates 11-96 and the electronic components 11-11 and 11-12. In some examples, the outer enclosures 11-52 may cover the top sides of the inner substrates 11-96, the top sides and (or lateral) sides of the electronic components 11-11 and 11-12, or the underfills 11-61. In some examples, the top side of the outer enclosures 11-52 or the top sides of the electronic components 11-11 and 11-12 may be thinned by grinding or etching. In some examples, the top side of the outer enclosures 11-52 may be coplanar with the top sides of the electronic components 11-11 and 11-12. In some examples, the top sides of the electronic components 11-11 and 11-12 may be exposed through the top side of the outer enclosures 11-52. In some examples, the features, materials, structures, or processes of fig. 15I with respect to the outer enclosures 11-52 may be similar to the features, materials, structures, or processes of examples 600H and 600I shown in fig. 6H and 6I, examples 800I and 800J shown in fig. 8I and 8J, or examples shown in fig. 13G. In some examples, the support carrier 11-52A may be removed after the process of providing the outer enclosures 11-52, and thus the outer interconnects 11-92 may be exposed.

The electronic device 1400 may be completed after the support carriers 11-52A and the adhesive 223 are removed. The electronic device 1400 may include the connecting dice 11-16 in a face down configuration in which the high density connecting die substrates 11-18 face or are coupled to the internal substrates 11-96, and in which the connecting die interconnects 11-17 face or are coupled to the external substrates 11-46. Such a downward facing configuration may permit a high density of connecting dies 11-16 to electrically connect electronic components 11-11 and 11-12 to each other in a horizontal direction, and may also permit connecting dies 11-16 to electrically connect electronic components 11-11 and 11-12 to external substrates 11-46 in a vertical direction for transferring power or signals through connecting dies 11-16.

Fig. 15J shows a cross-sectional view of the electronic assembly 1400A at a later stage of fabrication. In the example shown in FIG. 15J, the electronic device 1400 may be disposed on the assembly substrates 11-56. In some examples, the external interconnects 11-92 of the electronic device 1400 may be electrically connected to the assembly substrates 11-56. In some examples, the underfill 11-61A may be applied between the electronic device 1400 and the assembly substrate 11-56. In some examples, electronic components 11-58 (fig. 14) may additionally be disposed on the assembly substrates 11-56, and may include active devices such as processors, microcontrollers, memory, or transistor devices, or passive devices such as resistors, capacitors, inductors, or Integrated Passive Devices (IPDs).

In some examples, the peripheral structures 11-57 may be disposed on the assembly substrates 11-56. The peripheral structures 11-57 may include or be referred to as covers, shrouds, fins, stiffeners, covers, or covers. In some examples, the assembly interconnects 11-98 may be disposed on a bottom side of the assembly substrates 11-56. The assembly interconnects 11-98 may include or be referred to as conductive balls, conductive bumps, conductive pillars, or conductive pillars with solder caps. In some examples, the features, materials, structures, or processes of fig. 15J may be similar to those of the examples shown in fig. 13J-13K.

When completed, the electronic assembly 1400A may include an electronic device 1400 having connected dies 11-16 in a face-down configuration. When the electronic assembly 1400A is manufactured in a matrix type, a singulation or sawing process may additionally be performed to separate the individual assemblies.

The discussion herein includes a number of illustrative figures that show various portions of a semiconductor device assembly (or package) and/or a method of manufacturing the same. For clarity of illustration, these drawings do not show all aspects of each example assembly. Any example assembly presented herein may share any or all of the characteristics with any or all of the other assemblies presented herein.

Various aspects of the present disclosure provide a semiconductor package structure and a method for manufacturing a semiconductor package. As a non-limiting example, various aspects of the present disclosure provide various semiconductor package structures including a connecting die that routes electrical signals between a plurality of other semiconductor dies, and methods of manufacturing the same. While the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the scope thereof. Therefore, it is intended that the disclosure not be limited to the particular examples disclosed, but that the disclosure will include all examples falling within the scope of the appended claims.

Claims

1. An electronic device, comprising:

a signal redistribution structure comprising a signal redistribution structure top side, a signal redistribution structure bottom side, and a plurality of signal redistribution structure lateral sides, wherein the signal redistribution structure is coreless;

a lower electronic component comprising a lower electronic component top side, a lower electronic component bottom side, and a plurality of lower electronic component lateral sides, wherein the lower electronic component top side is coupled to the signal redistribution structure bottom side;

a vertical interconnect structure coupled to the signal redistribution structure bottom side at a location laterally offset from the lower electronic component;

a lower electronic component interconnect structure coupled to the lower electronic component top side and the lower electronic component bottom side such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the lower electronic component interconnect structure;

a semiconductor die comprising a die top side, a die bottom side, and a plurality of die lateral sides;

a first die interconnect structure coupled to the signal redistribution structure top side and the die bottom side such that the semiconductor die is electrically coupled to the vertical interconnect structure; and

a second die interconnect structure coupled to the signal redistribution structure top side and the die bottom side such that the semiconductor die is electrically coupled to the lower electronic component.

2. The electronic device of claim 1, wherein:

the semiconductor die is electrically coupled to the vertical interconnect structure through at least the first die interconnect structure and the signal redistribution structure; and is

The semiconductor die is electrically coupled to the lower electronic component through at least the second die interconnect structure, the signal redistribution structure, and the lower electronic component interconnect structure.

3. The electronic device of claim 1, wherein the lower electronic component interconnect structure comprises a metal pillar.

4. The electronic device of claim 1, wherein the vertical interconnect structure vertically spans the lower electronic component and the lower electronic component interconnect structure.

5. The electronic device of claim 1, comprising a first encapsulant laterally surrounding the lower electronic component, the lower electronic component interconnect structure, and the vertical interconnect structure.

6. The electronic device of claim 5, wherein the lower electronic component bottom side is exposed from the first encapsulant material, and further comprising a layer of material contacting and covering the lower electronic component bottom side.

7. The electronic device of claim 5, comprising a second encapsulant laterally surrounding the semiconductor die separate from the first encapsulant.

8. The electronic device of claim 1, wherein the lower electronic component comprises a lower electronic component substrate and a lower electronic component enclosure on the lower electronic component substrate.

9. The electronic device of claim 1, wherein the lower electronic component comprises a connection die.

10. The electronic device of claim 1, wherein a first portion of the lower electronic component is positioned within a footprint of the semiconductor die and a second portion of the lower electronic component is positioned outside the footprint of the semiconductor die.

11. An electronic device, comprising:

a first signal redistribution structure comprising a first signal redistribution structure first side and a first signal redistribution structure second side opposite the first signal redistribution structure first side;

a vertical interconnect structure on a first side of the first signal redistribution structure;

a connection die on a first side of the first signal redistribution structure, comprising:

a connection die signal redistribution structure including a connection die signal redistribution structure first side facing away from the first signal redistribution structure, and a connection die signal redistribution structure second side facing toward the first signal redistribution structure;

a connection die interconnect coupled to the connection die signal redistribution structure second side and the first signal redistribution structure first side; and

a connection die encapsulation body encapsulating the connection die interconnect and the connection die signal redistribution structure second side; and

a second signal redistribution structure on the vertical interconnect structure and on the connection die signal redistribution structure first side, the second signal redistribution structure including a second signal redistribution structure first side facing away from the connection die and a second signal redistribution structure second side facing toward the connection die.

12. The electronic device of claim 11, comprising a first semiconductor die coupled to the first signal redistribution structure second side, and a second semiconductor die coupled to the first signal redistribution structure second side.

13. The electronic device of claim 11, comprising an encapsulation material that encapsulates the vertical interconnect structure, the connection die, the first signal redistribution structure first side, and the second signal redistribution structure second side.

14. The electronic device of claim 13, wherein the encapsulation material includes a side that is coplanar with a side of the connection die encapsulant.

15. The electronic device of claim 11, comprising an adhesive layer coupling the connection die signal redistribution structure first side to the second signal redistribution structure second side.

16. A method of manufacturing an electronic device, the method comprising:

providing a Signal Redistribution Structure (SRS) comprising a signal redistribution structure topside, a signal redistribution structure underside, and a plurality of signal redistribution structure lateral sides, wherein the signal redistribution structure is coreless;

providing a Lower Electronic Component (LEC) comprising a lower electronic component top side, a lower electronic component bottom side, and a plurality of lower electronic component lateral sides, wherein the lower electronic component top side is coupled to the signal redistribution structure bottom side;

providing a vertical interconnect structure coupled to the signal redistribution structure bottom side at a location laterally offset from the lower electronic component;

providing a lower electronic component interconnect structure coupled to the lower electronic component top side and the signal redistribution structure bottom side such that the lower electronic component is electrically coupled to the signal redistribution structure through at least the lower electronic component interconnect structure;

providing a semiconductor die comprising a die top side, a die bottom side, and a plurality of die lateral sides;

providing a first die interconnect structure coupled to the signal redistribution structure top side and the die bottom side such that the semiconductor die is electrically coupled to the vertical interconnect structure; and

providing a second die interconnect structure coupled to the signal redistribution structure top side and the die bottom side such that the semiconductor die is electrically coupled to the lower electronic component.

17. The method of claim 16, wherein:

18. The method of claim 16, further comprising:

providing a first encapsulant material laterally surrounding the lower electronic component, the lower electronic component interconnect structure, and the vertical interconnect structure, wherein the lower electronic component bottom side is exposed from the first encapsulant material; and

a layer of material is provided that contacts and covers the bottom side of the lower electronic component.

19. The method of claim 16, further comprising:

providing a second encapsulant laterally surrounding the semiconductor die separate from the first encapsulant,

wherein each of the signal redistribution structure lateral sides is coplanar with a respective lateral side of the first encapsulant material and coplanar with a respective lateral side of the second encapsulant material.

20. The method of claim 16, wherein the lower electronic component comprises a lower electronic component substrate and a lower electronic component enclosure on the lower electronic component substrate.