CN114253898A - Bus device and data read-write circuit - Google Patents
Bus device and data read-write circuit Download PDFInfo
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Abstract
The application provides a bus device and data read-write circuit, among the bus device, include: a forwarding module, a first I2C bus, and a second I2C bus; the voltage domains of the first I2C bus and the second I2C bus are different; the first I2C bus is connected with a master device and comprises a first clock line and a first data line; a second I2C bus connecting the slave devices, including a second clock line and a second data line; a forwarding module connected between the first I2C bus and the second I2C bus for performing the following communication strategies: and transmitting the signal on the first clock line to the second clock line in a single direction, and transmitting the signal on the first data line and the signal on the second data line in a double direction. The data transmission is realized by arranging the forwarding module so that the first I2C bus and the second I2C bus. In addition, the forwarding module in the application does not need to access other external clock signals, and therefore power consumption of the bus device is reduced.
Description
Technical Field
The present application relates to the field of communications, and in particular, to a bus device and a data read/write circuit.
Background
Currently, the I2C bus (Inter-Integrated Circuit) is a simple, bi-directional two-wire synchronous serial bus that can be widely used in a variety of microcontrollers and their peripherals. The I2C bus generally includes two signal lines, namely a data line and a clock line, and a master device and a plurality of slave devices can be connected to the I2C bus, so that the master device and the plurality of slave devices can communicate with each other through the I2C bus.
However, when communication between the master device and the slave device is realized through the I2C bus, it is found that the I2C bus in two different voltage domains cannot be directly connected for communication, and further, communication cannot be realized between devices connected by the I2C buses in the two different voltage domains.
Therefore, it is necessary to provide a new bus device to solve the problem of the inability to communicate between buses in different voltage domains.
Disclosure of Invention
The present application provides a bus device and a data read/write circuit, which are used to solve the problem in the related art that the I2C buses in different voltage domains cannot communicate with each other.
In a first aspect, the present application provides a bus apparatus comprising: a forwarding module, a first I2C bus, and a second I2C bus;
the voltage domains of the first I2C bus and the second I2C bus are different; the first I2C bus is connected with a master device and comprises a first clock line and a first data line; the second I2C bus is connected with a slave device and comprises a second clock line and a second data line;
the forwarding module is connected between the first I2C bus and the second I2C bus, and is used for executing the following communication strategies: and transmitting the signal on the first clock line to the second clock line in a single direction, and transmitting the signal on the first data line and the signal on the second data line in a double direction.
In one possible implementation manner, the forwarding module includes: the four input and output units are respectively in one-to-one correspondence with the first clock line, the first data line, the second clock line and the second data line;
the forwarding unit is provided with four groups of ports, and each group of ports comprises a control port, an input port and an output port; the output port and the input port are respectively connected with the corresponding input and output units, and the control port is connected with the control end of the corresponding input and output unit;
the forwarding unit is configured to output a first signal through an output port, where the first signal is in a first state, and control, based on a read-write state, an input/output unit corresponding to the output port to be in an output state or an input state, so as to execute the communication policy;
the input/output unit is connected with a corresponding clock line or data line and is used for being in an output state or an input state under the control of the forwarding unit; the output state is used for outputting the first signal to a corresponding clock line or data line so that the signal on the clock line or data line is in the first state; the input state is used for transmitting signals on the corresponding clock line or data line to the corresponding input port.
In one possible implementation, the bus device further includes: the pull-up modules are in one-to-one correspondence with the first clock lines, the first data lines, the second clock lines and the second data lines, and are used for controlling signals on the clock lines or the data lines corresponding to the input and output units to be in a second state when the corresponding input and output units are in an input state;
the forwarding unit is configured to control the input/output unit corresponding to the first clock line to be in an input state, and control the input/output unit corresponding to the second clock line to be in an output state or an input state based on whether a clock signal on the first clock line is in a first state or a second state;
the forwarding unit is further configured to control the input/output unit corresponding to the first data line to be in an input state when data is written; and controlling the input/output unit corresponding to the second data line to be in an output state or an input state based on the signal on the first data line being in a first state or a second state;
the forwarding unit is further configured to control the input/output unit corresponding to the second data line to be in an input state when data is read; and controlling the input/output unit corresponding to the first data line to be in an output state or an input state based on the signal on the second data line being in a first state or a second state.
In one possible implementation manner, the forwarding unit includes: the device comprises a control module, a first logic module and a second logic module;
the input end of the first logic module is connected with the output end of the control module and the input port corresponding to the first data line, and the output end of the first logic module is connected with the control port corresponding to the second data line;
the input end of the second logic module is connected with the output end of the control module and the input port corresponding to the second data line, and the output end of the second logic module is connected with the control port corresponding to the first data line;
the input end of the control module is connected with the input ports corresponding to the first data line and the first clock line, and the output end of the control module is connected with the first logic module and the second logic module and used for outputting a third signal to activate the first logic module and preset the output of the second logic module when data is written; and outputting a fourth signal to preset the output of the first logic module and activate the second logic module when reading data.
In one possible implementation, the first logic module includes a nand gate;
the first input end of the NAND gate is connected with the control module, and the second input end of the NAND gate is connected with the input port corresponding to the first data line; and the output end of the NAND gate is connected with the control port corresponding to the second data line.
In one possible implementation, the second logic module includes an or gate;
a first input end of the OR gate is connected with the control module, and a second input end of the OR gate is connected with the input port corresponding to the second data line; and the output end of the OR gate is connected with the control port corresponding to the first data line.
In one possible implementation, the first state represents a low level state and the second state represents a high level state;
in the forwarding unit, each output port is grounded; the control port corresponding to the first clock line is connected to a power supply, and the control port corresponding to the second clock line is connected with the input port corresponding to the first clock line;
the input/output unit is specifically used for responding to a low level signal output by a corresponding control port and is in an output state; and responding to the high level signal output by the corresponding control port and being in an input state.
In one possible implementation manner, the input-output unit includes: a tri-state gate;
the control end of the tri-state gate is connected with the corresponding control port, the first end of the tri-state gate is connected with the corresponding output port, and the second end of the tri-state gate is connected with the corresponding input port and the corresponding clock line or data line.
In a possible implementation manner, the first I2C bus is further connected to other slave devices, and data reading and writing are performed between the master device and the slave device on the first I2C bus through the first I2C bus.
In a second aspect, the present application provides a data reading and writing circuit, comprising: a master device, a slave device and a bus apparatus as claimed in any one of the first aspect.
The application provides a bus device and data read-write circuit, in bus device, include: a forwarding module, a first I2C bus, and a second I2C bus; the voltage domains of the first I2C bus and the second I2C bus are different; the first I2C bus is connected with a master device and comprises a first clock line and a first data line; the second I2C bus is connected with a slave device and comprises a second clock line and a second data line; the forwarding module is connected between the first I2C bus and the second I2C bus, and is used for executing the following communication strategies: transmitting the signal on the first clock line to the second clock line in a unidirectional way, and transmitting the signal on the first data line and the signal on the second data line in a bidirectional way; in other words, in the present application, in order to realize the transmission of signals on the I2C bus in different voltage domains, a forwarding module is provided in the bus device. The forwarding module is connected between the first I2C bus and the second I2C bus, so as to realize unidirectional transmission of signals on the first clock line to the second clock line and bidirectional transmission of signals between the first data line and the second data line, and thus data transmission can be realized between the forwarding module and the first I2C bus and the second I2C bus. In addition, the forwarding module in the application does not need to access other external clock signals, and therefore power consumption of the bus device is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic view of an application scenario of communication based on an I2C bus provided in the present application;
fig. 2 is a schematic structural diagram of a bus device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a forwarding module according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another forwarding module provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of a forwarding unit according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of another forwarding unit provided in the embodiment of the present application;
FIG. 7 is a schematic structural diagram of another bus device according to an embodiment of the present disclosure;
fig. 8 is a schematic state diagram of a forwarding module according to an embodiment of the present application;
fig. 9 is a timing diagram in a process of reading data of a forwarding module according to an embodiment of the present application;
fig. 10 is a timing diagram in a data writing process of a forwarding module according to an embodiment of the present application;
FIG. 11 is a schematic structural diagram of another bus device according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a data read/write circuit according to an embodiment of the present disclosure.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the present application.
Currently, the I2C bus (Inter-Integrated Circuit) is a simple, bi-directional two-wire synchronous serial bus that can be widely used in a variety of microcontrollers and their peripherals. The I2C bus generally includes two signal lines, namely a data line and a clock line, and a master device and a plurality of slave devices can be connected to the same I2C bus, so that the master device and the plurality of slave devices can communicate with each other through the I2C bus. For example, fig. 1 is a schematic diagram of an application scenario of communication based on an I2C bus provided in the present application. As shown in fig. 1, fig. 1 includes a master device and two slave devices (identified by slave device 1 and slave device 2 in the figure). In addition, the I2C bus in the figure further includes a data line (shown by SDA in the figure) and a clock line (shown by SCL in the figure), the master device, the slave device a, and the slave device b are respectively connected to the data line and the clock line in the figure, and further, the master device, the slave device a, and the slave device b perform read/write operations, so that data transmission can be directly realized according to the connected data line and clock line.
However, in the related art, the I2C buses in the two different voltage domains cannot be directly connected for communication, and further, the devices connected by the I2C buses in the two different voltage domains cannot be communicated with each other.
Therefore, it is necessary to provide a new bus device to solve the problem of the inability to communicate between buses in different voltage domains.
The present application provides a bus device and a data read/write circuit for solving the above technical problems.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 2 is a schematic structural diagram of a bus device according to an embodiment of the present disclosure, as shown in the figure, the bus device includes: a forwarding module, a first I2C bus, and a second I2C bus; wherein the voltage domains of the first I2C bus and the second I2C bus are different; the first I2C bus is connected with a master device and comprises a first clock line and a first data line; a second I2C bus connecting the slave devices, including a second clock line and a second data line; a forwarding module connected between the first I2C bus and the second I2C bus for performing the following communication strategies: and transmitting the signal on the first clock line to the second clock line in a single direction, and transmitting the signal on the first data line and the signal on the second data line in a double direction.
Exemplarily, in the present embodiment, in order to solve the technical problem that the I2C buses in two different voltage domains cannot directly communicate, the bus device in the present embodiment is provided with a forwarding module, a first I2C bus, and a second I2C bus. The first I2C bus includes a first data line (identified by SDA0 in the figure) and a first clock line (identified by SCL0 in the figure); the second I2C bus includes a second data line (identified in the figure by SDA1) and a second clock line (identified in the figure by SCL 1). The master device is connected to the first data line and the first clock line, the slave device 1 is connected to the second data line and the second clock line, and the first I2C bus and the second I2C bus are located in different voltage domains. In addition, the forwarding module is connected to a first data line in the first I2C bus, a first clock line, and a second data line and a second clock line in the second I2C bus, respectively.
In this embodiment, a signal on a first clock line connected to the master device is transmitted to a second clock line connected to the slave device, that is, the signal on the first clock line is synchronized to the second clock line, so that the state changes of the signals on the first clock line and the second clock line are the same. In addition, the forwarding module is further configured to implement bidirectional transmission of signals between the first data line and the second data line, that is, to transmit a signal on the first data line to the second data line or to transmit a signal on the second data line to the first data line.
In this embodiment, in order to realize the transmission of signals between the first I2C bus and the second I2C bus in different voltage domains, a forwarding module is disposed in the bus device. The forwarding module is connected between the first I2C bus and the second I2C bus, so as to realize unidirectional transmission of signals on the first clock line to the second clock line and bidirectional transmission of signals between the first data line and the second data line, and thus data transmission can be realized between the forwarding module and the first I2C bus and the second I2C bus. In addition, the forwarding module in this embodiment does not need to access other external clock signals, thereby reducing the power consumption of the bus device.
Fig. 3 is a schematic structural diagram of a forwarding module according to an embodiment of the present application. As shown, the forwarding module includes: the forwarding unit and the four input/output units are respectively in one-to-one correspondence with the first clock line, the first data line, the second clock line and the second data line. The forwarding unit is provided with four groups of ports, and each group of ports comprises a control port, an input port and an output port; the output port and the input port in each group of ports are respectively connected with the corresponding input and output unit, and the control port in each group of ports is connected with the control end of the corresponding input and output unit;
exemplarily, as shown in fig. 3, a forwarding module is provided with one forwarding unit and input/output units corresponding to the first data line, the second data line, the first clock line and the second clock line one to one. The forwarding unit is provided with an input port, an output port, and a control port corresponding to the first data line, the second data line, the first clock line, and the second clock line. Wherein, the input port, the output port and the control port of the first clock line are respectively identified by scl _ c _0, scl _ i _0 and scl _ oen _0 in the figure; the input port, output port and control port of the first data line are identified in the figure by sda _ c _0, sda _ i _0, sda _ oen _0, respectively; the input port, the output port and the control port of the second clock line are respectively identified by scl _ c _1, scl _ i _1 and scl _ oen _1 in the figure; the input port, output port and control port of the second data line are identified in the figure by sda _ c _1, sda _ i _1, sda _ oen _1, respectively. Specifically, when the connection is made, for the first data line, the control port corresponding to the first data line is connected to the control port corresponding to the input/output unit corresponding to the first data line, and the output port and the input port corresponding to the first data line are respectively connected to the input/output unit corresponding to the first data line. The connection relationship between the first clock line, the second clock line, and the second data line, the corresponding input/output unit, and the corresponding port of each group may refer to the connection relationship between the first data lines.
During actual work, the forwarding unit is used for outputting a first signal through the output port and controlling the input/output unit corresponding to the output port to be in an output state or an input state based on the read-write state so as to execute a communication strategy; the input/output unit is connected with the corresponding clock line or data line and is used for being in an output state or an input state under the control of the forwarding unit; the output state is used for outputting a first signal to a corresponding clock line or data line so as to enable the signal on the clock line or the data line to be in the first state; the input state is used for transmitting a signal on a corresponding clock line or data line to a corresponding input port, wherein the first signal is in a first state.
In this embodiment, the forwarding unit may be configured to control the input/output unit to be in an input state or an output state. Specifically, the forwarding unit first controls each output port (scl _ i _0, sda _ i _0, scl _ i _1, sda _ i _1) to output the first signal, and then controls each input/output unit to be in an output or input state based on the read or write state of the master device. For example, when the master device needs to read data in the slave device 1, the input/output unit 4 is controlled to be in an input state, and the forwarding unit adjusts a signal on the first data line (SDA0) corresponding to the input/output unit 3 based on a signal input by the input/output unit 4. When the master device needs to write data to the slave device 1, that is, when the master device transmits data to the slave device 1, the forwarding unit controls the input/output unit 3 to be in an input state, and the forwarding unit adjusts a signal state on the second data line (SDA1) connected to the input/output unit 4 based on a signal input by the input/output unit 3.
In addition, when the input/output unit is in an input state, the signal on the clock line or the data line connected with the input/output unit is directly transmitted to the input port corresponding to the forwarding unit. For example, when the input-output unit 3 is in an input state, at this time, a signal on the first data line (SDA0) is transmitted to the input port scl _ c _0 of the forwarding unit through the input-output unit.
When the input-output unit is in the output state, the input-output unit outputs the first signal to the correspondingly connected clock line or data line, so that the signal on the clock line or data line connected with the input-output unit is in the first state. For example, when the input/output unit 3 is in the output state, the signal (i.e., the first signal) on the SDA _ i _0 port of the forwarding unit is output to the first data line (SDA0) through the input/output unit, so that the signal state on the first data line is the same as the signal output state (i.e., the first state) of the SDA _ i _0 port.
Fig. 4 is a schematic structural diagram of another forwarding module provided in the embodiment of the present application. In addition to the structure shown in fig. 3, the bus apparatus further includes: and the pull-up modules correspond to the first clock line, the first data line, the second clock line and the second data line one to one. When the input/output unit connected with the forwarding unit is in an input state, the pull-up module can be used for controlling the signal state on the clock line or the data line connected with the input/output unit to be in a second state when the input/output unit connected with the forwarding unit is in the input state.
And when the forwarding unit works specifically, the forwarding unit is used for controlling the input/output unit corresponding to the first clock line to be in an input state, and controlling the input/output unit corresponding to the second clock line to be in an output state or an input state based on the clock signal on the first clock line being in the first state or the second state.
Illustratively, for the clock line in the bus device, the forwarding unit in this embodiment is used to transmit the signal on the first clock line to the second clock line in one direction, i.e. the forwarding unit controls the input/output unit 1 to be in an input state, and the forwarding unit further controls the input state or the output state of the input/output unit 2 connected to the second clock line based on the state of the signal on the first clock line input by the input/output unit 1.
When the signal state on the first clock line is in the first state, the input/output unit 2 is controlled to be in the output state, that is, the input/output unit 2 controls the signal state on the SCL1 to be in the first state according to the first signal output from the SCL _ i _1 output port. When the signal state on the first clock line is in the second state, the control input-output unit 2 is in the input state at this time, i.e. the signal state on SCL1 is in the second state by the control of the pull-up module 2 at this time.
When the data writing device works specifically, the forwarding unit is also used for controlling the input and output unit corresponding to the first data line to be in an input state when data is written; and controlling the input and output unit corresponding to the second data line to be in an output state or an input state based on the signal on the first data line being in the first state or the second state.
Illustratively, for the data lines in the bus apparatus, when the master device writes data to the slave device 1, the input/output unit 3 controlling the connection of the first data line is in an input state, and when a signal to be written is transmitted on the first data line, the forwarding unit controls the input or output state of the input/output unit 4 corresponding to the second unit based on the state of the signal transmitted on the first data line.
When the signal state on the first data line is in the first state, the input/output unit 4 is controlled to be in the output state, that is, the input/output unit 4 controls the signal state on the SDA1 to be in the first state according to the signal output from the SDA _ i _1 output port. When the state of the signal on the first data line is in the second state, the control input-output cell 4 is in the input state at this time, i.e., the signal on SDA1 is in the second state by the control of pull-up module 4.
During specific work, the forwarding unit is also used for controlling the input/output unit corresponding to the second data line to be in an input state when data is read; and controlling the input and output unit corresponding to the first data line to be in an output state or an input state based on the signal on the second data line being in the first state or the second state.
Illustratively, for the data lines, when the master device reads data from the slave device 1, the input/output unit 4 connected to the second data line is controlled to be in an input state, and when a signal to be read is transmitted on the second data line, the forwarding unit controls the input or output state of the input/output unit 3 corresponding to the first data line based on the state of the signal transmitted on the second data line.
When the signal state on the second data line is in the first state, the input/output unit 3 is controlled to be in the output state, that is, the input/output unit 3 controls the signal state on the SDA0 to be in the first state according to the signal output from the SDA _ i _0 output port. When the state of the signal on the second data line is in the second state, the input-output unit 3 is controlled to be in the input state at this time, that is, the signal on the SDA0 is controlled to be in the second state by the pull-up module 3.
Fig. 5 is a schematic structural diagram of a forwarding unit according to an embodiment of the present application. As shown, the forwarding unit includes: the device comprises a control module, a first logic module and a second logic module.
Specifically, the input end of the first logic block is connected with the output end of the control module and the input port (i.e. sda _ c _0 in the figure) corresponding to the first data line, and the output end of the first logic block is connected with the control port (i.e. sda _ oen _1 in the figure) corresponding to the second data line. The input end of the second logic block is connected with the output end of the control block and the corresponding input port (namely sda _ c _1 in the figure) of the second data line, and the output end of the second logic block is connected with the corresponding control port (namely sda _ oen _0 in the figure) of the first data line.
The input end of the control module is respectively connected with the input ports (namely sda _ c _0, sda _ c _1 and scl _ c _0 in the figure) corresponding to the first data line and the first clock line, and the output end of the control module is connected with the first logic module and the second logic module, and is used for outputting a third signal to activate the first logic module and preset the output of the second logic module when data is written; and outputting a fourth signal to preset the output of the first logic module and activate the second logic module when reading the data.
Illustratively, when the forwarding unit controls the input-output unit to be in an input or output state, the control may be implemented in the following manner. The forwarding unit in this embodiment includes a control module, a first logic module, and a second logic module. When the first logic module is used for writing data to the slave device 1 by the master device, at this time, the control module outputs a third signal to the first logic module and the second logic module connected to the output end, and the first logic module is in an active state after receiving the third signal, that is, the output signal of the first logic module can be determined by the state of the signal at the input end corresponding to the second data line, and further the output signal of the control port corresponding to the second data line connected to the output end of the first logic module is changed by changing the state of the output signal of the first logic module, so that the input/output unit 4 is in an input state or an output state based on the signal output by the control end corresponding to the second data line. And, the second logic module is in a preset state under the action of the third signal, that is, at this time, the state of the output signal of the second logic module does not change with the state of the signal on the first data line connected thereto, and the state of the signal output by the control port corresponding to the first data line connected to the output end of the second logic module also remains unchanged, so that the input/output unit 3 corresponding to the first data line is in an input state based on the state of the output signal of the second logic module.
The control module is further configured to, when the master device reads data on the slave device, output a fourth signal to the first logic module and the second logic module connected to the output end by the control module, and then the second logic module is in an active state after receiving the fourth signal, that is, the output signal of the second logic module can be determined by the state of the signal at the input end corresponding to the first data line, and further change the output signal of the control port corresponding to the first data line connected to the output end of the second logic module by changing the state of the output signal of the second logic module, so that the input/output unit 3 corresponding to the first data line is in an input state or an output state based on the state of the signal output by the control end corresponding to the first data line. And, the first logic module is in a preset state under the action of the fourth signal, that is, at this time, the state of the output signal of the first logic module does not change with the state of the signal on the second data line connected thereto, and the state of the signal output by the control port corresponding to the second data line connected to the output end of the first logic module also remains unchanged, so that the input/output unit 4 corresponding to the second data line is in an input state based on the state of the output signal of the second logic module. In practical applications, the control module in the forwarding unit may comprise a plurality of triggers. When the signals on the first I2C bus are not inverted, all the flip-flops in the forwarding unit do not work, so that the dynamic power consumption of the bus device is reduced.
Fig. 6 is a schematic structural diagram of another forwarding unit provided in the embodiment of the present application. As shown in the figure, on the basis of the structure of the forwarding unit shown in fig. 5, the first logic module in this embodiment includes a nand gate. The first input end of the NAND gate is connected with the control module, and the second input end of the NAND gate is connected with the input port corresponding to the first data line; the output end of the NAND gate is connected with the control port corresponding to the second data line.
In some examples, when the input port sda _ c _0 of the first data line needs to transmit data to the second data line, at this time, the nand gate is activated by a third signal output from the control module, and a second input terminal of the nand gate is connected to the input port sda _ c _0 of the first data line through a not gate, the NAND gate can control the input/output unit 4 connected with the output terminal of the NAND gate according to the state of the signal output by the first data line, so that the signal state of the second data line SDA _1 connected to the input-output unit 4 is changed as the signal state of the input port SDA _ c _0 corresponding to the first data line is changed, that is, when the signal state input to the input port corresponding to the first data line is at a high level, the signal state of the second data line SDA _1 obtained by the control is also at a high level. When the signal state input from the first input port is at a low level, the signal state of the second data line SDA _1 obtained by the control is also at a low level. And when the control module outputs the fourth signal, the output of the NAND gate is in a preset state.
Further, in the present embodiment, the second logic module includes an or gate; the first input end of the OR gate is connected with the control module, and the second input end of the OR gate is connected with the input port corresponding to the second data line; and the output end of the OR gate is connected with the control port corresponding to the first data line.
In particular, in practical applications, the first state may represent a low level state, and the second state may be used to represent a high level state; in the forwarding unit, each output port (i.e., scl _ i _0, sda _ i _0, scl _ i _1, and sda _ i _1) is grounded, so that the signals output by the output ports are low-level signals; the control port scl _ oen _0 corresponding to the first clock line is connected to the power supply, the control port scl _ oen _1 corresponding to the second clock line is connected to the input port scl _ c _0 corresponding to the first clock line, and the forwarding unit can control the control port corresponding to the second clock line according to the state of the signal on the first clock line so that the signal state on the second clock line is consistent with the signal state on the first clock line, and further realize the unidirectional transmission of the signal on the first clock line to the second clock line.
In the practical application, the input/output unit is specifically configured to be in an output state in response to a low level signal output by a corresponding control port; and responding to the high level signal output by the corresponding control port and being in an input state.
In this practical application, the input/output unit is exemplified as a tri-state gate. Fig. 7 is a schematic structural diagram of another bus device according to an embodiment of the present disclosure. On the basis of the structure shown in fig. 4, the input-output unit in the present embodiment includes: a tri-state gate; the control end of the tri-state gate is connected with the corresponding control port, the first end of the tri-state gate is connected with the corresponding output port, and the second end of the tri-state gate is connected with the corresponding input port and the corresponding clock line or data line. With reference to the schematic structural diagram of the bus device shown in fig. 7 and the forwarding unit shown in fig. 6, the bus device operates according to the following principle:
for a clock line in the bus device, the forwarding unit realizes that the signal state on the first clock line SCL _0 is unidirectionally transmitted to the second clock line SCL _1, and when the clock signal is specifically controlled, the clock signal is transmitted from the first clock line to the second clock line, so that the output port SCL _ c _1 corresponding to the first clock line can be suspended and disconnected. Furthermore, the input port SCL _ c _0 corresponding to the first clock line is connected to the control port corresponding to the second clock line SCL _ oen _1, and when the signal inputted to the input port SCL _ c _0 corresponding to the first clock line is in a low level state, the signal of the control terminal SCL _ oen _1 corresponding to the second clock line connected thereto is also in a low level state, because the control terminal SCL _ oen _1 corresponding to the second clock line is also connected to the control terminal of the tristate gate in the input/output unit 2, and when the tristate gate receives a low level signal at the control terminal, the tristate gate controls the signal state on the SCL _1 connected to the second terminal of the tristate gate according to the signal state outputted from the output port SCL _ i _1 connected to the first terminal, because SCL _ i _1 is grounded, the signal state outputted therefrom is a low level signal, and further the signal state on the second clock line is also in a low level state, when the input port scl _ c _0 corresponding to the first clock line is at a low level, the signal state on the second clock line is also at a low level. When the signal input by the input port SCL _ c _0 corresponding to the first clock line is in a high level state, the signal of the control terminal SCL _ oen _1 corresponding to the second clock line connected to the control terminal SCL _ oen _0 is also in a high level state, and the tri-state gate connected to SCL _ oen _1 is in an off state based on the high level signal, so that the signal state on the second clock line SCL _1 is in a high level state based on the pull-up module 2, and the signal state on the second clock line is also in a high level state when the input port SCL _ c _0 corresponding to the first clock line is in a high level state.
For the bus device in the present embodiment, the forwarding unit can perform bidirectional transmission of signals on the first data line and the second data line. This process is divided into two cases in which,
the first case is: the master device connected with the first data line needs to write data into the slave device connected with the second data line, and at the moment:
when the control module outputs a third signal, and the third signal is a signal in a high level state, the or gate in the second logic module connected to the control module also receives the high level signal, and then the control port SDA _ oen _0 corresponding to the first data line connected to the output end of the or gate is in a high level state, and the tri-state gate connected to SDA _ oen _0 is in an off state (that is, at this time, the signal on SDA _ i _0 does not affect the signal state on SDA _0 through the tri-state gate), and then the signal state on the first data line SDA _0 can be input into the forwarding unit through the SDA _ c _0 port, so that the input/output unit 3 where the tri-state gate is currently located is in an input state.
In addition, when the control module in the forwarding unit outputs a third signal, and the third signal is a signal in a high level state, and further the nand gate in the first logic module connected to the output end of the control module, because the input of one end of the nand gate is a high level signal, when the signal input from the input port sda _ c _0 corresponding to the first data line is a low level signal, the low level signal is input to the second input end of the nand gate connected thereto through a not gate, and the signal output by the nand gate based on the signals input from the first input end and the second input end is also in a low level state, so that the control port sda _ oen _1 corresponding to the second data line connected to the output end of the nand gate receives a low level signal, the control end of the tri-state gate connected to sda _ oen _1 also receives a low level signal, and further the tri-state gate receives a low level signal based on the control end, the state of the signal on SDA _1 connected to the second end of the tri-state gate is controlled by the tri-state gate according to the state of the signal output from the output port SDA _ i _1 connected to the first end of the tri-state gate (i.e., the input/output unit 4 where the tri-state gate is in the output state), since SDA _ i _1 is grounded, the output signal state is a low level signal, and further the signal state on the second data line SDA _1 is also in the low level state, so that when the input port SDA _ c _0 corresponding to the first data line is in the low level state, the signal state on the second data line is also in the low level state. When the signal inputted to the input port SDA _ c _0 corresponding to the first data line is a high-level signal, and the high-level signal is inputted to the second input terminal of the nand gate connected thereto through a not gate, the signal outputted by the nand gate based on the signals inputted from the first input terminal and the second input terminal is also in a high-level state, so that the control port SDA _ oen _1 corresponding to the second data line connected to the output terminal of the nand gate receives the high-level signal, the control terminal of the tri-state gate connected to SDA _ oen _1 also receives the high-level signal, and the tri-state gate turns off based on the high-level signal received by the control terminal, so that the signal state on SDA _1 connected to the second terminal of the tri-state gate is in a high-level state under the action of the pull-up module 4 connected thereto, so as to realize that the input port SDA _ c _0 corresponding to the first data line is in a high-level state, the signal state on the second data line is also in a high level state, so that the data on the first data line is written into the second data line.
The second case is that the master device connected to the first data line needs to read data in the slave device connected to the second data line, and at this time:
and outputting a fourth signal at the control module, wherein the fourth signal is a signal in a low level state, at this time, the nand gate in the first logic module connected with the control module outputs a high level signal based on the low level signal, and the output high level signal is not influenced by the signal state of the input end sda _ c _0 corresponding to the first data line connected with the nand gate. The high-level signal output by the nand gate is transmitted to the control port SDA _ oen _1 corresponding to the second data line connected to the nand gate, and further transmitted to the control end of the tri-state gate in the input/output unit 4 connected to the control end through the control port SDA _ oen _1, so that the tri-state gate is in an off state (i.e., at this time, the signal on SDA _ i _1 does not affect the signal state on SDA _1 through the tri-state gate), and further the signal state on the second data line SDA _1 can be input to the forwarding unit through the SDA _ c _1 port.
In addition, when the control module in the forwarding unit outputs a fourth signal, and the fourth signal is a signal in a low level state, and then the or gate in the second logic module connected to the output end of the control module, because the input of one end of the or gate is a low level signal, when the signal input to the input port SDA _ c _1 corresponding to the second data line is a low level signal, the signal output by the or gate based on the signals input to the first input end and the second input end is also in a low level state, so that the control port SDA _ oen _0 corresponding to the first data line connected to the output end of the or gate receives a low level signal, the control end of the tri-state gate connected to SDA _ oen _0 also receives a low level signal, and the tri-state gate controls the signal state on the output port SDA _ i _0 connected to the second end of the tri-state gate based on the low level signal received by the control end, (SDA _ oen _0) the signal state on the second end of the tri-state gate based on the signal output by the output port SDA _ i _0 connected to the first end of the tri-state gate That is, the input/output unit 3 in which the tri-state gate is in the output state) is grounded, and thus the output signal state is a low level signal, and further the signal state on the first data line SDA _0 is also a low level state, so that when the input port SDA _ c _1 corresponding to the second data line is low level, the signal state on the first data line is also a low level state. When the signal inputted to the input port sda _ c _1 corresponding to the second data line is a high level signal, the or gate outputs a signal based on the signals input from the first input terminal and the second input terminal in a high state, so that the control port sda _ oen _0 corresponding to the first data line connected to the output terminal of the or gate receives a high level signal, the control terminal of the tri-state gate connected to sda _ oen _1 also receives the high level signal, and the tri-state gate, based on the high level signal received by the control terminal, the tri-state gate is turned off, so that the signal state on SDA _0 connected to the second terminal of the tri-state gate is in a high state by the action of the pull-up module 3 connected thereto, when the input port sda _ c _1 corresponding to the second data line is at a high level, the signal state on the first data line is also at a high level, so that data on the second data line can be read from the first data line.
In fig. 7, the forwarding unit further includes an rst _ n port, which can be used to initialize the forwarding unit.
Fig. 8 is a schematic state diagram of a forwarding module according to an embodiment of the present application. As shown in fig. 8, for the forwarding module in the bus device, the forwarding module may be initially set to receive a signal on the first clock line SCL _0 and a signal on the first data line SDA _0, and when a start signal sent by the master device is detected, a state REC _ CTRL of starting communication is entered, in which the master device sends a control signal including an address of the slave device 1 requesting communication and a read-write state. Then, the control module in the forwarding module outputs a third signal (high level signal) to forward the master control signal. After the forwarding of the master device signal is completed, the forwarding module enters a wait acknowledge state CHECK _ ACK, and generates a fourth signal (low level signal) through a control module in the forwarding module, forwards a response signal of the slave device 1, and simultaneously determines a read-write signal, where the start signal is generated by the master device, and when the forwarding module monitors that a signal on the first clock line is at a high level, the master device converts the signal state on the first data line from a high level turntable to a low level state at this time, and then uses the signal converted to the low level as a start signal.
If the forwarding module determines that the received signal is a read signal, the forwarding module enters a wait-to-RECEIVE state RECEIVE, and a control module in the forwarding module generates a fourth signal to forward the read data sent by the slave device 1. When the data transmission of the slave device 1 is finished, the forwarding module enters a RECEIVE acknowledge state RECEIVE _ ACK, and at this time, the control module in the forwarding module generates a third signal to forward the response or non-response signal generated by the master device. And if the response signal is forwarded by the forwarding module, entering a receiving waiting state again to continuously read data. If the forwarding module forwards the non-response signal, the system enters a pause state STOP, and at this time, the control module in the forwarding module generates a third signal to wait for detecting a new response signal generated by the master device. As shown in fig. 9, fig. 9 is a timing diagram in a data reading process of a forwarding module according to an embodiment of the present application, where signals from top to bottom in the timing diagram sequentially represent signals of ports scl _ c _0, sda _ c _0, scl _ c _1, sda _ c _1, rst _ n, scl _ i _0, sda _ i _0, scl _ i _1, sda _ i _1, scl _ oen _0, sda _ oen _0, scl _ oen _1, sda _ oen _1, and strobe signal. The strobe signal is used to characterize the signal generated by the control module in the forwarding module. In the process of reading data, the signal state change of the input port corresponding to the first data line is consistent with the signal state change of the input port corresponding to the second data line through the control of the forwarding module. The termination signal is shown as an end signal triggered by the master device by changing SDA0 from output low to output high when SCL0 is high when I2C communication is no longer required.
And if the forwarding module determines that the write signal is the write signal, entering a sending waiting state SEND, and generating a third signal by a control module in the forwarding module and forwarding the signal on the first data line of the master device. After the master device signal is completely forwarded, the forwarding module enters a waiting for acknowledgement state SEND _ ACK, and at this time, the control module in the forwarding module generates a fourth signal to forward the response signal sent by the slave device 1. After the slave device 1 finishes transmitting the response signal, the slave device enters the sending waiting state SEND again, the control module in the transmitting module generates a third signal to transmit the master device signal, and in the process, the transmitting module can continuously write data into the slave device 1 or wait for detecting a new start signal. As shown in fig. 10, fig. 10 is a timing diagram of a data writing process of a forwarding module according to an embodiment of the present application, where signals from top to bottom in the diagram sequentially represent signals of ports scl _ c _0, sda _ c _0, scl _ c _1, sda _ c _1, rst _ n, scl _ i _0, sda _ i _0, scl _ i _1, sda _ i _1, scl _ oen _0, sda _ oen _0, scl _ oen _1, sda _ oen _1, and strobe signal. The strobe signal is used to characterize the signal generated by the control module in the forwarding module. In the process of writing data, the signal state change of the input port corresponding to the second data line is kept consistent with the signal state change of the input port corresponding to the first data line through the control of the forwarding module.
The control logic of the forwarding module provided in this embodiment is simple, and the transmission direction of the forwarding data of the forwarding module can be determined only by controlling the signal output by the control module in the forwarding module to be the third signal or the fourth signal. When the signal is a third signal, the data is transmitted from the direction of the master device to the direction of the slave device; when it is the fourth signal, the data is transmitted from the direction of the slave 1 to the direction of the master at this time.
Fig. 11 is a schematic structural diagram of another bus device according to an embodiment of the present disclosure. On the basis of the structure shown in fig. 2, the present embodiment further includes other slave devices, for example, the slave device 2 in the figure. The slave device is connected to a first I2C bus, and data reading and writing are performed between the master device and the slave device (i.e., the slave device 2 in the figure) on the first I2C bus through the first I2C bus. Specifically, the communication process is similar to that in the related art, and is not described herein again.
Fig. 12 is a schematic structural diagram of a data read/write circuit according to an embodiment of the present disclosure, as shown in the figure, the data read/write circuit includes a master device, a slave device, and a bus device according to any one of the embodiments, so that a process of reading and writing data between the master device and the slave device connected to buses in different voltage domains can be implemented by the bus device, and communication between the master device and the slave device is implemented.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A bus apparatus, comprising: a forwarding module, a first I2C bus, and a second I2C bus;
the voltage domains of the first I2C bus and the second I2C bus are different; the first I2C bus is connected with a master device and comprises a first clock line and a first data line; the second I2C bus is connected with a slave device and comprises a second clock line and a second data line;
the forwarding module is connected between the first I2C bus and the second I2C bus, and is used for executing the following communication strategies: and transmitting the signal on the first clock line to the second clock line in a single direction, and transmitting the signal on the first data line and the signal on the second data line in a double direction.
2. The bus apparatus of claim 1, wherein the forwarding module comprises: the four input and output units are respectively in one-to-one correspondence with the first clock line, the first data line, the second clock line and the second data line;
the forwarding unit is provided with four groups of ports, and each group of ports comprises a control port, an input port and an output port; the output port and the input port are respectively connected with the corresponding input and output units, and the control port is connected with the control end of the corresponding input and output unit;
the forwarding unit is configured to output a first signal through an output port, where the first signal is in a first state, and control, based on a read-write state, an input/output unit corresponding to the output port to be in an output state or an input state, so as to execute the communication policy;
the input/output unit is connected with a corresponding clock line or data line and is used for being in an output state or an input state under the control of the forwarding unit; the output state is used for outputting the first signal to a corresponding clock line or data line so that the signal on the clock line or data line is in the first state; the input state is used for transmitting signals on the corresponding clock line or data line to the corresponding input port.
3. The bus apparatus according to claim 2, wherein the bus apparatus further comprises: the pull-up modules are in one-to-one correspondence with the first clock lines, the first data lines, the second clock lines and the second data lines, and are used for controlling signals on the clock lines or the data lines corresponding to the input and output units to be in a second state when the corresponding input and output units are in an input state;
the forwarding unit is configured to control the input/output unit corresponding to the first clock line to be in an input state, and control the input/output unit corresponding to the second clock line to be in an output state or an input state based on whether a clock signal on the first clock line is in a first state or a second state;
the forwarding unit is further configured to control the input/output unit corresponding to the first data line to be in an input state when data is written; and controlling the input/output unit corresponding to the second data line to be in an output state or an input state based on the signal on the first data line being in a first state or a second state;
the forwarding unit is further configured to control the input/output unit corresponding to the second data line to be in an input state when data is read; and controlling the input/output unit corresponding to the first data line to be in an output state or an input state based on the signal on the second data line being in a first state or a second state.
4. The bus apparatus according to claim 3, wherein the forwarding unit comprises: the device comprises a control module, a first logic module and a second logic module;
the input end of the first logic module is connected with the output end of the control module and the input port corresponding to the first data line, and the output end of the first logic module is connected with the control port corresponding to the second data line;
the input end of the second logic module is connected with the output end of the control module and the input port corresponding to the second data line, and the output end of the second logic module is connected with the control port corresponding to the first data line;
the input end of the control module is connected with the input ports corresponding to the first data line and the first clock line, and the output end of the control module is connected with the first logic module and the second logic module and used for outputting a third signal to activate the first logic module and preset the output of the second logic module when data is written; and outputting a fourth signal to preset the output of the first logic module and activate the second logic module when reading data.
5. The bus device of claim 4, wherein the first logic module comprises a NAND gate;
the first input end of the NAND gate is connected with the control module, and the second input end of the NAND gate is connected with the input port corresponding to the first data line; and the output end of the NAND gate is connected with the control port corresponding to the second data line.
6. The bus apparatus of claim 4, wherein the second logic module comprises an OR gate;
a first input end of the OR gate is connected with the control module, and a second input end of the OR gate is connected with the input port corresponding to the second data line; and the output end of the OR gate is connected with the control port corresponding to the first data line.
7. The bus apparatus of claim 4, wherein the first state represents a low state and the second state represents a high state;
in the forwarding unit, each output port is grounded; the control port corresponding to the first clock line is connected to a power supply, and the control port corresponding to the second clock line is connected with the input port corresponding to the first clock line;
the input/output unit is specifically used for responding to a low level signal output by a corresponding control port and is in an output state; and responding to the high level signal output by the corresponding control port and being in an input state.
8. The bus apparatus according to claim 2, wherein the input/output unit comprises: a tri-state gate;
the control end of the tri-state gate is connected with the corresponding control port, the first end of the tri-state gate is connected with the corresponding output port, and the second end of the tri-state gate is connected with the corresponding input port and the corresponding clock line or data line.
9. The bus device as claimed in any one of claims 1 to 8, wherein the first I2C bus is further connected to other slave devices, and data reading and writing between the master device and the slave devices on the first I2C bus are performed through the first I2C bus.
10. A data read/write circuit, comprising: a master device, a slave device and a bus arrangement as claimed in any one of claims 1 to 9.
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| CN115080493A (en) * | 2022-07-07 | 2022-09-20 | 上海集成电路研发中心有限公司 | Bus device and data read-write circuit |
| CN116541320A (en) * | 2023-05-22 | 2023-08-04 | 深圳市海思科自动化技术有限公司 | Intelligent IO module bus communication method, IO module, terminal and medium |
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