CN114253763A - Storage device and control system thereof - Google Patents
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- CN114253763A CN114253763A CN202010992639.8A CN202010992639A CN114253763A CN 114253763 A CN114253763 A CN 114253763A CN 202010992639 A CN202010992639 A CN 202010992639A CN 114253763 A CN114253763 A CN 114253763A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
- G06F11/1458—Management of the backup or restore process
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1474—Saving, restoring, recovering or retrying in transactions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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Abstract
A storage device comprises a control system, wherein the control system comprises two mainboards, two control modules and two non-volatile memories. The two control modules respectively read a firmware program code from the two non-volatile memories to execute a firmware so as to respectively operate in a master control mode and a controlled mode. When the control module operating in the master control mode is abnormal in the operation process, the control module operating in the controlled mode is converted into the master control mode, the control module operating in the controlled mode is controlled to be converted into a reduction mode, and the firmware program code stored in the corresponding volatile memory is transmitted to the control module operating in the abnormal mode so as to update the corresponding non-volatile memory.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to a storage device and a control system thereof, and more particularly, to a storage device with automatic repair and backup functions and a control system thereof.
[ background of the invention ]
An existing Enterprise (Enterprise) storage system belongs to a High Availability (HA) system, and includes a power unit, a fan unit, two mainboards, two control modules (IOMs), and at least one hard disk. The two control modules are respectively arranged on the two mainboards and used for monitoring and managing each hard disk, the power supply unit and the fan unit, and respectively operate in a master control (Active) mode and a controlled (Passive) mode after being powered on so as to be used as a backup system. Each control module is initialized to read a Firmware program code (e.g., Image) from a corresponding non-volatile memory to execute a Firmware (Firmware), and when the control module operating in the master mode is abnormal, one of the main reasons is that the corresponding Firmware is in error.
To solve the problem of firmware error, a simple method of the prior art is to replace the corresponding motherboard, but it will consume much labor, money and time. Another method of the prior art is to provide two non-volatile memories corresponding to the control module on each motherboard, and store the same firmware program code in both non-volatile memories, i.e. one of the non-volatile memories is to be read by default after the control module is powered on, and the other is used as a Backup (Backup), or one of the non-volatile memories stores an updated version of the firmware program code, and the other stores a version of the firmware program code that can be run when the motherboard leaves the factory. For example, when the firmware executed by the control module operating in the master control mode has an error, the control module reads the firmware program code as a backup to operate normally, however, such an approach requires two nonvolatile memories corresponding to the control module to be disposed on each motherboard, which not only wastes the cost of the nonvolatile memories, but also occupies the space of the circuit board. Furthermore, another approach is: when the control module operating in the master control mode reads the firmware program code from the nonvolatile memory and executes the firmware program code to cause the control module to generate an abnormal condition, the other control module is switched from the controlled mode to the master control mode to maintain the normal operation of the storage system.
At this time, although the storage system still operates normally, the firmware on the nonvolatile memory that causes the control module to generate the exception is still to be manually re-written by an engineer or a user to the firmware program code of another version that can operate normally. Therefore, it is a problem to be solved whether the storage system for enterprises has other firmware exception handling methods.
[ summary of the invention ]
The invention aims to provide a storage device with automatic repair and backup functions and a control system thereof.
In order to solve the above technical problems, the present invention provides a control system for a storage device, which is suitable for a power unit, a fan unit, and at least one hard disk, and comprises two main boards, two control modules, and two non-volatile memories. The two control modules are respectively arranged on the two mainboards, are electrically connected with each other and are electrically connected with the power supply unit, the fan unit and the at least one hard disk respectively, so as to be used for monitoring and managing the power supply unit, the fan unit and the at least one hard disk. The two non-volatile memories are respectively arranged on the two mainboards, are respectively electrically connected with the two control modules, and both store a firmware program code.
The two control modules respectively initialize to read the firmware program codes from the two nonvolatile memories respectively so as to execute a corresponding firmware, so that the two control modules respectively operate in a master control mode and a controlled mode.
When the control module operating in the master control mode is abnormal, the control module operating in the controlled mode is converted into the master control mode, the control module originally operating in the master control mode is controlled to be converted into a reduction mode, and the firmware program code stored in the volatile memory corresponding to the control module operating in the master control mode is transmitted to the control module operating in the reduction mode so as to update the nonvolatile memory corresponding to the control module operating in the reduction mode.
Preferably, each of the control modules is enabled to determine whether the other one of the control modules is abnormal or not by a health signal.
Preferably, each of the control modules includes a first bus for outputting the health signal and receiving the health signal output by the other. When any one of the control modules operates normally, the logic value of the health signal correspondingly output will jump between logic 1 and logic 0. When any one of the control modules operates abnormally, the logic value of the health signal correspondingly output is kept at logic 0 or logic 1.
Preferably, each of the control modules outputs the health signal via a first bus and includes a register. When one of the control modules operates normally, the corresponding health signal is used to change the value of the register of the other control module along with time. When one of the control modules is abnormal, the corresponding health signal can not be used to change the value of the register of the other control module along with time.
Preferably, each of the control modules includes a second bus for outputting a restore signal and for receiving another restore signal output by the other. Each control module determines whether to operate in the recovery mode according to the received recovery signal.
Preferably, each of the control modules includes a third bus for transmitting the firmware program code and for receiving the firmware program code transmitted by the other.
Preferably, the control modules are respectively defined as a first control module and a second control module, the first control module defaults to operate in the master control mode, and the second control module defaults to operate in the controlled mode. When the first control module is abnormal and is changed to operate in the reduction mode, and receives the firmware program code from the second control module to update the corresponding non-volatile memory, so that the firmware is re-executed and operates normally, the first control module is changed to operate in the main control mode and the second control module is changed to operate in the controlled mode.
In order to solve the above technical problem, the present invention further provides a storage device, which includes a power unit, a fan unit, at least one hard disk, and a control system. The power supply unit is used for providing operating power. The fan unit is used for providing heat dissipation. The at least one hard disk is used for storing data. The control system comprises two mainboards, two control modules and two non-volatile memories.
The two control modules are respectively arranged on the two mainboards, are electrically connected with each other and are electrically connected with the power supply unit, the fan unit and the at least one hard disk respectively, so as to be used for monitoring and managing the power supply unit, the fan unit and the at least one hard disk. The two non-volatile memories are respectively arranged on the two mainboards, are respectively electrically connected with the two control modules, and both store a firmware program code.
The two control modules respectively initialize to read the firmware program codes from the two nonvolatile memories respectively so as to execute a corresponding firmware, so that the two control modules respectively operate in a master control mode and a controlled mode.
When the control module operating in the master control mode is abnormal, the control module operating in the controlled mode is converted into the master control mode, the control module originally operating in the master control mode is controlled to be converted into a reduction mode, and the firmware program code stored in the volatile memory corresponding to the master control mode is transmitted to the control module operating in the reduction mode, so that the nonvolatile memory corresponding to the reduction mode is updated.
Preferably, each of the control modules is enabled to determine whether the other one of the control modules is abnormal or not by a health signal.
Preferably, each of the control modules includes a first bus for outputting a restore signal and for receiving another restore signal output by the other. Each control module determines whether to operate in the recovery mode according to the received recovery signal.
Compared with the prior art, when the control module operating in the master control mode is abnormal in the starting process, the control module operating in the controlled mode is converted into the master control mode, the control module operating in the abnormal mode is converted into the recovery mode, and the firmware program code stored in the corresponding volatile memory is transmitted to the control module operating in the abnormal mode to update the corresponding non-volatile memory, so that the abnormal condition of the firmware program code stored in the non-volatile memory can be repaired.
[ brief description of the drawings ]
Other features and effects of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram illustrating an embodiment of a storage device according to the present invention.
[ detailed description ] embodiments
Before the present invention is described in detail, it should be noted that in the following description, similar components are denoted by the same reference numerals.
Referring to fig. 1, an embodiment of the storage apparatus of the present invention includes a backplane 6, a power unit 7, a fan unit 8, a storage unit 9, and a control system 1. The storage device is, for example, a JBOD (just A Bunch Of disks); the power supply unit 7 is, for example, a power supply for supplying power required by the operation of the storage device; the fan unit 8 includes a plurality of fans, for example, to provide heat dissipation capability to the storage device; the storage unit 9 includes, for example, at least one hard disk for storing data; but are not limited thereto.
The control system 1 includes a first motherboard 21, a second motherboard 22, a first non-volatile memory 31, a second non-volatile memory 32, a first control module 41, and a second control module 42. The first main board 21 and the second main board 22 are, for example, inserted on the back board 6. The first nonvolatile memory 31 and the second nonvolatile memory 32 are respectively disposed on the first motherboard 21 and the second motherboard 22, are respectively electrically connected to the first control module 41 and the second control module 42, and both store a firmware program code.
The first control module (IOM) 41 and the second control module 42 are, for example, integrated circuit chips, and are respectively disposed on the first motherboard 21 and the second motherboard 22, and are electrically connected to each other and electrically connected to the power unit 7, the fan unit 8, and the storage unit 9, so as to monitor and manage the power unit 7, the fan unit 8, and the storage unit 9. For example, the system is used for monitoring and managing the related power supply state of the power supply, the rotation speed and the corresponding ambient temperature of the fans, and the related operation state of each hard disk.
The first control module 41 and the second control module 42 are electrically connected via the backplane 6 via a first bus 411, a second bus 412, and a third bus 413. For simplicity, fig. 1 does not show actual electrical connection, and the first bus 411, the second bus 412, and the third bus 413 can be electrically connected to the first control module 41 and the second control module 42 directly or indirectly via the backplane 6.
When the storage device is powered on, that is, after the control system 1 is powered on, the first control module 41 and the second control module 42 respectively initialize to read the Firmware program code from the first nonvolatile memory 31 and the second nonvolatile memory 32 respectively to execute a Firmware (Firmware), so that the first control module 41 and the second control module 42 respectively operate in a master control (Active) mode and a slave control (Passive) mode. For example, the first control module 41 operates in the master mode, and the second control module 42 operates in the controlled mode.
The first control module 41 (or the second control module 42) outputs a health signal to the second control module 42 via the first bus 411, and when the first control module 41 (or the second control module 42) operates normally, the logic value of the health signal output correspondingly will jump between logic 1 and logic 0, and when the first control module 41 (or the second control module 42) operates abnormally, the logic value of the health signal output correspondingly will remain at logic 0 or logic 1. Therefore, the second control module 42 (or the first control module 41) can determine whether the first control module 41 (or the second control module 42) is abnormal or not by the received health signal.
In the embodiment, the first bus 411 is, for example, a bus formed by connection lines between two General-purpose input/output (GPIO) pins of the first control module 41 and the second control module 42, and is used for transmitting and receiving the health signal, and the first bus 411 may also be an Inter-Integrated Circuit (I2C) bus between the first control module 41 and the second control module 42 for transmitting and receiving the health signal. In other embodiments, the first control module 41 and the second control module 42 each further include a register. When the first control module 41 (or the second control module 42) operates normally, the register value of the second control module 42 (or the first control module 41) is changed over time by using the corresponding health signal. When the first control module 41 (or the second control module 42) is abnormal, the value of the register of the second control module 42 (or the first control module 41) cannot be changed over time by using the corresponding health signal, so that the second control module 42 (or the first control module 41) can determine whether the first control module 41 (or the second control module 42) is abnormal or not by changing the value of the corresponding register.
When the first control module 41 operating in the master mode is abnormal during the operation process, the second control module 42 operating in the controlled mode is switched to operate in the master mode according to the determination, and controls the first control module 41 originally operating in the master mode to switch to operate in a recovery mode. In more detail, the first control module 41 (or the second control module 42) outputs the restore signal to the second control module 42 (or the first control module 41) via the second bus 412. The first control module 41 (or the second control module 42) determines whether to operate in the restore mode according to the received restore signal, for example, according to a logic value of the restore signal. In the present embodiment, the second bus 412 is, for example, a connection line between two general purpose input/output pins of the first control module 41 and the second control module 42 or another integrated circuit (I2C) bus between the first control module 41 and the second control module 42, but not limited thereto.
Then, the second control module 42 operating in the master mode transmits the firmware program code stored in the corresponding volatile memory 32 to the first control module 41 operating in the restore mode, so that the first control module 41 updates (i.e., re-stores) the received firmware program code in the corresponding non-volatile memory 31 in the restore mode, and reloads the updated firmware program code to execute the firmware again, so as to convert the firmware program code into the controlled mode, thereby enabling normal operation.
In this embodiment, the first control module 41 (or the second control module 42) transmits or receives the firmware program code via the third bus 413. In the embodiment, the third bus 413 is another integrated circuit (I2C) bus or an Intelligent Platform Management Interface (IPMI) bus, but not limited thereto. In addition, in other embodiments, the first control module 41 can be default to operate in the master mode, and the second control module 42 can be default to operate in the controlled mode. When the first control module 41 is abnormal and is changed to operate in the restore mode, and receives the firmware program code from the second control module 42 to update the corresponding non-volatile memory, and further re-executes the firmware and operates normally, the first control module 41 is changed to operate in the master mode, and the second control module 42, which is changed to operate in the master mode in response to the abnormality of the first control module 41, is changed to operate in the default controlled mode.
Particular emphasis is given to: when the first control module 41 or the second control module 42 is abnormal, the first control module 41 or the second control module 42 which operates normally transmits the firmware program code corresponding to the firmware which is executed by itself. In addition, both the two mainboards (i.e. the first mainboard 21 and the second mainboard 22) only need to be respectively provided with a single non-volatile memory (i.e. the first non-volatile memory 31 and the second non-volatile memory 32) for storing the firmware program code corresponding to the firmware being executed, and only need to store one firmware program code in the single non-volatile memory, which not only can provide the execution of the control modules (i.e. the first control module 41 and the second control module 42) on the two mainboards, but also can achieve the function of mutually repairing the firmware.
Further, it is to be noted that: the first control module 41 operating in the master mode and the second control module 42 operating in the controlled mode both monitor the power unit 7, the fan unit 8, and the storage unit 9 and respectively record and store monitoring information obtained by monitoring, so as to switch the master mode/the controlled mode in real time and provide a backup function in real time when one of the two is abnormal. But only the first control module 41 operating in the master mode manages (i.e., controls) the power supply unit 7, the fan unit 8, and the storage unit 9 according to the monitoring information obtained by monitoring.
Furthermore, particular emphasis is given to: the first control module 41 operating in the master mode also monitors the health signal of the second control module 42. For example, when the first control module 41 detects that the second control module 42 is abnormally operated, the restoring signal is also transmitted to the second control module 42, and then the firmware program code corresponding to the firmware being executed by the first control module 41 is transmitted to the second control module 42. After receiving the firmware program code transmitted by the first control module 41, the second control module 42 updates the firmware program code in the second non-volatile memory 32 corresponding to the second control module with the received firmware program code, and executes the updated firmware again after the firmware update is completed, so as to switch from the recovery mode to the controlled mode according to an identification code of the second motherboard 22, wherein since the first control module 41 is already operating in the master control mode, when the first control module 41 monitors that the second control module 42 is abnormal in operation, the first control module 41 does not switch to operating in the controlled mode, but continues to operate in the master control mode.
In summary, when the first control module 41 (or the second control module 42) operating in the master mode is abnormal during the operation process, the second control module 42 (or the first control module 41) operating in the controlled mode is switched to operate in the master mode, and the first control module 41 (or the second control module 42) having the abnormal operation is controlled to be switched to operate in the recovery mode, and the firmware program code stored in the corresponding volatile memory is transmitted to the first control module 41 (or the second control module 42) having the abnormal operation, so that the first control module 41 (or the second control module 42) having the abnormal operation automatically updates and stores the received firmware program code in the corresponding first nonvolatile memory 31 (or the second nonvolatile memory 32) in the recovery mode, therefore, the first control module 41 (or the second control module 42) with the exception is in the recovery mode, and automatically restarts itself after the received firmware program code is stored, and loads and executes the firmware corresponding to the stored firmware program code, so as to convert the firmware program code into the original default mode, thereby repairing the exception condition of the firmware program code stored in the first nonvolatile memory 31 (or the second nonvolatile memory 32), and thus the purpose of the present invention can be achieved.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A control system of a storage device is suitable for a power supply unit, a fan unit and at least one hard disk, and is characterized by comprising:
two main boards;
the two control modules are respectively arranged on the two mainboards, are electrically connected with each other and are electrically connected with the power supply unit, the fan unit and the at least one hard disk respectively, so as to be used for monitoring and managing the power supply unit, the fan unit and the at least one hard disk; and
two non-volatile memories respectively disposed on the two mainboards and electrically connected to the two control modules respectively, and storing a firmware program code,
wherein the two control modules respectively initialize to read the firmware program codes from the two non-volatile memories respectively to execute a corresponding firmware, so that the two control modules respectively operate in a master control mode and a controlled mode,
when the control module operating in the master control mode is abnormal, the control module operating in the controlled mode is converted into the master control mode, the control module originally operating in the master control mode is controlled to be converted into a reduction mode, and the firmware program code stored in the volatile memory of the control module corresponding to the master control mode is transmitted to the control module operating in the reduction mode, so that the non-volatile memory stored in the control module corresponding to the reduction mode is updated.
2. The system as claimed in claim 1, wherein each of the control modules determines whether the other one of the control modules is abnormal by a health signal.
3. The system as claimed in claim 2, wherein each of the control modules includes a first bus for outputting the health signal and receiving the health signal output from the other control module, and when any one of the control modules operates normally, the logic value of the health signal output correspondingly is toggled between logic 1 and logic 0, and when any one of the control modules operates abnormally, the logic value of the health signal output correspondingly is maintained at logic 0 or logic 1.
4. The system as claimed in claim 2, wherein each of the control modules outputs the health signal via a first bus and includes a register, and when one of the control modules operates normally, the value of the register of the other control module is changed over time by using the corresponding health signal, and when one of the control modules operates abnormally, the value of the register of the other control module is not changed over time by using the corresponding health signal.
5. The system as claimed in claim 1, wherein each of the control modules comprises a second bus for outputting a restore signal and receiving another restore signal from the other module, and each of the control modules determines whether to operate in the restore mode according to the received restore signal.
6. The system of claim 1, wherein each control module comprises a third bus for transmitting the firmware code and for receiving the firmware code transmitted by the other.
7. The system of claim 1, wherein the control modules are respectively defined as a first control module and a second control module, the first control module defaults to operate in the master mode, the second control module defaults to operate in the controlled mode, and when the first control module is abnormal and changes to operate in the restore mode, and receives the firmware program code from the second control module to update the corresponding non-volatile memory, and then re-executes the firmware and operates normally, the first control module changes to operate in the master mode and the second control module changes to operate in the controlled mode.
8. A storage device, comprising:
a power supply unit for providing operating power;
a fan unit for providing heat dissipation;
at least one hard disk for storing data; and
a control system, comprising:
two main boards;
the two control modules are respectively arranged on the two mainboards, are electrically connected with each other and are electrically connected with the power supply unit, the fan unit and the at least one hard disk respectively, so as to be used for monitoring and managing the power supply unit, the fan unit and the at least one hard disk; and
two non-volatile memories respectively disposed on the two mainboards and electrically connected to the two control modules respectively, and storing a firmware program code,
wherein the two control modules respectively initialize to read the firmware program codes from the two non-volatile memories respectively to execute a corresponding firmware, so that the two control modules respectively operate in a master control mode and a controlled mode,
when the control module operating in the master control mode is abnormal, the control module operating in the controlled mode is converted into the master control mode, the control module originally operating in the master control mode is controlled to be converted into a reduction mode, and the firmware program code stored in the volatile memory corresponding to the master control mode is transmitted to the control module operating in the reduction mode, so that the nonvolatile memory corresponding to the reduction mode is updated.
9. The storage device as claimed in claim 8, wherein each of the control modules is enabled by a health signal to enable another one of the control modules to determine whether the one of the control modules is abnormal.
10. The storage device according to claim 8, wherein each of the control modules includes a first bus for outputting a restore signal and for receiving another restore signal output by the other, and each of the control modules determines whether to operate in the restore mode according to the received restore signal.
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| CN202010992639.8A CN114253763A (en) | 2020-09-21 | 2020-09-21 | Storage device and control system thereof |
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| CN202010992639.8A CN114253763A (en) | 2020-09-21 | 2020-09-21 | Storage device and control system thereof |
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