CN114245040B - Reading circuit and infrared imager - Google Patents
Reading circuit and infrared imager Download PDFInfo
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- CN114245040B CN114245040B CN202111371955.4A CN202111371955A CN114245040B CN 114245040 B CN114245040 B CN 114245040B CN 202111371955 A CN202111371955 A CN 202111371955A CN 114245040 B CN114245040 B CN 114245040B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Abstract
The invention provides a reading circuit and an infrared imager, and relates to the field of infrared imaging. The circuit comprises: a pixel-level circuit and a column-level circuit; the pixel-level circuit receives the output current from the current detector to perform continuous integration to obtain an integration voltage, generates a turnover counting signal in the continuous integration process, and transmits the integration voltage and the turnover counting signal to the column-level circuit; the column level circuit processes the integral voltage and the turnover counting signal to obtain a quantization result, and the quantization result is synchronously read row by row and column by rolling reading. The reading circuit provided by the invention has the advantages that the integration process is not interrupted, the external reset is not required in the working state, the data is completely not missed, and the precision of the quantization result is greatly improved. The quantization results of the adjacent frames have relevance in a time domain, so that the time domain relevance can be subsequently utilized for carrying out related sampling, time domain related algorithm optimization is carried out, and the signal-to-noise ratio and the dynamic range of the whole equipment are excellently improved.
Description
Technical Field
The invention relates to the field of infrared imaging, in particular to a reading circuit and an infrared imager.
Background
Infrared imaging is a technique for recognizing an object by detecting infrared radiation emitted from the object, and is widely used in the fields of military, space technology, medicine, and the like. The infrared focal plane array component is a main body of an infrared imaging system and consists of an infrared detector and an infrared focal plane reading circuit. The reading circuit converts the electric signal generated by the infrared detector and outputs the electric signal to an off-chip signal processing system. For infrared focal plane arrays, especially long-wave infrared, the charge handling capability can be significantly improved by using a pixel-level analog-to-digital converter (ADC).
At present, an area array type focal plane array is integrated according to frames, each frame is integrated firstly and then sampled, and data of each frame are independent, so that signals outside the integration time in the same frame cannot be acquired, and linearity and even data are easily lost when the signal difference in each frame is large.
In addition, due to the non-uniformity caused by the reset integration capacitance, it is difficult to optimize the image data by the data of the close time, and the finally output noise is influenced more. And because there is no correlation in the time domain between each frame of data outputted, it is difficult to perform algorithm optimization of time domain correlation by DSP (Digital Signal processing).
Disclosure of Invention
In view of the above, the present invention has been developed to provide a readout circuit and an infrared imager that overcome or at least partially solve the above problems.
A first aspect of an embodiment of the present invention provides a readout circuit, including: a pixel-level circuit and a column-level circuit;
the pixel-level circuit receives the output current from the current detector, performs continuous integration to obtain an integration voltage, generates an overturning counting signal in the continuous integration process, and transmits the integration voltage and the overturning counting signal to the column-level circuit;
the column-level circuit processes the integral voltage and the turnover counting signal to obtain a quantization result, and the quantization result is synchronously read row by row and column by rolling reading;
the continuous integration is an integration process that the integration voltage is integrated until reaching the reset voltage and the reset operation is not carried out along with the frame time;
the turnover counting signal is a signal corresponding to the number of turnover reset operations after the integral voltage reaches the reference voltage;
when the column-level circuit adopts rolling readout, each row of pixels keeps continuous integration, and sampling is not stopped.
Optionally, the pixel stage circuit comprises: the system comprises an input integration unit, a threshold judgment unit, a source following unit and a turnover counting unit;
the input integration unit receives the output current, performs the continuous integration, and outputs the integration voltage to the threshold judgment unit and the source following unit;
the threshold judging unit generates a pulse signal according to the integral voltage and the reference voltage and outputs the pulse signal to the turnover counting unit, wherein the pulse signal is generated during the turnover reset operation;
the turnover counting unit counts the pulse signals to obtain turnover counting signals, and transmits the turnover counting signals to the column circuit;
the source follower unit transmits the integrated voltage to the column stage circuit every row clock cycle.
Optionally, the turnover counting unit counts the pulse signals in a line-by-line counting manner to obtain turnover counting signals, and transmits the turnover counting signals to the column circuit;
or the turnover counting unit counts the pulse signals in a single counting mode to obtain the turnover counting signals, and transmits the turnover counting signals to the column circuit.
Optionally, the input integration unit comprises: the first NMOS tube, the integrating capacitor and the first PMOS tube;
the source electrode of the first NMOS tube receives the output current;
the grid electrode of the first NMOS tube receives an integral signal;
the drain electrode of the first NMOS tube is respectively connected with the first end of the integrating capacitor, the drain electrode of the first PMOS tube, the threshold value judging unit and the source following unit;
the grid electrode of the first PMOS tube receives a reset signal;
the source electrode of the first PMOS tube receives reset voltage and is connected with the threshold value judging unit;
and the second end of the integrating capacitor is grounded.
Optionally, the threshold judging unit includes: the comparator and the second PMOS tube;
the inverting end of the comparator is connected with the drain electrode of the first NMOS tube and the source following unit respectively;
the same-direction end of the comparator receives the reference voltage;
the output end of the comparator is respectively connected with the grid electrode of the second PMOS tube and the turnover counting unit;
the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube;
and the comparator determines the input type of the comparator according to the working type of the current detector.
Optionally, the source follower unit comprises: a second NMOS transistor and a third NMOS transistor;
the grid electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube;
the drain electrode of the second NMOS tube receives working voltage;
the source electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube;
the grid electrode of the third NMOS tube receives a row selection signal;
and the drain electrode of the third NMOS tube is connected with the column-level circuit.
Optionally, the first PMOS transistor is turned on once when the readout circuit is started, and resets the integrating capacitor;
and the first PMOS tube is not conducted in the process of continuous integration of the pixel level circuit.
Optionally, in the process of counting the pulse signals by the turnover counting unit, the turnover counting signal of the corresponding row is obtained based on a current counting result and a previous counting result.
Optionally, the frame rate of the quantization result read out by the column-level circuit each time synchronously is determined by an external clock, and is not controlled by the integration time, and the quantization results of adjacent frames have correlation in the time domain.
A second aspect of an embodiment of the present invention provides an infrared imager, including: a photo-current detector and a readout circuit as claimed in any one of the first aspects.
According to the readout circuit provided by the invention, the pixel-level circuit receives the output current from the current detector, performs continuous integration to obtain an integration voltage, generates a turnover counting signal in the continuous integration process, and transmits the integration voltage and the turnover counting signal to the column-level circuit; the column level circuit processes the integral voltage and the turnover counting signal to obtain a quantization result, and the quantization result is synchronously read row by row and column by rolling reading.
The reading circuit of the invention abandons the traditional mode of integrating according to frames, but integrates continuously, the integration process is not interrupted, and the reading circuit does not need to rely on external reset in a working state, thereby ensuring that data is not missed completely. When the column-level circuit adopts rolling reading, each row of pixels keeps continuous integration, and simultaneously sampling is not stopped, because the frame frequency of each reading quantization result is determined by an external clock instead of the integration time, the quantization results of adjacent frames have relevance in a time domain, so that the time domain relevance can be subsequently utilized for carrying out relevant sampling, time domain correlation algorithm optimization is carried out, and the signal-to-noise ratio and the dynamic range of the whole equipment are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive labor.
FIG. 1 is a signal flow diagram of a sensing circuit in an embodiment of the present invention;
fig. 2 is a schematic diagram schematically illustrating a structure of a pixel-level circuit in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The inventor finds that the traditional focal plane array is integrated according to frames, each frame is integrated firstly and then sampled, and data of each frame are independent, so that signals outside the same intra-frame integration time cannot be acquired, and linearity and even data are easily lost when the signal difference in each frame is large. In addition, there is non-uniformity introduced by the reset integration capacitance, which means that it is difficult to optimize the image data by the data of the close time, and the noise of the final output is more affected. And because each frame of data outputted has no time-domain correlation, the algorithm optimization of time-domain correlation by the DSP is difficult.
The existing solution mainly adopts an IWR mode to reduce the distance between the integration time of frames, increase the integration time as much as possible to occupy the whole frame time, and reduce the data loss in transmission. But even if very little time is reserved between IWR integrations for reset and sampling, there is still considerable signal data lost in this process, and the final effective integration time is still much less because of the boundary effect of the integration capacitance. Furthermore, the information collected within a pixel is still data within the frame, and the information data of the frame cannot be optimized from other data in the time domain.
In view of the above problems, the inventors have creatively proposed a readout circuit of the present invention, and have better solved the above problems, and a readout circuit of the present invention will be described below.
The readout circuit of the embodiment of the invention comprises: a pixel-level circuit and a column-level circuit; the pixel-level circuit receives the output current from the current detector, performs continuous integration to obtain an integration voltage, generates a turnover counting signal in the continuous integration process, and transmits the integration voltage and the turnover counting signal to the column-level circuit. In the continuous integration process of the pixel-level circuit, whether the integration voltage reaches the threshold value or not needs to be continuously judged, integration is kept when the integration voltage does not reach the threshold value, and the integration capacitor is reset when the integration voltage reaches the threshold value. Each reset of the integrating capacitor is equivalent to generating an overturning signal, and the number of times of the overturning signal is used as an overturning counting signal and is transmitted to the column-level circuit together with the integrating voltage in the continuous integrating process.
The column-level circuit processes the integrated voltage and the turnover counting signal to obtain a quantization result, and the quantization result is synchronously read row by row and column by rolling reading. This process can be intuitively explained with reference to the signal flow diagram shown in fig. 1.
When a certain row in the focal plane array starts to be quantized, the output current of the current detector is input into the pixel level circuit, the pixel level circuit carries out continuous integration, whether the integration voltage reaches a threshold value or not is continuously judged in the continuous integration process, and meanwhile, the integration voltage in the continuous integration process of the row is transmitted to the column level circuit in a whole row reading mode.
And if the integral voltage does not reach the threshold value, returning to the continuous integral process, if the integral voltage reaches the threshold value, carrying out integral reset, and simultaneously counting the reset times. When the row is continuously integrated, the reset counting result is transmitted to the column level circuit, after the column level circuit receives the reset counting result, the reset times are read out, the row is sequentially read out by combining the integrated voltage, and finally the synchronous reading is carried out.
After the row continuous integration is finished, the quantization result of the row is read out, and then the next row is quantized continuously according to the method until the whole focal plane array is quantized and read out.
Continuous integration is an integration process that the integration voltage is integrated until reaching the reset voltage and the reset operation is not carried out along with the frame time; the integration process is not interrupted, external reset is not needed in the working state, data are guaranteed not to be omitted completely, and the precision of a quantization result is greatly improved.
While the column level circuit employs rolling readout, each row of pixels maintains continuous integration without stopping sampling. Because the frame frequency of the quantization result read out every time is determined by the external clock instead of the integration time, the quantization results of adjacent frames have correlation in the time domain, so that the time domain correlation can be used for performing correlation sampling subsequently, time domain correlation algorithm optimization is performed, and the signal-to-noise ratio and the dynamic range of the whole equipment are improved excellently.
In the embodiment of the present invention, a preferable structure of the pixel level circuit may include: the system comprises an input integration unit, a threshold judgment unit, a source following unit and a turnover counting unit; the input integration unit receives the output current, performs continuous integration, and outputs integration voltage to the threshold judgment unit and the source following unit; the threshold value judging unit generates a pulse signal when the integral voltage reaches the reference voltage according to the integral voltage and the reference voltage and outputs the pulse signal to the turnover counting unit, wherein the pulse signal is generated when the turnover resetting operation is carried out; the turnover counting unit counts the pulse signals to obtain turnover counting signals, and the turnover counting signals are transmitted to the column circuit; the source follower unit transmits the integrated voltage to the column stage circuit every row clock cycle.
The turnover counting unit can count the pulse signals in a line-by-line counting mode to obtain turnover counting signals, and the turnover counting signals are transmitted to the column-level circuit. The line-by-line counting mode is as follows: in the continuous integration process of a certain row, the turnover counting unit only counts the turnover counting time once, namely counts the turnover counting time when the row finishes integration, outputs a counter, and then transmits the counter to a column level through the row and column selection in one-to-one correspondence.
Or the turnover counting unit counts the pulse signals in a single counting mode to obtain turnover counting signals, and transmits the turnover counting signals to the column circuit. The single counting mode is as follows: in the continuous integration process of a certain row, the turnover counting unit counts each turnover, namely, a counter is output after each turnover, the counter is transmitted to the column level through the row selection and the column selection in one-to-one correspondence, the column level receives a plurality of counters, the operation is more accurate, the workload of the turnover counting unit and the workload of the column level are increased to a certain extent, and the power consumption is slightly improved.
In addition, the turnover counting unit does not need to be reset and can continuously count. That is, no matter which counting method is adopted by the turnover counting unit, the turnover counting signal of the corresponding row can be obtained based on the current counting result and the previous counting result in the process of counting the pulse signal by the turnover counting unit. For example: in the process of continuous integration of the previous first line, the counting result of the turnover counting unit is 1000, while in the process of continuous integration of the current first line, the counting result of the turnover counting unit is directly accumulated from 1000 upwards, and if the counting result of the turnover counting unit is 1020, in the process of continuous integration of the current first line, the counting result of the turnover counting unit is as follows: 1020-1000=20. If the upper counting limit of the turnover counting unit is 1024 times, the counting of the turnover counting unit is cleared after the upper counting limit is reached, and counting is started from 0. For example, in the next continuous integration process performed on the first row, the turnover counting unit starts to accumulate from 1020, and the final counting result is: 9, then it represents that during this time of the continuous integration of the first row, the counting result of the turnover counting unit is: 1024-1020+9=15. The rest can be analogized.
To more clearly illustrate the readout circuit of the present invention, referring to fig. 2, a schematic diagram of a pixel-level circuit is schematically shown. Fig. 2 includes: the current detector Diode, the first NMOS tube M1, the first PMOS tube M2, the second PMOS tube M3, the second NMOS tube M4, the third NMOS tube M5, the integrating capacitor Cp, the comparator CMP and the Counter. The first NMOS tube M1, the integrating capacitor Cp and the first PMOS tube M2 form an input integrating unit; the second PMOS tube M3 and the comparator CMP form a threshold value judging unit; the second NMOS tube M4 and the third NMOS tube M5 form a source following unit; the Counter constitutes an inverting counting unit. The specific structure may be replaced by other circuits or components with the same function, and the embodiment of the present invention is only shown by way of example, and does not represent only such a structure.
The source electrode of the first NMOS tube M1 receives the output current of the current detector Diode; the grid electrode of the first NMOS tube M1 receives an integration signal GPOL; the drain electrode of the first NMOS transistor M1 is connected to the first end of the integrating capacitor Cp, the drain electrode of the first PMOS transistor M2, the drain electrode of the second PMOS transistor M3, the inverting terminal of the comparator, and the gate electrode of the second NMOS transistor M4, respectively.
The grid electrode of the first PMOS pipe M2 receives a reset signal RST; the source electrode of the first PMOS pipe M2 receives the reset voltage VR and is connected with the source electrode of the second PMOS pipe M3; the second terminal of the integrating capacitor Cp is grounded.
The inverting terminal of the comparator CMP is connected to the aforementioned terminal, and the inverting terminal of the comparator CMP receives the reference voltage Vref; the output terminal of the comparator CMP is connected to the gate of the second PMOS transistor M3 and the Counter, respectively. The output Countout to which the Counter is respectively connected may be output to the column stage or the buffer stage.
The gate connection of the second NMOS transistor M4 is as described above; the drain electrode of the second NMOS tube M4 receives the working voltage VDD; the source electrode of the second NMOS tube M4 is connected with the source electrode of the third NMOS tube M5; the grid electrode of the third NMOS tube M5 receives a row selection signal RS; the drain electrode of the third NMOS transistor M5 is connected to the column stage circuit Colin.
When the pixel level circuit starts to work, the first PMOS tube M2 is conducted once only when the whole reading circuit is started, and the integrating capacitor Cp is reset; the first PMOS transistor M2 is not turned on during the continuous integration of the pixel-level circuit. When the pixel-level circuit integrates continuously, the source follower unit transmits the integrated voltage to the column-level circuit Colin in each row clock period. Each time the integrated voltage reaches the reference voltage, the output terminal of the comparator CMP is inverted once, and the inversion is recorded by the Counter through several stages of buffering until the inversion is output to the column stage circuit Colin. Meanwhile, each time the comparator CMP is turned over, a pulse signal is generated and output to the gate of the second PMOS transistor M3, which is used for resetting the integration capacitor Cp. The comparator CMP is operated again, and the operation is repeated cyclically.
It should be noted that the comparator CMP determines its own input type according to the operation type of the current detector matched by the readout circuit, that is, the operation type of the current detector for extraction or injection. Typically, the comparator CMP will also be a p-type or n-type input, respectively. During operation of the comparator CMP, the input voltage will continuously rise with current injection or continuously fall with current extraction.
In summary, the column-level readout scheme is different from the conventional readout scheme, and the main differences are:
1. the signal transmitted to the column stage encompasses the reset count signal in addition to the analog signal (i.e., integrated voltage) of the conventional readout mode.
2. Each row in the array is continuously sampled, namely the pixels have no frame concept, the whole array does not perform snapshot frame-by-frame sampling and then reads out data, the method of rolling readout and no need of stopping sampling is adopted, the pixels of each row are kept integrated, the integration is not stopped even in the sampling process, and only the column stage is connected to the source following units of n rows through the RS < n > switch to read out the data at the current moment. And connects the column stage to the source follower of row n +1 during the next row clock, cycling until all data is scanned out, and finally reading out synchronously row by row and column. Therefore, the frame rate of the quantization result read out synchronously by the column-level circuit each time is determined by the external clock, and is not controlled by the integration time, and the quantization results of adjacent frames have correlation in the time domain.
Based on the column circuit, an embodiment of the present invention further provides an infrared imager, where the infrared imager includes: a current detector and a readout circuit as described in any of the above.
Through the example, the read-out circuit of the invention abandons the traditional mode of integrating according to frames, but continuously integrates, does not follow the integration process of the frame time for resetting operation, is not interrupted in the integration process, does not need to rely on external resetting in the working state, ensures that data is not missed completely, and greatly improves the precision of the quantization result. When the column-level circuit adopts rolling reading, each row of pixels keeps continuous integration, and sampling is not stopped at the same time, because the frame frequency of each time of reading the quantization result is determined by an external clock instead of the integration time, the quantization results of adjacent frames have relevance in a time domain, so that the time domain relevance can be used for performing related sampling in the subsequent process, time domain correlation algorithm optimization is performed, and the signal-to-noise ratio and the dynamic range of the whole equipment are improved excellently.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the particular illustrative embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications, equivalent arrangements, and equivalents thereof, which may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A sensing circuit, the sensing circuit comprising: a pixel-level circuit and a column-level circuit;
the pixel-level circuit receives output current from the current detector, performs continuous integration to obtain integral voltage, continuously judges whether the integral voltage reaches a threshold value in the continuous integration process, keeps integration when the integral voltage does not reach the threshold value, resets the integral capacitor when the integral voltage reaches the threshold value, generates an overturning signal for resetting the integral capacitor each time, transmits the overturning counting signal to the column-level circuit by taking the number of times of the overturning signal as an overturning counting signal, and simultaneously transmits the integral voltage in the continuous integration process of a row to the column-level circuit in a whole row reading mode;
the column-level circuit processes the integral voltage and the turnover counting signal to obtain a quantization result, and the quantization result is synchronously read row by row and column by rolling reading;
the continuous integration is an integration process that the integration voltage is integrated until reaching the reset voltage and the reset operation is not carried out along with the frame time;
the turnover counting signal is a signal corresponding to the number of turnover reset operations after the integral voltage reaches the reference voltage;
when the column-level circuit adopts rolling readout, each row of pixels keeps continuous integration, and sampling is not stopped.
2. A readout circuit according to claim 1, wherein the pixel stage circuit comprises: the system comprises an input integration unit, a threshold judgment unit, a source following unit and a turnover counting unit;
the input integration unit receives the output current, performs continuous integration, and outputs the integration voltage to the threshold judgment unit and the source following unit;
the threshold judging unit generates a pulse signal when the integral voltage reaches the reference voltage according to the integral voltage and the reference voltage, and outputs the pulse signal to the turnover counting unit, wherein the pulse signal is generated when the turnover resetting operation is performed;
the turnover counting unit counts the pulse signals to obtain turnover counting signals, and the turnover counting signals are transmitted to the column-level circuit;
the source follower unit transmits the integrated voltage to the column stage circuit every row clock cycle.
3. The readout circuit of claim 2, wherein the flip-flop counting unit counts the pulse signals in a row-by-row counting manner to obtain the flip-flop counting signal, and transmits the flip-flop counting signal to the column circuit; the line-by-line counting mode is as follows: when the continuous integration of a certain row is finished, the turnover counting unit counts the total occurrence frequency of the turnover signals, outputs a counter, and then transmits the counter to a row level through row selection and column selection in one-to-one correspondence;
or the turnover counting unit counts the pulse signals in a single counting mode to obtain the turnover counting signals, and transmits the turnover counting signals to the column circuit; the single counting mode is as follows: in the process of continuous integration of a certain row, the turnover counting unit counts turnover signals generated each time, outputs a counter each time, and then transmits the counter to the column level through row selection and column selection in one-to-one correspondence, wherein the column level receives a plurality of counters.
4. The readout circuit of claim 2, wherein the input integration unit comprises: the first NMOS tube, the integrating capacitor and the first PMOS tube;
the source electrode of the first NMOS tube receives the output current;
the grid electrode of the first NMOS tube receives an integral signal;
the drain electrode of the first NMOS tube is respectively connected with the first end of the integrating capacitor, the drain electrode of the first PMOS tube, the threshold value judging unit and the source following unit;
the grid electrode of the first PMOS tube receives a reset signal;
the source electrode of the first PMOS tube receives reset voltage and is connected with the threshold value judging unit;
and the second end of the integrating capacitor is grounded.
5. The readout circuit according to claim 4, wherein the threshold judging unit includes: a comparator and a second PMOS tube;
the inverting end of the comparator is respectively connected with the drain electrode of the first NMOS tube and the source following unit;
the same-direction end of the comparator receives the reference voltage;
the output end of the comparator is connected with the grid electrode of the second PMOS tube and the turnover counting unit respectively;
the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube;
and the comparator determines the input type of the comparator according to the working type of the current detector.
6. The readout circuit of claim 4, wherein the source follower unit comprises: a second NMOS transistor and a third NMOS transistor;
the grid electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube;
the drain electrode of the second NMOS tube receives working voltage;
the source electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube;
the grid electrode of the third NMOS tube receives a row selection signal;
and the drain electrode of the third NMOS tube is connected with the column-level circuit.
7. The readout circuit of claim 4, wherein the first PMOS transistor is turned on once at start-up of the readout circuit to reset the integrating capacitor;
and the first PMOS tube is not conducted in the process of continuous integration of the pixel level circuit.
8. The readout circuit of claim 5, wherein the frame rate at which the quantization results are read out synchronously by the column-level circuit each time is determined by an external clock without being controlled by an integration time, and the quantization results of adjacent frames have temporal correlation.
9. The readout circuit of claim 3, wherein the count-inversion unit counts the pulse signals, and obtains the count-inversion signal for a corresponding row based on a current count result and a previous count result.
10. An infrared imager, comprising: a current detector and a readout circuit as claimed in any one of claims 1 to 9.
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| CN101924558A (en) * | 2009-04-24 | 2010-12-22 | 索尼公司 | Binary conversion circuit and method, AD converter, solid-state imaging device and camera system |
| CN112866593A (en) * | 2021-01-06 | 2021-05-28 | 北京大学 | Pixel circuit and infrared imaging system |
| CN113091900A (en) * | 2021-03-01 | 2021-07-09 | 北京大学 | Reading circuit and infrared imager |
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| CN114245040A (en) | 2022-03-25 |
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