CN114237955A - Verification method and system for memory disambiguation in processor - Google Patents
Verification method and system for memory disambiguation in processor Download PDFInfo
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- CN114237955A CN114237955A CN202111541836.9A CN202111541836A CN114237955A CN 114237955 A CN114237955 A CN 114237955A CN 202111541836 A CN202111541836 A CN 202111541836A CN 114237955 A CN114237955 A CN 114237955A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
Abstract
The invention relates to the technical field of processors, in particular to a method and a system for verifying memory disambiguation in a processor. The invention verifies the logic of memory disambiguation and simultaneously supports single-core and multi-core memory disambiguation. The final result of memory disambiguation is whether the pipeline needs to be re-flushed and from which instruction the pipeline needs to be re-flushed.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a verification method and a verification system for memory disambiguation in a processor.
Background
In a high-performance out-of-order execution processor, memory access instructions are often executed out-of-order, load instructions can adopt a speculative execution strategy, and store instructions must be guaranteed to be written into a memory in sequence. After obtaining the physical address, the Load instruction may attempt to obtain data, and during the attempt, the Load instruction may search for a store instruction having an address correlation with itself, and if there is a store instruction having the same address and a younger address, the Load may obtain data directly from the store instruction. But there are also some store instructions that are older and have not yet been obtained by physical address, the load can first fetch data regardless of the store instructions, wait until the store instruction obtains the physical address, the store instruction needs to find whether there is a load instruction that has obtained data by being younger than the store instruction and the same physical address, and if so, the pipeline needs to be flushed, and the speculatively executed load instruction is re-executed because the load instruction obtains stale data. This operation is called memory disambiguation.
Another situation requiring memory disambiguation occurs in a multi-core system, if two load instructions of core 0 access the same address, but for some reason a younger load instruction executes first and gets data, then core 1 writes to the address, which changes the data, and then core 0 executes an older load instruction, which gets new data, and a younger load instruction gets stale data, which then requires flushing the pipeline to re-execute the younger load instruction.
In the conventional processor verification, aiming at a memory access module, independent modeling is carried out, and obtained access data are compared, but accurate verification of a micro-architecture of memory disambiguation is difficult to carry out, particularly in the multi-core system, the micro-architecture and the system need to be fully familiar with memory disambiguation verification, and related technologies are difficult to find in the market at present.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a verification method and a verification system for memory disambiguation in a processor, which are used for solving the problems.
The invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for verifying memory disambiguation in a processor, the method verifies memory disambiguation logic caused by single-core, multi-core, and non-aligned access by monitoring execution information of a load instruction and a store instruction in a DUT, and determines whether a pipeline needs to be re-flushed and from which instruction to start re-flushing by comparing a memory disambiguation result of the DUT with a memory disambiguation result of a checker, wherein if the pipeline re-flushing information is inconsistent with the DUT, error information is immediately reported.
Further, in the method, the single-core memory disambiguation includes memory disambiguation verification caused by a store instruction and memory disambiguation verification caused by a cache kick line.
Furthermore, in the method, the memory disambiguation verification process caused by the store instruction in the single core is as follows:
monitoring a store instruction in a DUT (device under test), and after the store instruction obtains a physical address, starting to search whether a load instruction meeting the condition exists in a core by a single-core memory disambiguation judger;
if there is a load instruction that satisfies the above conditions, the mononuclear memory disambiguation judger performs the following operations: comparing the age information of the load instructions to find out the oldest one; storing the selected load instruction information into the commit information of the store instruction, wherein the load instruction information comprises a mark or program counter information of the load instruction information in the instruction stream;
if no load instruction meeting the conditions exists, the single-core memory disambiguation judger invalidates the re-flushing pipeline information in the store instruction commit information;
monitoring commit information of the store instruction in the DUT, when the store instruction commit is carried out, comparing information of a re-flushing pipeline in the DUT commit information with a verified single-core memory disambiguation result by a comparator, if the information of the re-flushing pipeline is not consistent with the verified single-core memory disambiguation result, reporting an error, wherein the information of the error comprises whether the pipeline needs to be re-flushed, and if the pipeline needs to be re-flushed, starting the re-flushing from which load instruction.
Further, in the method, the load instruction satisfied is as follows:
the access range of the Load instruction is overlapped with the access range of the store instruction;
the Load instruction has acquired data;
the Load instruction is younger in the program order than the store instruction.
Further, in the method, a memory disambiguation verification process caused by a cache kick row in a single core is as follows:
monitoring whether a first-level cache line is kicked out in a DUT (device under test), if yes, starting to search whether two types of load instructions meeting conditions exist in a core by a single-core memory disambiguation judger;
if the first type of load instruction meets the condition, the load instruction mark needs to be refreshed by the pipeline flag bit:
the second type of load instruction, if the condition is satisfied, may need to bring the pipeline information to be flushed when the load instruction is commit:
finding out all load instructions which accord with the two types of conditions, and searching whether the second type of load instructions are older than the first type of load instructions;
if the situation exists, finding out one oldest load instruction which is younger than the second load instruction in the first load instruction, wherein the load instruction is the initial position of the pipeline needing to be refreshed, and the position information of the load instruction in the program is marked on the second load instruction;
if the condition does not exist, the memory disambiguation is not needed;
when memory disambiguation is needed, commit information of a second type of load instruction in the DUT is waited, when the load instruction commit is needed, the comparator compares the information of the pipeline of the DUT and the pipeline of the checker, if the information of the pipeline of the DUT and the pipeline of the checker is inconsistent, an error is reported, the error reporting information comprises whether the pipeline needs to be refreshed, and if the pipeline needs to be refreshed, the pipeline is refreshed from which load instruction.
Further, in the method, if the first type load instruction satisfies the condition:
the physical address of the Load instruction and the kicked cache line are the same cache line;
the Load instruction has acquired data;
the data of the Load instruction is not obtained from the core forward;
if the second type of load instruction meets the condition:
the physical address of the Load instruction and the kicked cache line are the same cache line;
load instructions have not yet acquired data.
Further, in the method, the multi-core memory disambiguation verification process includes:
monitoring a store instruction of each core in the multi-core system, and when data of the store instruction is visible by other cores, searching whether two types of load instructions meeting conditions exist in the other cores by a multi-core memory disambiguation judger;
if the first type of load instruction meets the condition, the load instruction mark needs to be refreshed by the pipeline flag bit:
if the second type of load instruction meets the condition, the load instruction needs to bring the pipeline information of the re-flushing when the load instruction is commit:
finding out all load instructions which accord with the two types of conditions in each core, and finding out whether the second type of load instructions are older than the first type of load instructions in the same core;
if the situation exists, finding out one oldest load instruction which is younger than the second load instruction in the first load instruction, wherein the load instruction is the initial position of the pipeline needing to be refreshed, and the position information of the load instruction in the program is marked on the second load instruction;
if the condition does not exist, the memory disambiguation is not needed;
when memory disambiguation is needed, commit information of a second type of load instruction in the DUT is waited, when the load instruction commit is needed, the information of the pipeline of the DUT and the checker is compared, if the information of the pipeline of the DUT and the pipeline of the checker is inconsistent, an error is reported, the error reporting information comprises whether the pipeline needs to be rewashed, and if the pipeline needs to be rewashed, the pipeline is rewashed from which load instruction.
Further, in the method, if the first type load instruction satisfies the condition:
the physical address of the Load instruction and the physical address of the store instruction are in the same cache line;
the Load instruction has acquired data;
the data of the Load instruction is not obtained from the core forward;
if the second type of load instruction meets the condition:
the physical address of the Load instruction and the physical address of the store instruction are in the same cache line;
the Load instruction has not yet acquired data.
Further, in the method, the memory disambiguation caused by the non-aligned access is verified as follows:
if the load instruction is non-aligned access, the processor divides the load access into two aligned accesses, and the checker processes the two accesses into two independent accesses to perform single-core and multi-core memory disambiguation check;
if the store instruction is a non-aligned access, the processor splits the store access into two aligned write operations, and the checker processes the two write operations into two independent write operations to perform single-core and multi-core memory disambiguation checking.
In a second aspect, the present invention provides a system for verifying memory disambiguation in a processor, where the system is used to implement the method for verifying memory disambiguation in a processor according to the first aspect, and the method includes
The memory access instruction monitor is used for monitoring the execution information of a load instruction and a store instruction in the DUT, wherein the execution information of the load instruction is stored in a load instruction queue of each core, and the execution information of the store instruction is simultaneously transmitted to the single-core memory disambiguation judger and the multi-core memory disambiguation judger;
the first-level cache monitor is used for monitoring whether a cache line is kicked out from the first-level cache or not and transmitting the information to the single-core memory disambiguation judger;
the commit information monitor is used for monitoring commit information of the load/store instruction in the DUT, comprises pipeline information which is refreshed in the commit information, is a result of disambiguation of the DUT memory, and is compared with a memory disambiguation result of the checker;
the single-core memory disambiguation judger is used for searching a load instruction queue of a corresponding core according to the input store instruction execution information and the first-level cache kicking-out information, judging whether the memory disambiguation condition is met, and finally outputting a single-core memory disambiguation result;
the multi-core memory disambiguation judger is used for searching load instruction queues of other cores according to the input store instruction execution information, judging whether the memory disambiguation conditions are met or not, and finally outputting a multi-core memory disambiguation result;
the load instruction queue of each core is used for storing load instruction execution information input by the access instruction monitor into the load instruction queue of the corresponding core, wherein the information comprises an access address of a load instruction, whether data are obtained or not, a data source and whether non-aligned access exists or not;
a comparator for comparing the memory disambiguation result of the DUT with the memory disambiguation result of the checker.
The invention has the beneficial effects that:
the invention verifies the logic of memory disambiguation and simultaneously supports single-core and multi-core memory disambiguation. The final result of memory disambiguation is whether the pipeline needs to be re-flushed and from which instruction the pipeline needs to be re-flushed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of a memory disambiguation verification architecture according to an embodiment of the invention;
FIG. 2 is a flow chart illustrating disambiguation verification of a single-core memory according to an embodiment of the invention;
FIG. 3 is a flowchart illustrating multi-core memory disambiguation verification according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The embodiment provides a method for verifying memory disambiguation in a processor, which verifies memory disambiguation logic caused by single-core, multi-core and non-aligned access by monitoring execution information of a load instruction and a store instruction in a DUT, and judges whether a pipeline needs to be re-flushed and from which instruction the pipeline needs to be re-flushed by comparing a memory disambiguation result of the DUT with a memory disambiguation result of a checker, wherein if the information of the re-flushed pipeline is inconsistent with the DUT, error information is immediately reported.
The method supports the verification of memory disambiguation under the condition of a single core, and comprises the memory disambiguation caused by a store instruction and the memory disambiguation caused by the kick-out of a first-level cache line.
The method supports memory disambiguation verification in a multi-core system, and the number of cores can be matched.
For a processor supporting non-aligned access, a load/store instruction may be split into two memory accesses, the memory disambiguation generated by the instruction is more complex, and the verification method supports verification of the memory disambiguation generated by the non-aligned access;
in the embodiment, the data comparison between the checker and the DUT is carried out when the access instruction commit, and the information is printed in real time, so that the verifier can quickly find the problem.
Example 2
On the basis of embodiment 1, this embodiment provides a memory disambiguation verification process caused by a store instruction in a single core, as shown in fig. 2, specifically as follows:
monitoring a store instruction in a DUT (device under test), and after the store instruction obtains a physical address, starting to search whether a load instruction meeting the following three conditions exists in a core by a single-core memory disambiguation judger;
a) the access range of the Load instruction is overlapped with the access range of the store instruction;
b) the Load instruction has acquired data;
c) the Load instruction is younger in the program order than the store instruction.
If there is a load instruction that satisfies the above conditions, the mononuclear memory disambiguation judger performs the following operations:
a) comparing the age information of the load instructions to find out the oldest one;
b) and storing the selected load instruction information into the commit information of the store instruction, wherein the load instruction information comprises a mark of the load instruction information in the instruction stream or program counter information, and the load instruction information is information of later refreshing the pipeline.
If no load instruction meeting the conditions exists, the single-core memory disambiguation judger invalidates the re-flushing pipeline information in the store instruction commit information;
monitoring commit information of the store instruction in the DUT, when the store instruction commit is carried out, comparing information of a re-flushing pipeline in the DUT commit information with a verified single-core memory disambiguation result by a comparator, if the information of the re-flushing pipeline is not consistent with the verified single-core memory disambiguation result, reporting an error, wherein the information of the error comprises whether the pipeline needs to be re-flushed, and if the pipeline needs to be re-flushed, starting the re-flushing from which load instruction.
Example 3
On the basis of embodiment 2, this embodiment provides a memory disambiguation verification process caused by cache kicking out of a line in a single core, as follows:
monitoring whether a first-level cache line is kicked out in a DUT (device under test), if yes, starting to search whether two types of load instructions meeting conditions exist in a core by a single-core memory disambiguation judger;
the first type of load instruction marks that the pipeline flag bit needs to be flushed if the following three conditions are met:
the physical address of the load instruction and the kicked cache line are the same cache line;
the load instruction has acquired data;
the data of the load instruction is not obtained from the local core forward;
the second type of load instruction may need to be flushed with pipeline information when the load instruction is commit if the following two conditions are met:
the physical address of the load instruction and the kicked cache line are the same cache line;
the load instruction has not yet acquired data;
finding out all load instructions which accord with the two types of conditions, and searching whether the second type of load instructions are older than the first type of load instructions;
if the situation exists, finding out one oldest load instruction which is younger than the second load instruction in the first load instruction, wherein the load instruction is the initial position of the pipeline needing to be refreshed, and the position information of the load instruction in the program is marked on the second load instruction;
if the condition does not exist, the memory disambiguation is not needed;
when memory disambiguation is needed, commit information of a second type of load instruction in the DUT is waited, when the load instruction commit is needed, the comparator compares the information of the pipeline of the DUT and the pipeline of the checker, if the information of the pipeline of the DUT and the pipeline of the checker is inconsistent, an error is reported, the error reporting information comprises whether the pipeline needs to be refreshed, and if the pipeline needs to be refreshed, the pipeline is refreshed from which load instruction.
Example 4
On the basis of embodiment 1, this embodiment provides a multi-core memory disambiguation verification process, which is shown in fig. 3 and specifically includes the following steps:
monitoring a store instruction of each core in the multi-core system, and when data of the store instruction is visible by other cores, searching whether two types of load instructions meeting conditions exist in the other cores by a multi-core memory disambiguation judger;
the first type of load instruction marks that the pipeline flag bit needs to be flushed if the following conditions are met:
the physical address of the load instruction and the physical address of the store instruction are in the same cache line;
the load instruction has obtained data;
data of the load instruction is not obtained from the core forward;
the second type of load instruction may need to be flushed with pipeline information when the load instruction is commit if the following conditions are met:
the physical address of the load instruction and the physical address of the store instruction are in the same cache line;
the load instruction has not yet acquired data;
finding out all load instructions which accord with the two types of conditions in each core, and finding out whether the second type of load instructions are older than the first type of load instructions in the same core;
if the situation exists, finding out one oldest load instruction which is younger than the second load instruction in the first load instruction, wherein the load instruction is the initial position of the pipeline needing to be refreshed, and the position information of the load instruction in the program is marked on the second load instruction;
if the condition does not exist, the memory disambiguation is not needed;
when memory disambiguation is needed, commit information of a second type of load instruction in the DUT is waited, when the load instruction commit is needed, the information of the pipeline of the DUT and the checker is compared, if the information of the pipeline of the DUT and the pipeline of the checker is inconsistent, an error is reported, the error reporting information comprises whether the pipeline needs to be rewashed, and if the pipeline needs to be rewashed, the pipeline is rewashed from which load instruction.
Example 5
On the basis of embodiment 1, this embodiment provides a memory disambiguation verification caused by non-aligned access, and the verification method is as follows:
if the load instruction is non-aligned access, the general processor divides the load access into two aligned accesses, and the checker processes the two accesses into two independent accesses to perform single-core and multi-core memory disambiguation check, wherein the difference is that when the pipeline information is marked to be refreshed again, the position information of the load instruction needs to be used;
if the store instruction is a non-aligned access, the general processor will split the store access into two aligned write operations, and the checker will also process the two write operations into two independent write operations to perform the above single-core and multi-core memory disambiguation check, except that when the refresh pipeline information is finally marked, the information needs to be marked in the information of the store instruction commit.
Example 6
The present embodiment provides a verification system for memory disambiguation in a processor, a structure diagram of which is shown in fig. 1, and the verification system includes a memory access instruction monitor, a first-level cache monitor, a commit information monitor, a single-core memory disambiguation determiner, a multi-core memory disambiguation determiner, a load instruction queue of each core, and a comparator. The function of each component is explained below.
The memory access instruction monitor is used for monitoring execution information of a load instruction and a store instruction in a DUT (device under test), wherein the execution information of the load instruction is stored in a load instruction queue of each core, and the execution information of the store instruction is simultaneously transmitted to a single-core memory disambiguation judger and a multi-core memory disambiguation judger.
The first-level cache monitor of the embodiment is used for monitoring whether a cache line is kicked out from the first-level cache or not and transmitting the information to the single-core memory disambiguation judger.
The commit information monitor of the embodiment is used for monitoring commit information of a load/store instruction in a DUT, and comprises the flushing pipeline information in the commit information, which is a result of memory disambiguation of the DUT and is used for comparing with a memory disambiguation result of a checker.
The single-core memory disambiguation determiner of this embodiment is configured to search a load instruction queue of a corresponding core according to input store instruction execution information and first-level cache kickout information, determine whether a memory disambiguation condition is met, and finally output a single-core memory disambiguation result.
The multi-core memory disambiguation determiner of this embodiment is configured to search the load instruction queues of the other cores according to the input store instruction execution information, determine whether the memory disambiguation condition is met, and finally output a multi-core memory disambiguation result.
The load instruction queue of each core in this embodiment is configured to store load instruction execution information input by the access instruction monitor into the load instruction queue of the corresponding core, where the information includes an access address of the load instruction, whether data has been obtained, a data source, whether non-aligned access is available, and the like.
The comparator of the present embodiment is used for comparing the memory disambiguation result of the DUT with the memory disambiguation result of the checker.
In summary, the present invention verifies the logic of memory disambiguation, and supports both single-core and multi-core memory disambiguation. The final result of memory disambiguation is whether the pipeline needs to be re-flushed and from which instruction the pipeline needs to be re-flushed.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A verification method for memory disambiguation in a processor is characterized in that the method verifies memory disambiguation logic caused by single-core, multi-core and non-aligned access by monitoring execution information of a load instruction and a store instruction in a DUT (device under test), judges whether a pipeline needs to be re-flushed and from which instruction the pipeline needs to be re-flushed by comparing a memory disambiguation result of the DUT with a memory disambiguation result of a checker, and immediately reports error information if the information of the re-flushed pipeline is inconsistent with the DUT.
2. The method of claim 1, wherein the single-core memory disambiguation comprises memory disambiguation verification caused by a store instruction and memory disambiguation verification caused by a cache kick line.
3. The method of claim 2, wherein the memory disambiguation verification caused by the store instruction in the single core is performed by:
monitoring a store instruction in a DUT (device under test), and after the store instruction obtains a physical address, starting to search whether a load instruction meeting the condition exists in a core by a single-core memory disambiguation judger;
if there is a load instruction that satisfies the above conditions, the mononuclear memory disambiguation judger performs the following operations: comparing the age information of the load instructions to find out the oldest one; storing the selected load instruction information into the commit information of the store instruction, wherein the load instruction information comprises a mark or program counter information of the load instruction information in the instruction stream;
if no load instruction meeting the conditions exists, the single-core memory disambiguation judger invalidates the re-flushing pipeline information in the store instruction commit information;
monitoring commit information of the store instruction in the DUT, when the store instruction commit is carried out, comparing information of a re-flushing pipeline in the DUT commit information with a verified single-core memory disambiguation result by a comparator, if the information of the re-flushing pipeline is not consistent with the verified single-core memory disambiguation result, reporting an error, wherein the information of the error comprises whether the pipeline needs to be re-flushed, and if the pipeline needs to be re-flushed, starting the re-flushing from which load instruction.
4. A method of validating memory disambiguation in a processor as claimed in claim 3, wherein the load instruction satisfied in said method is as follows:
the access range of the Load instruction is overlapped with the access range of the store instruction;
the Load instruction has acquired data;
the Load instruction is younger in the program order than the store instruction.
5. A method as claimed in claim 2, wherein the verification of memory disambiguation caused by cache kick out in a single core is performed by:
monitoring whether a first-level cache line is kicked out in a DUT (device under test), if yes, starting to search whether two types of load instructions meeting conditions exist in a core by a single-core memory disambiguation judger;
if the first type of load instruction meets the condition, the load instruction mark needs to be refreshed by the pipeline flag bit:
the second type of load instruction, if the condition is satisfied, may need to bring the pipeline information to be flushed when the load instruction is commit:
finding out all load instructions which accord with the two types of conditions, and searching whether the second type of load instructions are older than the first type of load instructions;
if the situation exists, finding out one oldest load instruction which is younger than the second load instruction in the first load instruction, wherein the load instruction is the initial position of the pipeline needing to be refreshed, and the position information of the load instruction in the program is marked on the second load instruction;
if the condition does not exist, the memory disambiguation is not needed;
when memory disambiguation is needed, commit information of a second type of load instruction in the DUT is waited, when the load instruction commit is needed, the comparator compares the information of the pipeline of the DUT and the pipeline of the checker, if the information of the pipeline of the DUT and the pipeline of the checker is inconsistent, an error is reported, the error reporting information comprises whether the pipeline needs to be refreshed, and if the pipeline needs to be refreshed, the pipeline is refreshed from which load instruction.
6. A method as claimed in claim 5, wherein said method comprises the step of, if the condition is satisfied:
the physical address of the Load instruction and the kicked cache line are the same cache line;
the Load instruction has acquired data;
the data of the Load instruction is not obtained from the core forward;
if the second type of load instruction meets the condition:
the physical address of the Load instruction and the kicked cache line are the same cache line;
load instructions have not yet acquired data.
7. The method of claim 1, wherein the multi-core memory disambiguation verification process comprises:
monitoring a store instruction of each core in the multi-core system, and when data of the store instruction is visible by other cores, searching whether two types of load instructions meeting conditions exist in the other cores by a multi-core memory disambiguation judger;
if the first type of load instruction meets the condition, the load instruction mark needs to be refreshed by the pipeline flag bit:
if the second type of load instruction meets the condition, the load instruction needs to bring the pipeline information of the re-flushing when the load instruction is commit:
finding out all load instructions which accord with the two types of conditions in each core, and finding out whether the second type of load instructions are older than the first type of load instructions in the same core;
if the situation exists, finding out one oldest load instruction which is younger than the second load instruction in the first load instruction, wherein the load instruction is the initial position of the pipeline needing to be refreshed, and the position information of the load instruction in the program is marked on the second load instruction;
if the condition does not exist, the memory disambiguation is not needed;
when memory disambiguation is needed, commit information of a second type of load instruction in the DUT is waited, when the load instruction commit is needed, the information of the pipeline of the DUT and the checker is compared, if the information of the pipeline of the DUT and the pipeline of the checker is inconsistent, an error is reported, the error reporting information comprises whether the pipeline needs to be rewashed, and if the pipeline needs to be rewashed, the pipeline is rewashed from which load instruction.
8. A method as claimed in claim 7, wherein if the condition is satisfied, the first type of load instruction is:
the physical address of the Load instruction and the physical address of the store instruction are in the same cache line;
the Load instruction has acquired data;
the data of the Load instruction is not obtained from the core forward;
if the second type of load instruction meets the condition:
the physical address of the Load instruction and the physical address of the store instruction are in the same cache line;
the Load instruction has not yet acquired data.
9. A method of verifying memory disambiguation in a processor according to claim 1, wherein the memory disambiguation due to non-aligned access is verified as follows:
if the load instruction is non-aligned access, the processor divides the load access into two aligned accesses, and the checker processes the two accesses into two independent accesses to perform single-core and multi-core memory disambiguation check;
if the store instruction is a non-aligned access, the processor splits the store access into two aligned write operations, and the checker processes the two write operations into two independent write operations to perform single-core and multi-core memory disambiguation checking.
10. A system for verifying memory disambiguation in a processor, said system being adapted to implement a method for verifying memory disambiguation in a processor according to any of claims 1-9, comprising
The memory access instruction monitor is used for monitoring the execution information of a load instruction and a store instruction in the DUT, wherein the execution information of the load instruction is stored in a load instruction queue of each core, and the execution information of the store instruction is simultaneously transmitted to the single-core memory disambiguation judger and the multi-core memory disambiguation judger;
the first-level cache monitor is used for monitoring whether a cache line is kicked out from the first-level cache or not and transmitting the information to the single-core memory disambiguation judger;
the commit information monitor is used for monitoring commit information of the load/store instruction in the DUT, comprises pipeline information which is refreshed in the commit information, is a result of disambiguation of the DUT memory, and is compared with a memory disambiguation result of the checker;
the single-core memory disambiguation judger is used for searching a load instruction queue of a corresponding core according to the input store instruction execution information and the first-level cache kicking-out information, judging whether the memory disambiguation condition is met, and finally outputting a single-core memory disambiguation result;
the multi-core memory disambiguation judger is used for searching load instruction queues of other cores according to the input store instruction execution information, judging whether the memory disambiguation conditions are met or not, and finally outputting a multi-core memory disambiguation result;
the load instruction queue of each core is used for storing load instruction execution information input by the access instruction monitor into the load instruction queue of the corresponding core, wherein the information comprises an access address of a load instruction, whether data are obtained or not, a data source and whether non-aligned access exists or not;
a comparator for comparing the memory disambiguation result of the DUT with the memory disambiguation result of the checker.
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